Search results for "DSPs"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
98	Gerhard P. Fettweis	DSPs: why don't they just go away!.	LCTES-SCOPES	2002	DBLP DOI BibTeX RDF
93	Peter Westermann, Ludwig Schwoerer, André Kaufmann	Applying Data Mapping Techniques to Vector DSPs.	J. Signal Process. Syst.	2009	DBLP DOI BibTeX RDF	Vector DSPs, Vectorizing compilers
70	Peter Westermann, Hartmut Schröder	Modeling Scalable SIMD DSPs in LISA.	SAMOS	2009	DBLP DOI BibTeX RDF	SIMD DSPs, Scalable Processor Models, LISA
65	Peter Westermann, Ludwig Schwoerer, André Kaufmann	Applying Data Mapping Techniques to Vector DSPs.	ICSAMOS	2007	DBLP DOI BibTeX RDF
65	Michael Hosemann, Gerhard P. Fettweis	On Enhancing SIMD-Controlled DSPs for Performing Recursive Filtering.	SAMOS	2004	DBLP DOI BibTeX RDF
59	Björn Franke, Michael F. P. O'Boyle	Compiler parallelization of C programs for multi-core DSPs with multiple address spaces.	CODES+ISSS	2003	DBLP DOI BibTeX RDF	address resolution, multiple address space compilation, DSPs, data partitioning
54	Michael Hosemann, Gerhard P. Fettweis	On Enhancing SIMD-controlled DSPs for Performing Recursive Filtering.	J. VLSI Signal Process.	2006	DBLP DOI BibTeX RDF
54	Markus Lorenz, Peter Marwedel	Phase Coupled Code Generation for DSPs Using a Genetic Algorithm.	DATE	2004	DBLP DOI BibTeX RDF
54	Jie Guo 0007, Michael Hosemann, Gerhard P. Fettweis	Employing Compilers for Determining Architectural Features of Application-Specific DSPs.	PARELEC	2004	DBLP DOI BibTeX RDF
54	Paul S. Graham, Brent E. Nelson	Frequency-Domain Sonar Processing in FPGAs and DSPs.	FCCM	1998	DBLP DOI BibTeX RDF
44	V. Parthasarathy, S. Aram valartha Bharathi, V. Rhymend Uthariaraj	Performance Analysis of Embedded Media Applications in Newer ARM Architectures.	ICPP Workshops	2005	DBLP DOI BibTeX RDF	ARM v6, DSP Extensions, Instruction set architecture (ISA), Single Instruction Multiple Data (SIMD)
44	Jeonghun Cho, Yunheung Paek, David B. Whalley	Fast memory bank assignment for fixed-point digital signal processors.	ACM Trans. Design Autom. Electr. Syst.	2004	DBLP DOI BibTeX RDF	dual memory banks, nonorthogonal architecture, Compiler, DSP, dependence analysis, maximum spanning tree
44	Gene Frantz	Digital Signal Processor Trends.	IEEE Micro	2000	DBLP DOI BibTeX RDF
43	Jintao Wang, Rui Lv, Pengdong Gao, Yongquan Lu, Chu Qiu, Wenhua Yu	The Design of HDTV H.264 Encoding System Based on Multi-DSPs Architecture.	CSSE (4)	2008	DBLP DOI BibTeX RDF
43	Gary Gréwal, Stelian Coros, Dilip K. Banerji, Andrew Morton	Assigning data to dual memory banks in DSPs with a genetic algorithm using a repair heuristic.	Appl. Intell.	2007	DBLP DOI BibTeX RDF	Memory assignment, Repair method, Genetic algorithm, Multi-Objective optimization, Embedded processors
43	Dan Zhang, Zeng-zhi Li, Hai Wang, Tao Zhan	A Novel Genetic Algorithm for Variable Partition of Dual Memory Bank DSPs.	ICNC (3)	2005	DBLP DOI BibTeX RDF
43	Siddharth Rele, Vipin Jain, Santosh Pande, J. Ramanujam	Compact and efficient code generation through program restructuringon limited memory embedded DSPs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
43	Rainer Leupers	Instruction Scheduling for Clustered VLIW DSPs.	IEEE PACT	2000	DBLP DOI BibTeX RDF
43	Naji Ghazal, A. Richard Newton, Jan M. Rabaey	Predicting performance potential of modern DSPs.	DAC	2000	DBLP DOI BibTeX RDF
43	Rainer Leupers, Peter Marwedel	Time-constrained code compaction for DSPs.	IEEE Trans. Very Large Scale Integr. Syst.	1997	DBLP DOI BibTeX RDF
43	Marcos Luiz Mucheroni, Célio Estevan Morón, José Hiroki Saito	ArchMDSP: using DSPs for parallel image processing.	EUROMICRO	1997	DBLP DOI BibTeX RDF	ArchMDSP, image mapping, real-time problems, fault-tolerant problems, sub-image distribution available, Sun SparcStation, Sbus, multiple-module carrier card, TMS320C40 processors, timing measurements, 8 Mbyte, parallel architecture, parallel machines, parallel machine, speedup, operators, digital signal processors, communication overhead, parallel programming environment, image size, pipeline structure, parallel image processing
39	Desiree Ottoni, Guilherme Ottoni, Guido Araujo, Rainer Leupers	Offset assignment using simultaneous variable coalescing.	ACM Trans. Embed. Comput. Syst.	2006	DBLP DOI BibTeX RDF	Stack offset assignment, address registers, autoincrement addressing modes, variable coalescing, DSPs, register allocation
33	M. Van Der Horst, Kees van Berkel 0001, Johan Lukkien, Rudolf H. Mak	Recursive Filtering on a Vector DSP with Linear Speedup.	ASAP	2005	DBLP DOI BibTeX RDF
33	Ross Snider, Yongming Zhu	Developing a Data Driven System for Computational Neuroscience.	International Conference on Computational Science	2004	DBLP DOI BibTeX RDF
33	Yuhei Kaneko, Nobuhiko Sugino, Akinori Nishihara	Memory allocation method for indirect addressing with an index register.	APCCAS (1)	2002	DBLP DOI BibTeX RDF
33	Sadagopan Srinivasan, Vinodh Cuppu, Bruce L. Jacob	Transparent data-memory organizations for digital signal processors.	CASES	2001	DBLP DOI BibTeX RDF
33	Sungjoon Jung, Yunheung Paek	The very portable optimizer for digital signal processors.	CASES	2001	DBLP DOI BibTeX RDF
33	Adrian Johnstone, Elizabeth Scott, Tim Womack	Experience Paper: Reverse Compilation of Digital Signal Processor Assembler Source to ANSI-C.	ICSM	1999	DBLP DOI BibTeX RDF	reverse compilation, low to high level language translation, digital signal processing
33	Mazen A. R. Saghir, Paul Chow, Corinna G. Lee	Exploiting Dual Data-Memory Banks in Digital Signal Processors.	ASPLOS	1996	DBLP DOI BibTeX RDF
32	Chun Jason Xue, Tiantian Liu 0001, Zili Shao, Jingtong Hu, Zhiping Jia, Weijia Jia 0001, Edwin Hsing-Mean Sha	Address assignment sensitive variable partitioning and scheduling for DSPS with multiple memory banks.	ICASSP	2008	DBLP DOI BibTeX RDF
32	Doosan Cho, Ravi Ayyagari, Gang-Ryung Uh, Yunheung Paek	Instruction Re-selection for Iterative Modulo Scheduling on High Performance Multi-issue DSPs.	EUC Workshops	2006	DBLP DOI BibTeX RDF
32	Partha Biswas, Nikil D. Dutt	Code Size Reduction in Heterogeneous-Connectivity-Based DSPs Using Instruction Set Extensions.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	DSP, VLIW, ASIP, Coprocessors, instruction set extensions, code size reduction
32	Bharath Iyer, Sadagopan Srinivasan, Bruce L. Jacob	Extended Split-Issue: Enabling Flexibility in the Hardware Implementation of NUAL VLIW DSPs.	ISCA	2004	DBLP DOI BibTeX RDF
32	Viera Sipková	Efficient Variable Allocation to Dual Memory Banks of DSPs.	SCOPES	2003	DBLP DOI BibTeX RDF
32	Partha Biswas, Nikil D. Dutt	Reducing code size for heterogeneous-connectivity-based VLIW DSPs through synthesis of instruction set extensions.	CASES	2003	DBLP DOI BibTeX RDF	dependence conflict graph, heterogeneous-connectivity-based DSP, restricted data dependence graph, instruction set extensions, instruction set architecture, static single assignment
32	Markus Lorenz, Lars Wehmeyer, Thorsten Dräger	Energy aware compilation for DSPs with SIMD instructions.	LCTES-SCOPES	2002	DBLP DOI BibTeX RDF	zero overhead hardware loop, DSP, vectorization, energy minimization, SIMD instruction
32	Eugenio Suárez Cáner, José Manoel de Seixas, Rodrigo Coura Torres	A Development Environment for Multilayer Neural Network Applications Mapped onto DSPs with Multiprocessing Capabilities.	VECPAR	2002	DBLP DOI BibTeX RDF
32	Nagisa Ishiura, Tatsuo Watanabe	Datapath oriented codesign method of application specific DSPs using retargetable compiler.	APCCAS (1)	2002	DBLP DOI BibTeX RDF
32	Subramanian Rajagopalan, Sreeranga P. Rajan, Sharad Malik, Sandro Rigo, Guido Araujo, Koichiro Takayama	A retargetable VLIW compiler framework for DSPs withinstruction-level parallelism.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
32	Gary William Grewal, Thomas Charles Wilson	Mapping reference code to irregular DSPs within the retargetable, optimizing compiler COGEN(T).	MICRO	2001	DBLP DOI BibTeX RDF
32	Markus Lorenz, David Koffmann, Steven Bashford, Rainer Leupers, Peter Marwedel	Optimized address assignment for DSPs with SIMD memory accesses.	ASP-DAC	2001	DBLP DOI BibTeX RDF
32	Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh 0001	Low-power realization of FIR filters on programmable DSPs.	IEEE Trans. Very Large Scale Integr. Syst.	1998	DBLP DOI BibTeX RDF
32	Guido Araujo, Sharad Malik	Code generation for fixed-point DSPs.	ACM Trans. Design Autom. Electr. Syst.	1998	DBLP DOI BibTeX RDF	scheduling, code generation, register allocation
32	Jan M. Rabaey, Marlene Wan	An Energy-Conscious Exploration Methodology for Reconfigurable DSPs.	DATE	1998	DBLP DOI BibTeX RDF
32	Thomas Charles Wilson, Gary William Grewal	Shake And Bake: A Method of Mapping Code to Irregular DSPs.	VLSI Design	1997	DBLP DOI BibTeX RDF
32	Gary William Grewal	A Global Mode Instruction Minimization Technique for Embedded DSPs.	Great Lakes Symposium on VLSI	1996	DBLP DOI BibTeX RDF
32	Rainer Leupers, Peter Marwedel	Time-constrained code compaction for DSPs.	ISSS	1995	DBLP DOI BibTeX RDF	code generation techniques, digital signal processing algorithms, encoding restrictions, exact timing behavior, hard real-time constraints, integer programming model, local code compaction, programmable DSP, rigid heuristics, time-constrained code compaction, real-time systems, timing, integer programming, instruction-level parallelism, source coding, automatic programming, digital signal processing chips, side-effects
32	Edward A. Lee, E. Goei, H. Heine, W.-H. Ho, Shuvra S. Bhattacharyya, Jeffery C. Bier, E. Guntvedt	GABRIEL: A Design Environment for Programmable DSPs.	DAC	1989	DBLP DOI BibTeX RDF
27	Atsushi Ishii, Toyotaro Suzumura	Elastic Stream Computing with Clouds.	IEEE CLOUD	2011	DBLP DOI BibTeX RDF	SPADE, Amazon EC2, Cloud, Dynamic Load Balancing, DSMS, Data Stream Processing, System S, DSPS
27	Guido Araujo, Guilherme Ottoni, Marcelo Silva Cintra	Global array reference allocation.	ACM Trans. Design Autom. Electr. Syst.	2002	DBLP DOI BibTeX RDF	Address registers, auto-increment addressing modes, DSPs, register allocation
22	André Ludwig, Marek Kowalkiewicz	Supporting Service Level Agreement Creation with Past Service Behavior Data.	BIS (Workshops)	2009	DBLP DOI BibTeX RDF	Dynamic Service Profiling, Service behavior, Service Level Agreement, Contracting
22	Hong Liu 0002, Ke Wu, Peter Meusel, Nikolaus Seitz, Gerd Hirzinger, M. H. Jin, Yiwei Liu, Shaowei Fan, T. Lan, Zhaopeng Chen	Multisensory five-finger dexterous hand: The DLR/HIT Hand II.	IROS	2008	DBLP DOI BibTeX RDF
22	Gian Carlo Cardarilli, Luca Di Nunzio, Marco Re, Alberto Nannarelli	ADAPTO: full-adder based reconfigurable architecture for bit level operations.	ISCAS	2008	DBLP DOI BibTeX RDF
22	Hangpei Tian, Deyuan Gao, Deli Wang, Yian Zhu, Shengbing Zhang, Jing Wang	Dynamically Reconfigurable Instruction Set for Software Radio Encoding/Coding.	MUE	2008	DBLP DOI BibTeX RDF	Instruction Set, Software Radio
22	Yi-Hsuan Lee, Cheng Chen	An Efficient Code Generation Algorithm for Non-orthogonal DSP Architecture.	J. VLSI Signal Process.	2007	DBLP DOI BibTeX RDF	non-orthogonal architecture, code generation, DSP
22	Doosan Cho, Ravi Ayyagari, Gang-Ryung Uh, Yunheung Paek	Preprocessing Strategy for Effective Modulo Scheduling on Multi-issue Digital Signal Processors.	CC	2007	DBLP DOI BibTeX RDF
22	Muhammet Fikret Ercan	Parallel Image Understanding on a Multi-DSP System.	ICCSA (2)	2007	DBLP DOI BibTeX RDF
22	Ozcan Ozturk 0001, Mahmut T. Kandemir, Suleyman Tosun	An ILP based approach to address code generation for digital signal processors.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	code generation, DSP, integer linear programming
22	Takashi Shono, Yushi Shirato, Hiroyuki Shiba, Kazuhiro Uehara, Katsuhiko Araki, Masahiro Umehira	IEEE 802.11 wireless LAN implemented on software defined radio with hybrid programmable architecture.	IEEE Trans. Wirel. Commun.	2005	DBLP DOI BibTeX RDF
22	Björn Franke, Michael F. P. O'Boyle	A Complete Compiler Approach to Auto-Parallelizing C Programs for Multi-DSP Systems.	IEEE Trans. Parallel Distributed Syst.	2005	DBLP DOI BibTeX RDF	conversion from sequential to parallel forms, modeling, evaluation, compilers, measurement, performance measures, interprocessor communications, arrays, real-time and embedded systems, restructuring, Parallel processors, simulation of multiple-processor systems, reverse engineering and reengineering, signal processing systems
22	Gordon Cichon, Pablo Robelly, Hendrik Seidel, Emil Matús, Marcus Bronzel, Gerhard P. Fettweis	Synchronous Transfer Architecture (STA).	SAMOS	2004	DBLP DOI BibTeX RDF
22	Kees A. Vissers	Programming models and architectures for FPGA platforms.	CASES	2004	DBLP DOI BibTeX RDF
22	John Y. Oliver, Ravishankar Rao, Paul Sultana, Jedidiah R. Crandall, Erik Czernikowski, Leslie W. Jones IV, Diana Franklin, Venkatesh Akella, Frederic T. Chong	Synchroscalar: A Multiple Clock Domain, Power-Aware, Tile-Based Embedded Processor.	ISCA	2004	DBLP DOI BibTeX RDF
22	Jae C. Oh, Madhura S. Tamhankar, Daniel Mossé	Design of Very Lightweight Agents for Reactive Embedded Systems.	ECBS	2003	DBLP DOI BibTeX RDF
22	Björn Franke, Michael F. P. O'Boyle	Combining Program Recovery, Auto-Parallelisation and Locality Analysis for C Programs on Multi-Processor Embedded Systems.	IEEE PACT	2003	DBLP DOI BibTeX RDF
22	Erik Eckstein, Bernhard Scholz	Addressing Mode Selection.	CGO	2003	DBLP DOI BibTeX RDF
22	Heiko Michel, Alexander Worm, Norbert Wehn, Michael Münch	Hardware/Software Trade-Offs for Advanced 3G Channel Coding.	DATE	2002	DBLP DOI BibTeX RDF
22	Christoph W. Keßler, Andrzej Bednarski	A Dynamic Programming Approach to Optimal Integrated Code Generation.	LCTES/OM	2001	DBLP DOI BibTeX RDF	integrated code generation, time profile, dynamic programming, register allocation, instruction scheduling, instruction selection
22	Ashok Sudarsanam, Sharad Malik	Simultaneous reference allocation in code generation for dual data memory bank ASIPs.	ACM Trans. Design Autom. Electr. Syst.	2000	DBLP DOI BibTeX RDF	memory bank assignment, code generation, register allocation, code optimization, graph labelling
22	David W. Currie, Alan J. Hu, Sreeranga P. Rajan	Automatic formal verification of DSP software.	DAC	2000	DBLP DOI BibTeX RDF
22	Anupam Basu, Rainer Leupers, Peter Marwedel	Register-Constrained Address Computation in DSP Programs.	DATE	1998	DBLP DOI BibTeX RDF	DSP compiler, address computation, embedded processors
22	Shuvra S. Bhattacharyya, Edward A. Lee	Scheduling synchronous dataflow graphs for efficient looping.	J. VLSI Signal Process.	1993	DBLP DOI BibTeX RDF
21	Yang Wang, Qinglin Wang, Xiangdong Pei, Songzhu Mei, Rongchun Li, Jie Liu 0002	High performance dilated convolutions on multi-core DSPs.	CCF Trans. High Perform. Comput.	2024	DBLP DOI BibTeX RDF
21	Wei Tang 0010, Sung-Gun Cho, Tim Tri Hoang, Jacob Botimer, Wei Qiang Zhu, Ching-Chi Chang, Cheng-Hsun Lu, Junkang Zhu, Yaoyu Tao, Tianyu Wei, Naomi Kavi Motwani, Mani Yalamanchi, Ramya Yarlagadda, Sirisha Kale, Mark Flannigan, Allen Chan, Thungoc Tran, Sergey Y. Shumarayev, Zhengya Zhang	Arvon: A Heterogeneous SiP Integrating a 14nm FPGA and Two 22nm 1.8TFLOPS/W DSPs with 1.7Tbps/mm2 AIB 2.0 Interface to Provide Versatile Workload Acceleration.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
21	Deshun Bi, Xiaowen Tian, Shengguo Li, Dezun Dong	Efficiently Running SpMV on Multi-Core DSPs for Block Sparse Matrix.	ICPADS	2023	DBLP DOI BibTeX RDF
21	Yufei Guo, Xinjie An, Shijie Li, Yingbo Cui, Peng Zhang, Biao Long, Shanshan Li	MTMap: A Long-Read Alignment Tool based on Multi-Core DSPs.	BIBM	2023	DBLP DOI BibTeX RDF
21	Yang Wang, Qinglin Wang, Xiangdong Pei, Songzhu Mei, Jie Liu 0002	Optimizing Pointwise Convolutions on Multi-core DSPs.	ICA3PP (7)	2023	DBLP DOI BibTeX RDF
21	Deshun Bi, Shengguo Li, Yichen Zhang, Xiaojian Yang, Dezun Dong	Efficiently Running SpMV on Multi-core DSPs for Banded Matrix.	ICA3PP (5)	2023	DBLP DOI BibTeX RDF
21	Xiaolei Zhao, Zhaoyun Chen, Yang Shi, Mei Wen, Chunyun Zhang	Automatic End-to-End Joint Optimization for Kernel Compilation on DSPs.	DAC	2023	DBLP DOI BibTeX RDF
21	Shangfei Yin, Qinglin Wang, Ruochen Hao, Tianyang Zhou, Songzhu Mei, Jie Liu 0002	Optimizing Irregular-Shaped Matrix-Matrix Multiplication on Multi-Core DSPs.	CoRR	2022	DBLP DOI BibTeX RDF
21	Shun Orita, Akiko Narita, Kenji Ichijo	Design of Multicore Dataflow DSPs with Different Loop Iteration Mechanisms.	ICCE-TW	2022	DBLP DOI BibTeX RDF
21	Wei Niu 0002, Jiexiong Guan, Xipeng Shen, Yanzhi Wang, Gagan Agrawal, Bin Ren	GCD2: A Globally Optimizing Compiler for Mapping DNNs to Mobile DSPs.	MICRO	2022	DBLP DOI BibTeX RDF
21	Bowen Zhu, Yanyi Wang, Weiping Li, Feng Wang, Jiaxuan Liu, Jianjun Yu	40-Gbit/s W-band Signal Delivery over 4600-m Wireless Distance Employing Advanced DSPs.	ICC Workshops	2022	DBLP DOI BibTeX RDF
21	Elliott Wen, Jiaxing Shen	DSPBooster: Offloading Unmodified Mobile Applications to DSPs for Power-performance Optimal Execution.	COMPSAC	2022	DBLP DOI BibTeX RDF
21	Rafael Romón Sagredo, Erik Börjeson, Ali Mirani, Magnus Karlsson 0001, Per Larsson-Edefors	Waveform Memory for Real-Time FPGA Test of Fiber-Optic Receiver DSPs.	NorCAS	2022	DBLP DOI BibTeX RDF
21	Ankita Shah, Uma Shanker Tiwary	Dominance Submissiveness Predisposition Scale (DSPS): Development and Validation.	ICHI	2022	DBLP DOI BibTeX RDF
21	Shangfei Yin, Qinglin Wang, Ruochen Hao, Tianyang Zhou, Songzhu Mei, Jie Liu 0002	Optimizing Irregular-Shaped Matrix-Matrix Multiplication on Multi-Core DSPs.	CLUSTER	2022	DBLP DOI BibTeX RDF
21	David Uzan, Roger Kahn, Shlomo Weiss	Perceptron based filtering of futile prefetches in embedded VLIW DSPs.	J. Syst. Archit.	2020	DBLP DOI BibTeX RDF
21	Elif Bilge Kavun, Nele Mentens, Jo Vliegen, Tolga Yalçin	Efficient Utilization of DSPs and BRAMs Revisited: New AES-GCM Recipes on FPGAs.	IACR Cryptol. ePrint Arch.	2019	DBLP BibTeX RDF
21	Elif Bilge Kavun, Nele Mentens, Jo Vliegen, Tolga Yalçin	Efficient Utilization of DSPs and BRAMs Revisited: New AES-GCM Recipes on FPGAs.	ReConFig	2019	DBLP DOI BibTeX RDF
21	Rui Qin 0002, Yong Yuan, Fei-Yue Wang 0001	Exploring Optimal Revenue Models For DSPs In Real Time Bidding Advertising.	SOLI	2019	DBLP DOI BibTeX RDF
21	Amir HajiRassouliha, Andrew J. Taberner, Martyn P. Nash, Poul M. F. Nielsen	Suitability of recent hardware accelerators (DSPs, FPGAs, and GPUs) for computer vision and image processing algorithms.	Signal Process. Image Commun.	2018	DBLP DOI BibTeX RDF
21	Yuan Li, Wei Li 0032, Lu Li 0005	Hyperspectral Anomaly Dectection on Multicore DSPs.	CISP-BMEI	2018	DBLP DOI BibTeX RDF
21	Amine Mrabet, Nadia El Mrabet, Ronan Lashermes, Jean-Baptiste Rigaud, Belgacem Bouallegue, Sihem Mesnager, Mohsen Machhout	A Scalable and Systolic Architectures of Montgomery Modular Multiplication for Public Key Cryptosystems Based on DSPs.	J. Hardw. Syst. Secur.	2017	DBLP DOI BibTeX RDF
21	Sander Vocke, Henk Corporaal, Roel Jordans, Rosilde Corvino, Rick J. M. Nas	Extending Halide to Improve Software Development for Imaging DSPs.	ACM Trans. Archit. Code Optim.	2017	DBLP DOI BibTeX RDF
21	Rui Chang, Jun Wu 0006, Haoqi Ren	A compilation method for zero overhead loop in DSPs with VLIW.	WCSP	2017	DBLP DOI BibTeX RDF
21	Shiming Sun, Hongxu Jiang, Bo Li 0006	An efficient Markov chain-based data prefetching for motion estimation of HEVC on multi-core DSPs.	Multim. Tools Appl.	2016	DBLP DOI BibTeX RDF
21	Sheng Liu 0001, Haiyan Chen, Jianghua Wan, Yaohua Wang	Mod (2P-1) Shuffle Memory-Access Instructions for FFTs on Vector SIMD DSPs.	ISVLSI	2016	DBLP DOI BibTeX RDF
21	Amine Mrabet, Nadia El Mrabet, Ronan Lashermes, Jean-Baptiste Rigaud, Belgacem Bouallegue, Sihem Mesnager, Mohsen Machhout	A Scalable and Systolic Architectures of Montgomery Modular Multiplication for Public Key Cryptosystems Based on DSPs.	SPACE	2016	DBLP DOI BibTeX RDF
21	Xiangyang Liu, Hua Bao	Efficient Implementation of 2-D FCT with Reduced Memory Access for Programmable DSPs.	J. Signal Process. Syst.	2015	DBLP DOI BibTeX RDF