Search results for "FPU"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
99	Yee Jern Chong, Sri Parameswaran	Flexible multi-mode embedded floating-point unit for field programmable gate arrays.	FPGA	2009	DBLP DOI BibTeX RDF	dual-precision, embedded block, fpu, fpga, floating-point, fpga architecture
85	Yongsoon Lee, Seok-Bum Ko	FPGA Implementation of a Face Detector using Neural Networks.	CCECE	2006	DBLP DOI BibTeX RDF
77	In-hye Seo, Heau-Jo Kang, Tai-Hoon Kim	Performance Analysis of Adaptive Digital FPU Transmission System in Fading Environment.	ICIC (1)	2006	DBLP DOI BibTeX RDF
68	Kingshuk Karuri, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Monu Kedia	Design and implementation of a modular and portable IEEE 754 compliant floating-point unit.	DATE Designers' Forum	2006	DBLP DOI BibTeX RDF
68	Ajay Naini, Atul Dhablania, Warren James, Debjit Das Sarma	1-GHz HAL SPARC64 Dual Floating Point Unit with RAS Features.	IEEE Symposium on Computer Arithmetic	2001	DBLP DOI BibTeX RDF
52	Dmitry E. Pelinovsky, Guido Schneider	The monoatomic FPU system as a limit of a diatomic FPU system.	Appl. Math. Lett.	2020	DBLP DOI BibTeX RDF
52	Jing Pu, Sameh Galal, Xuan Yang, Ofer Shacham, Mark Horowitz	FPMax: a 106GFLOPS/W at 217GFLOPS/mm2 Single-Precision FPU, and a 43.7GFLOPS/W at 74.6GFLOPS/mm2 Double-Precision FPU, in 28nm UTBB FDSOI.	CoRR	2016	DBLP BibTeX RDF
51	Yee Jern Chong, Sri Parameswaran	Automatic application specific floating-point unit generation.	DATE	2007	DBLP DOI BibTeX RDF
51	Silvia M. Müller, Christian Jacobi 0002, Hwa-Joon Oh, Kevin D. Tran, Scott R. Cottier, Brad W. Michael, Hiroo Nishikawa, Yonetaro Totsuka, Tatsuya Namatame, Naoka Yano, Takashi Machida, Sang H. Dhong	The Vector Floating-Point Unit in a Synergistic Processor Element of a CELL Processor.	IEEE Symposium on Computer Arithmetic	2005	DBLP DOI BibTeX RDF
51	Leonardo R. Bachega, Siddhartha Chatterjee, Kenneth A. Dockser, John A. Gunnels, Manish Gupta 0002, Fred G. Gustavson, Christopher A. Lapkowski, Gary K. Liu, Mark P. Mendell, Charles D. Wait, T. J. Christopher Ward	A High-Performance SIMD Floating Point Unit for BlueGene/L: Architecture, Compilation, and Algorithm Design.	IEEE PACT	2004	DBLP DOI BibTeX RDF
51	Zhenyu Tang, Lei He 0001, Norman Chang, Shen Lin, Weize Xie, O. Sam Nakagawa	Instruction Prediction for Step Power Reduction.	ISQED	2001	DBLP DOI BibTeX RDF
51	Zhenyu Tang, Norman Chang, Shen Lin, Weize Xie, O. Sam Nakagawa, Lei He 0001	Ramp Up/Down Functional Unit to Reduce Step Power.	PACS	2000	DBLP DOI BibTeX RDF
34	Seyed Mohammad Hossein Shekarian, Alireza Ejlali, Seyed Ghassem Miremadi	A Low Power Error Detection Technique for Floating-Point Units in Embedded Applications.	EUC (1)	2008	DBLP DOI BibTeX RDF
34	Yee Jern Chong, Sri Parameswaran	Rapid application specific floating-point unit generation with bit-alignment.	DAC	2008	DBLP DOI BibTeX RDF	bit-alignment, datapath merging, floating-point
34	Thomas Y. Yeh, Petros Faloutsos, Milos D. Ercegovac, Sanjay J. Patel, Glenn Reinman	The Art of Deception: Adaptive Precision Reduction for Area Efficient Physics Acceleration.	MICRO	2007	DBLP DOI BibTeX RDF
34	J. Gonzalez-Gomez, Iván González, Francisco J. Gomez-Arribas, Eduardo I. Boemo	Evaluation of a Locomotion Algorithm for Worm-Like Robots on FPGA-Embedded Processors.	ARC	2006	DBLP DOI BibTeX RDF
34	Neil Burgess	Prenormalization rounding in IEEE floating-point operations using a flagged prefix adder.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
34	Christian Jacobi 0002, Christoph Berg	Formal Verification of the VAMP Floating Point Unit.	Formal Methods Syst. Des.	2005	DBLP DOI BibTeX RDF	IEEE standard 754, formal verification, theorem proving, PVS, floating point unit
34	Christian Jacobi 0002, Kai Weber 0001, Viresh Paruthi, Jason Baumgartner	Automatic Formal Verification of Fused-Multiply-Add FPUs.	DATE	2005	DBLP DOI BibTeX RDF
34	Marc Epalza, Paolo Ienne, Daniel Mlynek	Adding Limited Reconfigurability to Superscalar Processors.	IEEE PACT	2004	DBLP DOI BibTeX RDF
34	Jens Peter Wittenburg, Ulrich Schreiber, Ulrich Gries, Markus Schneider 0003, Tim Niggemeier	A Cost-Efficient RISC Processor Platform for Real Time Audio Applications.	SAMOS	2004	DBLP DOI BibTeX RDF
34	Eric M. Schwarz, Ronald M. Smith, Christopher A. Krygowski	The S/390 G5 Floating Point Unit Supporting Hex and Binary Architectures.	IEEE Symposium on Computer Arithmetic	1999	DBLP DOI BibTeX RDF
32	David Monniaux	The pitfalls of verifying floating-point computations.	ACM Trans. Program. Lang. Syst.	2008	DBLP DOI BibTeX RDF	AMD64, FPU, IA32, x87, Verification, Static analysis, Abstract interpretation, Program testing, Embedded software, Floating point, Safety-Critical Software, Rounding, PowerPC, IEEE-754
32	Michael J. Beauchamp, Scott Hauck, Keith D. Underwood, K. Scott Hemmert	Embedded floating-point units in FPGAs.	FPGA	2006	DBLP DOI BibTeX RDF	FPU, FPGA, floating-point, FPGA architecture
26	Lyle Parsons, Guang Deng, Robert Ross	Detecting image edges in IOT nodes without FPU.	Multim. Tools Appl.	2024	DBLP DOI BibTeX RDF
26	Bastian Hilder, Björn de Rijk, Guido Schneider	Moving Modulating Pulse and Front Solutions of Permanent Form in a FPU Model with Nearest and Next-to-Nearest Neighbor Interaction.	SIAM J. Appl. Dyn. Syst.	2023	DBLP DOI BibTeX RDF
26	Chris Keilbart, Yuhui Gao, Martin Chua, Eric Matthews, Steven J. E. Wilton, Lesley Shannon	Designing a configurable IEEE-compliant FPU that supports variable precision for soft processors.	FCCM	2023	DBLP DOI BibTeX RDF
26	Jina Park, Kyuseung Han, Eunjin Choi, Sukho Lee, Jae-Jin Lee, Woojoo Lee, Massoud Pedram	Florian: Developing a Low-Power RISC-V Multicore Processor with a Shared Lightweight FPU.	ISLPED	2023	DBLP DOI BibTeX RDF
26	Sridutt Bhalachandra, Brian Austin, Samuel Williams 0001, Nicholas J. Wright	Understanding the Impact of Input Entropy on FPU, CPU, and GPU Power.	CoRR	2022	DBLP DOI BibTeX RDF
26	Henry Duran, Jesús Cuevas-Maraver, Panayotis G. Kevrekidis, Anna Vainchtein	Moving discrete breathers in a β-FPU lattice revisited.	Commun. Nonlinear Sci. Numer. Simul.	2022	DBLP DOI BibTeX RDF
26	Won Jeon, Yong Cheol Peter Cho, Hyun-Mi Kim, Hyeji Kim, Jaehoon Chung, Ju-Yeob Kim, Miyoung Lee, Chun-Gi Lyuh, Jinho Han, Youngsu Kwon	M3FPU: Multiformat Matrix Multiplication FPU Architectures for Neural Network Computations.	AICAS	2022	DBLP DOI BibTeX RDF
26	Davide Zoni, Andrea Galimberti, William Fornaciari	An FPU design template to optimize the accuracy-efficiency-area trade-off.	Sustain. Comput. Informatics Syst.	2021	DBLP DOI BibTeX RDF
26	Peng Chen	Periodic motion for FPU lattice dynamical systems with the strongly indefinite case.	Appl. Math. Lett.	2021	DBLP DOI BibTeX RDF
26	Chiara Caracciolo, Ugo Locatelli	Elliptic tori in FPU non-linear chains with a small number of nodes.	Commun. Nonlinear Sci. Numer. Simul.	2021	DBLP DOI BibTeX RDF
26	Noureddine Ait Said, Mounir Benabdenbi, Katell Morin-Allory	FPU Reduced Variable Precision in Time: Application to the Jacobi Iterative Method.	ISVLSI	2021	DBLP DOI BibTeX RDF
26	Luca Bertaccini, Matteo Perotti, Stefan Mach, Pasquale Davide Schiavone, Florian Zaruba, Luca Benini	Tiny-FPU: Low-Cost Floating-Point Support for Small RISC-V MCU Cores.	ISCAS	2021	DBLP DOI BibTeX RDF
26	Luca Cremona, William Fornaciari, Andrea Galimberti, Andrea Romanoni, Davide Zoni	VGM-Bench: FPU Benchmark Suite for Computer Vision, Computer Graphics and Machine Learning Applications.	SAMOS	2020	DBLP DOI BibTeX RDF
26	Noureddine Ait Said, Mounir Benabdenbi, Katell Morin-Allory	FPU Bit-Width Optimization for Approximate Computing: A Non-Intrusive Approach.	DTIS	2020	DBLP DOI BibTeX RDF
26	Athanassios Tziouvaras, Georgios Dimitriou, Michael F. Dossis, Georgios I. Stamoulis	Adaptive Operation-Based ALU and FPU Clocking.	MOCAST	2020	DBLP DOI BibTeX RDF
26	Roelof Bruggeman, Ferdinand Verhulst	Near-Integrability and Recurrence in FPU Chains with Alternating Masses.	J. Nonlinear Sci.	2019	DBLP DOI BibTeX RDF
26	Xiang Yi, Shixiao Liu	Mobility of Discrete Breather in a FPU-KG Chain.	CIS	2019	DBLP DOI BibTeX RDF
26	Aneesh Raveendran, Vinay Kumar, Vivian Desalphine, David Selvakumar	Functional Simulation Verification of RISC-V Instruction Set Based High Level Language Modeled FPU.	VDAT	2019	DBLP DOI BibTeX RDF
26	Julian Stecklina, Thomas Prescher 0002	LazyFP: Leaking FPU Register State using Microarchitectural Side-Channels.	CoRR	2018	DBLP BibTeX RDF
26	Michael Herrmann	High-Energy Waves in Superpolynomial FPU-Type Chains.	J. Nonlinear Sci.	2017	DBLP DOI BibTeX RDF
26	Ferdinand Verhulst	Near-Integrability and Recurrence in FPU-Cells.	Int. J. Bifurc. Chaos	2016	DBLP DOI BibTeX RDF
26	Alexandre Aminot, Yves Lhuillier, Andrea Castagnetti, Henri-Pierre Charles	FPU Speedup Estimation for Task Placement Optimization on Asymmetric Multicore Designs.	MCSoC	2015	DBLP DOI BibTeX RDF
26	Jeremy Gaison, Shari Moskow, J. Douglas Wright, Qimin Zhang	Approximation of Polyatomic FPU Lattices by KdV Equations.	Multiscale Model. Simul.	2014	DBLP DOI BibTeX RDF
26	Aarti Gupta, V. M. Achutha KiranKumar, Rajnish Ghughal	Formally Verifying Graphics FPU - An Intel® Experience.	FM	2014	DBLP DOI BibTeX RDF
26	Bogdan Pasca 0001	Low-cost multiplier-based FPU for embedded processing on FPGA.	FPL	2014	DBLP DOI BibTeX RDF
26	Angelos Ntasios, Minas Dasygenis	Design, Implementation and Verification of a Customizing IP Soft Core With FPU Support.	Panhellenic Conference on Informatics	2014	DBLP DOI BibTeX RDF
26	Michail Maniatakos, Prabhakar Kudva, Bruce M. Fleischer, Yiorgos Makris	Low-Cost Concurrent Error Detection for Floating-Point Unit (FPU) Controllers.	IEEE Trans. Computers	2013	DBLP DOI BibTeX RDF
26	Marat Dukhan	What a fast FPU means for algorithms: A story of vector elementary functions.	Hot Chips Symposium	2013	DBLP DOI BibTeX RDF
26	Sameh Galal, Ofer Shacham, John S. Brunhaver, Jing Pu, Artem Vassiliev, Mark Horowitz	FPU Generator for Design Space Exploration.	IEEE Symposium on Computer Arithmetic	2013	DBLP DOI BibTeX RDF
26	Abbas Rahimi, Andrea Marongiu, Rajesh K. Gupta 0001, Luca Benini	A variability-aware OpenMP environment for efficient execution of accuracy-configurable computation on shared-FPU processor clusters.	CODES+ISSS	2013	DBLP DOI BibTeX RDF
26	Mohammad Reza Kakoee, Igor Loi, Luca Benini	A shared-FPU architecture for ultra-low power MPSoCs.	Conf. Computing Frontiers	2013	DBLP DOI BibTeX RDF
26	V. M. Achutha KiranKumar, Aarti Gupta, Rajnish Ghughal	Symbolic Trajectory Evaluation: The primary validation Vehicle for next generation Intel® Processor Graphics FPU.	FMCAD	2012	DBLP BibTeX RDF
26	Michael Herrmann	Action Minimising Fronts in General FPU-type Chains.	J. Nonlinear Sci.	2011	DBLP DOI BibTeX RDF
26	Jaume Joven, Per Strict, David Castells-Rufas, Akash Bagdia, Giovanni De Micheli, Jordi Carrabina	HW-SW implementation of a decoupled FPU for ARM-based Cortex-M1 SoCs in FPGAs.	SIES	2011	DBLP DOI BibTeX RDF
26	Minh Thien Trieu, Huong Thien Hoang, Phong The Vo, Hung Bao Vo, Yoichi Yuyama	Saving 78.11% Dhrystone power consumption in FPU by clock gating while still keeping co-operation with CPU.	ASICON	2011	DBLP DOI BibTeX RDF
26	Michail Maniatakos, Yiorgos Makris, Prabhakar Kudva, Bruce M. Fleischer	Exponent monitoring for low-cost concurrent error detection in FPU control logic.	VTS	2011	DBLP DOI BibTeX RDF
26	Michael Herrmann, Jens D. M. Rademacher	Heteroclinic Travelling Waves in Convex FPU-Type Chains.	SIAM J. Math. Anal.	2010	DBLP DOI BibTeX RDF
26	T. R. Gopalakrishnan Nair, R. Selvarani, Vighnaraju Saraf	Execution and Result Integration Scheme in FPU Farms for Co-ordinated Performance	CoRR	2010	DBLP BibTeX RDF
26	Bob Rink	Fermi Pasta Ulam systems (FPU): mathematical aspects.	Scholarpedia	2009	DBLP DOI BibTeX RDF
26	Fumio Arakawa, Takashi Okada, Tomoichi Hayashi, Osamu Nishii, Toshihiro Hattori	An embedded processor core for consumer appliances with 5.6 GFLOPS and 73M polygons/s FPU.	Microprocess. Microsystems	2009	DBLP DOI BibTeX RDF
26	Hartmut Schwetlick, Johannes Zimmer	Solitary Waves for Nonconvex FPU Lattices.	J. Nonlinear Sci.	2007	DBLP DOI BibTeX RDF
26	Yung-Ming Chang, Juan-Ming Yuan, Chin-Chieh Chiang	FPU Recurrence in the KdV-Type Equations.	ICICIC (2)	2006	DBLP DOI BibTeX RDF
26	Charles D. Wait	IBM PowerPC 440 FPU with complex-arithmetic extensions.	IBM J. Res. Dev.	2005	DBLP DOI BibTeX RDF
26	Juergen Lorenz, Stefan Kral, Franz Franchetti, Christoph W. Ueberhuber	Vectorization techniques for the Blue Gene/L double FPU.	IBM J. Res. Dev.	2005	DBLP DOI BibTeX RDF
26	Eric M. Schwarz, Martin S. Schmookler, Son Dao Trong	FPU Implementations with Denormalized Numbers.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	Denormalized numbers, subnormals, floating-point hardware, underflow trap, IEEE 754 Standard
26	Claudio Brunelli, Fabio Campi, Juha Kylliäinen, Jari Nurmi	A reconfigurable FPU as IP component for SoCs.	SoC	2004	DBLP DOI BibTeX RDF
26	Franz Franchetti, Stefan Kral, Juergen Lorenz, Markus Püschel, Christoph W. Ueberhuber	Automatically Tuned FFTs for BlueGene/L's Double FPU.	VECPAR	2004	DBLP DOI BibTeX RDF
26	Mourad Aberbour, A. Houelle, Habib Mehrez, Nicolas Vaucher, Alain Guyot	On portable macrocell FPU generators for division and square root operators complying to the full IEEE-754 standard.	IEEE Trans. Very Large Scale Integr. Syst.	1998	DBLP DOI BibTeX RDF
17	Florent de Dinechin, Jérémie Detrey, Octavian Cret, Radu Tudoran	When FPGAs are better at floating-point than microprocessors.	FPGA	2008	DBLP DOI BibTeX RDF	FPGA, floating-point, arithmetic
17	Andrew G. Schmidt, William V. Kritikos, Siddhartha Datta, Ron Sass	Reconfigurable Computing Cluster Project: Phase I Brief.	FCCM	2008	DBLP DOI BibTeX RDF
17	Karthik Ganesan 0006, Lizy Kurian John, Valentina Salapura, James C. Sexton	A Performance Counter Based Workload Characterization on Blue Gene/P.	ICPP	2008	DBLP DOI BibTeX RDF
17	Xuehai Qian, He Huang, Zhenzhong Duan, Junchao Zhang, Nan Yuan, Yongbin Zhou, Hao Zhang 0009, Huimin Cui, Dongrui Fan	Optimized Register Renaming Scheme for Stack-Based x86 Operations.	ARCS	2007	DBLP DOI BibTeX RDF
17	Libo Huang, Li Shen 0007, Kui Dai, Zhiying Wang 0003	A New Architecture For Multiple-Precision Floating-Point Multiply-Add Fused Unit Design.	IEEE Symposium on Computer Arithmetic	2007	DBLP DOI BibTeX RDF
17	Libo Huang, Ming-che Lai, Kui Dai, Hong Yue, Li Shen 0007	Hardware Support for Arithmetic Units of Processor with Multimedia Extension.	MUE	2007	DBLP DOI BibTeX RDF
17	Viay Holimath, Javier D. Bruguera	A Linear Convergent Functional Iterative DivisionWithout a Look-Up Table.	DSD	2006	DBLP DOI BibTeX RDF
17	Dong-Sun Kim 0002, Hyunsik Kim, Duck-Jin Chung	Implementation of a Neural Network Processor Based on RISC Architecture for Various Signal Processing Applications.	ISNN (2)	2006	DBLP DOI BibTeX RDF
17	Kyprianos Papademetriou, Apostolos Dollas	A Task Graph Approach for Efficient Exploitation of Reconfiguration in Dynamically Reconfigurable Systems.	FCCM	2006	DBLP DOI BibTeX RDF
17	Tim Barrett, Sumit D. Mediratta, Taek-Jun Kwon, Ravinder Singh, Sachit Chandra, Jeff Sondeen, Jeffrey T. Draper	A double-data rate (DDR) processing-in-memory (PIM) device with wideword floating-point capability.	ISCAS	2006	DBLP DOI BibTeX RDF
17	Taek-Jun Kwon, Jeff Sondeen, Jeffrey T. Draper	Design trade-offs in floating-point unit implementation for embedded and processing-in-memory systems.	ISCAS (4)	2005	DBLP DOI BibTeX RDF
17	François Gygi, Robert K. Yates, Juergen Lorenz, Erik W. Draeger, Franz Franchetti, Christoph W. Ueberhuber, Bronis R. de Supinski, Stefan Kral, John A. Gunnels, James C. Sexton	Large-Scale First-Principles Molecular Dynamics simulations on the BlueGene/L Platform using the Qbox code.	SC	2005	DBLP DOI BibTeX RDF	Electronic structure, Ab initio simulations, First-principles simulations, BlueGene/L, Parallel computing, Molecular Dynamics
17	Sangsoo Park, Yonghee Lee, Heonshik Shin	Experimental Performance Evaluation of Embedded Linux Using Alternative CPU Core Organizations.	EUC	2004	DBLP DOI BibTeX RDF
17	Jiansheng Chen, Yiu Sang Moon, K. F. Fong	Efficient Fingerprint Image Enhancement for Mobile Embedded Systems.	ECCV Workshop BioAW	2004	DBLP DOI BibTeX RDF
17	Pavel Tvrdík, Ivan Simecek	Analytical Modeling of Optimized Sparse Linear Code.	PPAM	2003	DBLP DOI BibTeX RDF
17	Jeffrey Bolz, Peter Schröder	Rapid evaluation of Catmull-Clark subdivision surfaces.	Web3D	2002	DBLP DOI BibTeX RDF
17	Cheol-Ho Jeong, Woo-Chan Park, Tack-Don Han, Moon Key Lee, Sang-Woo Kim	In-Order Issue Out-of-Order Execution Floating-Point Coprocessor for CalmRISC32.	IEEE Symposium on Computer Arithmetic	2001	DBLP DOI BibTeX RDF
17	Christoph Berg, Christian Jacobi 0002	Formal Verification of the VAMP Floating Point Unit.	CHARME	2001	DBLP DOI BibTeX RDF
17	Matthias Pflanz, Karsten Walther, Heinrich Theodor Vierhaus	On-line Error Detection Techniques for Dependable Embedded Processors with High Complexity.	IOLTW	2001	DBLP DOI BibTeX RDF
17	Gülbin Ezer	Xtensa with User Defined DSP Coprocessor Microarchitectures.	ICCD	2000	DBLP DOI BibTeX RDF
17	Stuart F. Oberman, Hesham A. Al-Twaijry, Michael J. Flynn	The SNAP Project: Design of Floating Point Arithmetic Unit.	IEEE Symposium on Computer Arithmetic	1997	DBLP DOI BibTeX RDF	performance-area tradeoffs, computer arithmetic, multiplication, division, Addition, floating point unit
17	Peter Soderquist, Miriam Leeser	An Area/Performance Comparison of Subtractive and Multiplicative Divide/Square Root Implementations.	IEEE Symposium on Computer Arithmetic	1995	DBLP DOI BibTeX RDF	Newton-Raphson method, Goldschmidt's algorithm, microprocessor, Floating-point, division, square root, SRT
17	Michael H. Arnold, Walter S. Scott	An Interactive Maze Router with Hints.	DAC	1988	DBLP BibTeX RDF