Search results for "FSMs"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
78	Carlos Humberto Llanos Quintero, Marius Strum	SINMEF - A Decomposition Based Synthesis Tool for Large FSMs.	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF	non-deterministic transitions, redundant transitions, decomposition, FSM, clustering technique
69	Ajay J. Daga, William P. Birmingham	A symbolic-simulation approach to the timing verification of interacting FSMs.	ICCD	1995	DBLP DOI BibTeX RDF	symbolic-simulation approach, interacting FSMs, timing verifier, complex sequential circuit verification, combinational paths, inherently modular nature, symbolic simulation verification methodology, formal verification, logic testing, finite state machines, finite state machines, sequential circuits, circuit analysis computing, timing verification
68	Tomoo Inoue, Toshimitsu Masuzawa, Hiroshi Youra, Hideo Fujiwara	An Approach To The Synthesis Of Synchronizable Finite State Machines With Partial Scan.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF	synchronizable finite state machines, sequential circuits synthesis, extended synchronizing sequence, scan inputs, normal inputs, MCNC'91 benchmark FSM, minimum-length extended synchronizing sequence, test generation, finite state machines, DFT, heuristic algorithm, minimization, partial scan, synthesis for testability, state assignment, state transition, state encoding
68	Wenbo Mao, George J. Milne	An Automated Proof Technique for Finite-State Machine Equivalence.	CAV	1991	DBLP DOI BibTeX RDF
66	Gustavo Sutter, Elias Todorovich, Sergio López-Buedo, Eduardo I. Boemo	Low-Power FSMs in FPGA: Encoding Alternatives.	PATMOS	2002	DBLP DOI BibTeX RDF	One-Hot, State Encod-ing, FPGA, Low-Power, Finite State Machine
60	Natalia Shabaldina, Khaled El-Fakih, Nina Yevtushenko 0001	Testing Nondeterministic Finite State Machines with Respect to the Separability Relation.	TestCom/FATES	2007	DBLP DOI BibTeX RDF	separability relation, testing nondeterministic FSMs
60	Chunduri Rama Mohan, Srobona Mitra, Partha Pal Chaudhuri	On Incorporation of BIST for the Synthesis of Easily and Fully Testable Controllers.	VLSI Design	1997	DBLP DOI BibTeX RDF	fully testable controllers, testing scheme, Cadence, target library, built-in self test, cellular automata, VHDL, ATPGs, BIST, testability, FSMs, partial scan, VERILOG, area overhead, RTL designs, SYNERGY, full scan, stuck-at fault model
58	Jun Sun 0001, Jin Song Dong	Extracting FSMs from Object-Z Specifications with History Invariants.	ICECCS	2005	DBLP DOI BibTeX RDF	Software Specification, FSMs, Object-Z
55	Rainer Findenig, Florian Eibensteiner, Markus Pfaff	Optimizing the Hardware Usage of Parallel FSMs.	EUROCAST	2009	DBLP DOI BibTeX RDF	Scheduling, Resource Sharing, FSM, Serialization
55	Anneliese Amschler Andrews, Jeff Offutt, Roger T. Alexander	Testing Web applications by modeling with FSMs.	Softw. Syst. Model.	2005	DBLP DOI BibTeX RDF	Testing of Web applications, Finite state machines, System testing
55	Luis Mengibar, Luis Entrena, Michael G. Lorenz, Raul Sánchez-Reillo	State Encoding for Low-Power FSMs in FPGA.	PATMOS	2003	DBLP DOI BibTeX RDF
55	Robert M. Fuhrer, Steven M. Nowick	OPTIMISTA: state minimization of asynchronous FSMs for optimum output logic.	ICCAD	1999	DBLP DOI BibTeX RDF
47	Jessica Chen	A study on static analysis in network of synchronizing FSMs.	APSEC	2000	DBLP DOI BibTeX RDF	synchronizing FSMs, multithreaded systems, nondeterministic behavior, Java monitors, Java, static analysis, finite state machines, synchronisation, operational semantics, multi-threading, labeled transition systems, thread synchronization, design artifacts
45	Jie-Hong Roland Jiang, Robert K. Brayton	Retiming and Resynthesis: A Complexity Perspective.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
45	Lin Yuan, Gang Qu 0001, Tiziano Villa, Alberto L. Sangiovanni-Vincentelli	FSM re-engineering and its application in low power state encoding.	ASP-DAC	2005	DBLP DOI BibTeX RDF
45	Jie-Hong Roland Jiang	On Some Transformation Invariants Under Retiming and Resynthesis.	TACAS	2005	DBLP DOI BibTeX RDF
45	Isaac Rudomín, Erik Millán	Probabilistic, layered and hierarchical animated agents using XML.	GRAPHITE	2005	DBLP DOI BibTeX RDF	XML, maps, virtual characters, crowds
45	Uttam K. Sarkar, Subramanian Ramakrishnan, Dilip Sarkar	Modeling full-length video using Markov-modulated Gamma-based framework.	IEEE/ACM Trans. Netw.	2003	DBLP DOI BibTeX RDF	QQ plot, frame-size traffic model, leaky-bucket simulation, variable bit rate (VBR) video, MPEG, gamma distribution
45	Hideo Fujiwara	A New Class of Sequential Circuits with Combinational Test Generation Complexity.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	complexity, test generation, design for testability, sequential circuits, reducibility, partial scan, Balanced structure
45	Hideo Fujiwara	A New Definition and a New Class of Sequential Circuits with Combinational Test Generation Complexity.	VLSI Design	2000	DBLP DOI BibTeX RDF	complexity, test generation, design for testability, sequential circuits, reducibility, partial scan, Balanced structure
45	Gagan Hasteer, Anmol Mathur, Prithviraj Banerjee	Efficient equivalence checking of multi-phase designs using phase abstraction and retiming.	ACM Trans. Design Autom. Electr. Syst.	1998	DBLP DOI BibTeX RDF	binary decision, encoding density, multi-phase FSM, product machine, sequential hardware equivalence, diagram, steady states
45	Hyoung Seok Hong, Yong Rae Kwon, Sung Deok Cha	Testing of Object-Oriented Programs Based on Finite State Machines.	APSEC	1995	DBLP DOI BibTeX RDF	software testing, object-oriented programs, finite state machines, classes
44	Roman Goot, Ilya Levin, Sergei Ostanin	Fault Latencies of Concurrent Checking FSMs.	DSD	2002	DBLP DOI BibTeX RDF
44	Petros Drineas, Yiorgos Makris	Non-Intrusive Design of Concurrently Self-Testable FSMs.	Asian Test Symposium	2002	DBLP DOI BibTeX RDF
44	Valery Sklyarov	An Evolutionary Algorithm for the Synthesis of RAM-Based FSMs.	IEA/AIE	2002	DBLP DOI BibTeX RDF
44	Loe M. G. Feijs	Generating FSMs from Interworkings.	Distributed Comput.	1999	DBLP DOI BibTeX RDF	Sequence chart, Synthesis, Finite state machine, Process algebra
44	Diana Marculescu, Radu Marculescu, Massoud Pedram	Trace-Driven Steady-State Probability Estimation in FSMs with Application to Power Estimation.	DATE	1998	DBLP DOI BibTeX RDF	Probabilistic FSM analysis, high-order Markov chains, power estimation
42	Jumei Yue, Yongyi Yan	Update Law of Simplifying Finite State Machines (FSMs): An Answer to the Open Question of the Unmanned Optimization of FSMs.	IEEE Trans. Circuits Syst. II Express Briefs	2022	DBLP DOI BibTeX RDF
42	Peter Bodorik, Christian G. Liu, Dawn N. Jutla	Using FSMs to Find Patterns for Off-Chain Computing: Finding Patterns for Off-Chain Computing with FSMs.	ICBCT	2021	DBLP DOI BibTeX RDF
37	Qiang Guo 0001, Robert M. Hierons, Mark Harman, Karnig Derderian	Computing Unique Input/Output Sequences Using Genetic Algorithms.	FATES	2003	DBLP DOI BibTeX RDF	UIOs, Genetic Algorithms, Optimisation, Conformance Testing, FSMs
37	Franco Fummi, U. Rovati, Donatella Sciuto	Functional design for testability of control-dominated architectures.	ACM Trans. Design Autom. Electr. Syst.	1997	DBLP DOI BibTeX RDF	interacting FSMs, functional testing
37	Manish Pandey, Alok Jain, Randal E. Bryant, Derek L. Beatty, Gary York, Samir Jain	Extraction of finite state machines from transistor netlists by symbolic simulation.	ICCD	1995	DBLP DOI BibTeX RDF	finite state machine extraction, transistor netlists, clock level finite state machines, gate level representation, circuit clocking, output timing, simulation patterns, next state, output function, equivalent FSM, static storage structures, time multiplexed inputs, time multiplexed outputs, finite state machines, logic design, logic CAD, circuit analysis computing, FSMs, symbolic simulation, symbolic simulator, Ordered Binary Decision Diagrams
37	Mandyam-Komar Srinivas, James Jacob, Vishwani D. Agrawal	Functional test generation for non-scan sequential circuits.	VLSI Design	1995	DBLP DOI BibTeX RDF	nonscan sequential circuits, functional test vectors, growth and disappearance fault model, complete stuck fault coverage, algebraic transformations, synthesized FSMs, VLSI, fault diagnosis, logic testing, finite state machines, integrated circuit testing, sequential circuits, automatic testing, functional test generation
34	Maxim Gromov, Khaled El-Fakih, Natalia Shabaldina, Nina Yevtushenko 0001	Distinguing Non-deterministic Timed Finite State Machines.	FMOODS/FORTE	2009	DBLP DOI BibTeX RDF
34	Adenilso da Silva Simão, Alexandre Petrenko	Generating Checking Sequences for Partial Reduced Finite State Machines.	TestCom/FATES	2008	DBLP DOI BibTeX RDF
34	Ghaith Hammouri, Kahraman D. Akdemir, Berk Sunar	Novel PUF-Based Error Detection Methods in Finite State Machines.	ICISC	2008	DBLP DOI BibTeX RDF	adversarial-faults, state-machines, PUF, Fault-resilience
34	Simon M. Lucas, T. Jeff Reynolds	Learning Finite-State Transducers: Evolution Versus Heuristic State Merging.	IEEE Trans. Evol. Comput.	2007	DBLP DOI BibTeX RDF
34	Florentin Ipate	Bounded Sequence Testing from Non-deterministic Finite State Machines.	TestCom	2006	DBLP DOI BibTeX RDF
34	Anurag Tiwari, Karen A. Tomko	Saving Power by Mapping Finite-State Machines into Embedded Memory Blocks in FPGAs.	DATE	2004	DBLP DOI BibTeX RDF
34	David A. Bader, Kamesh Madduri	A Parallel State Assignment Algorithm for Finite State Machines.	HiPC	2004	DBLP DOI BibTeX RDF
34	Ricardo Nastas Acras, Silvia Regina Vergilio	Splinter: A Generic Framework for Evolving Modular Finite State Machines.	SBIA	2004	DBLP DOI BibTeX RDF	modularity, evolutionary programming
34	Marcelo Fantinato, Mário Jino	Applying Extended Finite State Machines in Software Testing of Interactive Systems.	DSV-IS	2003	DBLP DOI BibTeX RDF	Finite State Machines, Model Based Testing, Functional Testing, Testing Criteria
34	Sezer Gören 0001, F. Joel Ferguson	Testing Finite State Machines Based on a Structural Coverage Metric .	ITC	2002	DBLP DOI BibTeX RDF
34	Umberto Cerruti, Mario Giacobini, Pierre Liardet	Prediction of Binary Sequences by Evolving Finite State Machines.	Artificial Evolution	2001	DBLP DOI BibTeX RDF
34	Richard Raimi, Ramin Hojati, Kedar S. Namjoshi	Environment modeling and language universality.	ACM Trans. Design Autom. Electr. Syst.	2000	DBLP DOI BibTeX RDF	language universality, model checking, abstraction, environment modeling
34	M. Tuan Tu, Eberhard Wolff, Winfried Lamersdorf	Genetic Algorithms for Automated Negotiations: A FSM-Based Application.	DEXA Workshops	2000	DBLP DOI BibTeX RDF	FSM based application approach, electronic commerce applications, GA principles, negotiating agents, genetic algorithms, electronic commerce, finite state machines, automated negotiations, negotiation strategy
34	In Sang Chung, Malcolm Munro, Wan Kwon Lee, Yong Rae Kwon	Applying Conventional Testing Techniques for Class Testing.	COMPSAC	1996	DBLP DOI BibTeX RDF	program testing techniques, class member function testing, code-based testing, formal specification, object-oriented programming, object oriented programming, finite state machines, finite state machines, program testing, symbolic execution, programming theory, specification-based testing, class testing, branch coverage
32	Ivan Radojevic, Zoran A. Salcic, Partha S. Roop	McCharts and Multiclock FSMs for modeling large scale systems.	MEMOCODE	2007	DBLP DOI BibTeX RDF
32	Danilo Ravotto, Edgar E. Sánchez, Massimiliano Schillaci, Matteo Sonza Reorda, Giovanni Squillero	On Automatic Test Block Generation for Peripheral Testing in SoCs via Dynamic FSMs Extraction.	MTV	2007	DBLP DOI BibTeX RDF
32	Andrzej Krasniewski	Concurrent Error Detection for FSMs Designed for Implementation with Embedded Memory Blocks of FPGAs.	DSD	2007	DBLP DOI BibTeX RDF
32	Jaan Raik, Raimund Ubar, Taavi Viilukas	High-Level Decision Diagram based Fault Models for Targeting FSMs.	DSD	2006	DBLP DOI BibTeX RDF
32	Sobeeh Almukhaizim, Petros Drineas, Yiorgos Makris	On Concurrent Error Detection with Bounded Latency in FSMs.	DATE	2004	DBLP DOI BibTeX RDF
32	Amit M. Paradkar	Plannable Test Selection Criteria for FSMs Extracted From Operational Specifications.	ISSRE	2004	DBLP DOI BibTeX RDF	Model-Based Test Generation, EFSM-based Test Selection, Mutation-based Test Selection
32	Petros Drineas, Yiorgos Makris	Non-Intrusive Concurrent Error Detection in FSMs through State/Output Compaction and Monitoring via Parity Trees.	DATE	2003	DBLP DOI BibTeX RDF
32	Konstantinos Rokas, Yiorgos Makris, Dimitris Gizopoulos	Low Cost Convolutional Code Based Concurrent Error Detection in FSMs.	DFT	2003	DBLP DOI BibTeX RDF
32	Petros Drineas, Yiorgos Makris	SPaRe: Selective Partial Replication for Concurrent Fault Detection in FSMs.	VLSI Design	2003	DBLP DOI BibTeX RDF
32	Luca Macchiarulo, Shih-Ming Shu, Malgorzata Marek-Sadowska	Wave Steered FSMs.	DATE	2000	DBLP DOI BibTeX RDF
32	Luca Macchiarulo, Malgorzata Marek-Sadowska	Wave-steering one-hot encoded FSMs.	DAC	2000	DBLP DOI BibTeX RDF
32	Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda	Circular Self-Test Path for FSMs.	IEEE Des. Test Comput.	1996	DBLP DOI BibTeX RDF
32	Timothy Kam, Tiziano Villa, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli	Implicit state minimization of non-deterministic FSMs.	ICCD	1995	DBLP DOI BibTeX RDF	implicit state minimization, nondeterministic finite state machines, fully implicit algorithm, finite state machines, logic design, minimisation
32	Dan R. Olsen	A Subset Algorithm for Deterministic FSMs within Deterministic PDAs.	ACM SIGPLAN Notices	1983	DBLP DOI BibTeX RDF
23	Mario García-Valderas, Raúl Fernández Cardenal, Celia López-Ongil, Marta Portela-García, Luis Entrena	SET Emulation Under a Quantized Delay Model.	DFT	2007	DBLP DOI BibTeX RDF
23	Sezer Gören 0001, F. Joel Ferguson	Test sequence generation for controller verification and test with high coverage.	ACM Trans. Design Autom. Electr. Syst.	2006	DBLP DOI BibTeX RDF	finite state machine, Fault coverage, black box testing, X-machine
23	Vít Fábera, Vlastimil Jánes, Mária Jánesová	Automata Construct with Genetic Algorithm.	DSD	2006	DBLP DOI BibTeX RDF
23	Valdivino Alexandre de Santiago Jr., Ana Silvia Martins do Amaral, Nandamudi L. Vijaykumar, Maria de Fátima Mattiello-Francisco, Eliane Martins, Odnei Cuesta Lopes	A Practical Approach for Automated Test Case Generation using Statecharts.	COMPSAC (2)	2006	DBLP DOI BibTeX RDF
23	Joumana Dargham, Sukaina Al Nasrawi	FSM Behavioral Modeling Approach for Hypermedia Web Applications: FBM-HWA Approach.	AICT/ICIW	2006	DBLP DOI BibTeX RDF
23	Grigore Rosu, Klaus Havelund	Rewriting-Based Techniques for Runtime Verification.	Autom. Softw. Eng.	2005	DBLP DOI BibTeX RDF	verification, rewriting, runtime analysis
23	Alexandre Petrenko, Nina Yevtushenko 0001	Testing from Partial Deterministic FSM Specifications.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	partially specified FSM, weak conformance testing, test generation, Finite State Machine, fault detection, checking experiment, state identification
23	Islam Elgedawy, Zahir Tari, James A. Thom	A High-Level Functional Matching for Semantic Web Services.	ICSOC	2005	DBLP DOI BibTeX RDF
23	Alan Mishchenko, Robert K. Brayton, Jie-Hong Roland Jiang, Tiziano Villa, Nina Yevtushenko 0001	Efficient Solution of Language Equations Using Partitioned Representations.	DATE	2005	DBLP DOI BibTeX RDF
23	Steffen Toscher, Roland Kasper, Thomas Reinemann	Dynamic Reconfiguration of Mechatronic Real-Time Systems Based on Configuration State Machines.	IPDPS	2005	DBLP DOI BibTeX RDF
23	Alexandre Petrenko, Nina Yevtushenko 0001	Conformance Tests as Checking Experiments for Partial Nondeterministic FSM.	FATES	2005	DBLP DOI BibTeX RDF
23	Lech Józwiak, Dominik Gawlowski, Aleksander Slusarczyk	An Effective Solution of Benchmarking Problem FSM Benchmark Generator and Its Application to Analysis of State Assignment Methods.	DSD	2004	DBLP DOI BibTeX RDF
23	Maik Boden, Manfred Koegst, José Luis Tiburcio Badía, Steffen Rülke	Cost-Efficient Implementation of Adaptive Finite State Machines.	DSD	2004	DBLP DOI BibTeX RDF
23	Karnig Derderian, Robert M. Hierons, Mark Harman, Qiang Guo 0001	Input Sequence Generation for Testing of Communicating Finite State Machines (CFSMs).	GECCO (2)	2004	DBLP DOI BibTeX RDF
23	Yun Zhai, Zeeshan Rasheed, Mubarak Shah	A Framework for Semantic Classification of Scenes Using Finite State Machines.	CIVR	2004	DBLP DOI BibTeX RDF
23	Khaled El-Fakih, Nina Yevtushenko 0001	Fault Propagation by Equation Solving.	FORTE	2004	DBLP DOI BibTeX RDF
23	Yanlei Diao, Mehmet Altinel, Michael J. Franklin, Hao Zhang 0003, Peter M. Fischer 0001	Path sharing and predicate evaluation for high-performance XML filtering.	ACM Trans. Database Syst.	2003	DBLP DOI BibTeX RDF	Nondeterministic Finite Automaton, XML filtering, content-based matching, nested path expressions., path sharing, predicate evaluation, structure matching
23	Wolfgang Grieskamp, Lev Nachmanson, Nikolai Tillmann, Margus Veanes	Test Case Generation from AsmL Specifications.	Abstract State Machines	2003	DBLP DOI BibTeX RDF
23	Giuliano Antoniol, Lionel C. Briand, Massimiliano Di Penta, Yvan Labiche	A Case Study Using the Round-Trip Strategy for State-Based Class Testing.	ISSRE	2002	DBLP DOI BibTeX RDF
23	Atsushi Fukada, Akio Nakata, Junji Kitamichi, Teruo Higashino, Ana R. Cavalli	A Conformance Testing Method for Communication Protocols Modeled as Concurrent DFSMs.	ICOIN	2001	DBLP DOI BibTeX RDF
23	Luca Benini, Giovanni De Micheli	Synthesis of low-power selectively-clocked systems from high-level specification.	ACM Trans. Design Autom. Electr. Syst.	2000	DBLP DOI BibTeX RDF	low power, high-level synthesis, gated clock
23	Valery Sklyarov	Synthesis and Implementation of RAM-Based Finite State Machines in FPGAs.	FPL	2000	DBLP DOI BibTeX RDF
23	Eberhard Wolff, M. Tuan Tu, Winfried Lamersdorf	Using Genetic Algorithms to Enable Automated Auctions.	EC-Web	2000	DBLP DOI BibTeX RDF	genetic algorithms, E-Commerce, auctions, negotiation strategies
23	Andreas Hett, Christoph Scholl 0001, Bernd Becker 0001	Distance driven finite state machine traversal.	DAC	2000	DBLP DOI BibTeX RDF
23	Matthias Anlauff, Philipp W. Kutter, Alfonso Pierantonio	Enhanced Control Flow Graphs in Montages.	Ershov Memorial Conference	1999	DBLP DOI BibTeX RDF
23	Wai-Kwong Lee, Chi-Ying Tsui	Finite state machine partitioning for low power.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
23	B. N. V. Malleswara Gupta, H. Narayanan, Madhav P. Desai	A State Assignment Scheme Targeting Performance and Area.	VLSI Design	1999	DBLP DOI BibTeX RDF
23	S. Ramesh	Efficient Translation of Statecharts to Hardware Circuits.	VLSI Design	1999	DBLP DOI BibTeX RDF
23	Jeffrey X. Su, David L. Dill, Jens U. Skakkebæk	Formally Verifying Data and Control with Weak Reachability Invariants.	FMCAD	1998	DBLP DOI BibTeX RDF
23	Sumit Roy 0003, Prithviraj Banerjee, Majid Sarrafzadeh	Partitioning sequential circuits for low power.	VLSI Design	1998	DBLP DOI BibTeX RDF	low-power, gated-clock, sequential synthesis
23	Dechang Sun, Bapiraju Vinnakota, Wanli Jiang	Fast State Verification.	DAC	1998	DBLP DOI BibTeX RDF	model checking, verification, guided search
23	Frank F. Hsu, Janak H. Patel	Design for Testability Using State Distances.	J. Electron. Test.	1997	DBLP DOI BibTeX RDF	state distance, finite-state-machine, design-for-testability, synthesis-for-testability
23	Luca Benini, Patrick Vuillod, Claudionor José Nunes Coelho Jr., Giovanni De Micheli	Synthesis of Low-Power Selectively-Clocked Systems from High-Level Specification.	ISSS	1996	DBLP DOI BibTeX RDF	low power, High level synthesis, finite state machines, gated clocks
23	Lakshmikant Bhupathi, Liang-Fang Chao	Dichotomy-based Model for FSM Power Minimization.	ICCD	1996	DBLP DOI BibTeX RDF
23	Frank F. Hsu, Janak H. Patel	A distance reduction approach to design for testability.	VTS	1995	DBLP DOI BibTeX RDF	distance reduction approach, center state, test function embedding technique, SFT techniques, logic testing, finite state machines, finite state machines, design for testability, design for testability, sequential circuits, sequential circuits, flip-flops, flip-flops, synthesis for testability, test function, average distance, DFT techniques
23	Adnan Aziz, Thomas R. Shiple, Vigyan Singhal	Formula-Dependent Equivalence for Compositional CTL Model Checking.	CAV	1994	DBLP DOI BibTeX RDF
23	Kwang-Ting Cheng, Srinivas Devadas, Kurt Keutzer	Delay-fault test generation and synthesis for testability under a standard scan design methodology.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
23	Alan Rotman, Ran Ginosar	Control unit synthesis from a high-level language.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
23	Doron Drusinsky-Yoresh	Decision problems for interacting finite state machines.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1991	DBLP DOI BibTeX RDF