|
|
Venues (Conferences, Journals, ...)
|
|
GrowBag graphs for keyword ? (Num. hits/coverage)
Group by:
The graphs summarize 22 occurrences of 19 keywords
|
|
|
Results
Found 20 publication records. Showing 20 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
99 | Jason Cong, Yuzheng Ding |
FlowMap: an optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(1), pp. 1-12, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
78 | Wai Shing Lau, Kin-Hong Lee, Kwong-Sak Leung |
A hybridized genetic parallel programming based logic circuit synthesizer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
GECCO ![In: Genetic and Evolutionary Computation Conference, GECCO 2006, Proceedings, Seattle, Washington, USA, July 8-12, 2006, pp. 839-846, 2006, ACM, 1-59593-186-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
FlowMap, a hybridized genetic parallel programming logic circuit synthesizer, genetic parallel programming, field programmable gate array, technology mapping, LookUp table |
63 | Wai-Chung Tang, Wing-Hang Lo, Yu-Liang Wu, Shih-Chieh Chang |
FPGA technology mapping optimization by rewiring algorithms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (6) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 5653-5656, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
63 | Jason Cong, Yean-Yow Hwang |
Simultaneous Depth and Area Minimization in LUT-based FPGA Mapping. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the Third International ACM Symposium on Field-Programmable Gate Arrays,FPGA 1995, Monterey, California, USA, February 12-14, 1995, pp. 68-74, 1995, ACM, 0-89791-743-X. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
42 | Yu-Chen Chen, Hou-Yu Pang, Kuen-Wen Lin, Rung-Bin Lin, Hui-Hsiang Tung, Shih-Chieh Su |
Via configurable three-input lookup-tables for structured ASICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, Providence, Rhode Island, USA, May 16-18 2010, pp. 49-54, 2010, ACM, 978-1-4503-0012-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
via-configurable, layout, look-up-table, vlsi, structured ASIC |
42 | Vamsi Boppana, Prashant Saxena, Prithviraj Banerjee, W. Kent Fuchs, C. L. Liu 0001 |
A Parallel Algorithm for the Technology Mapping of LUT-Based FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Euro-Par, Vol. I ![In: Euro-Par '96 Parallel Processing, Second International Euro-Par Conference, Lyon, France, August 26-29, 1996, Proceedings, Volume I, pp. 828-831, 1996, Springer, 3-540-61626-8. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
42 | Hyunchul Shin, Chunghee Kim |
Performance-oriented technology mapping for LUT-based FPGA's. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 3(2), pp. 323-327, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
42 | Hannah Honghua Yang, D. F. Wong 0001 |
Edge-map: optimal performance driven technology mapping for iterative LUT based FPGA designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1994, San Jose, California, USA, November 6-10, 1994, pp. 150-155, 1994, IEEE Computer Society / ACM, 0-89791-690-5. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
36 | Wenchao Ding 0001, Jieru Zhao, Yubin Chu, Haihui Huang, Tong Qin 0001, Chunjing Xu, Yuxiang Guan, Zhongxue Gan |
FlowMap: Path Generation for Automated Vehicles in Open Space Using Traffic Flow. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2305.01622, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
36 | Wenchao Ding 0001, Jieru Zhao, Yubin Chu, Haihui Huang, Tong Qin 0001, Chunjing Xu, Yuxiang Guan, Zhongxue Gan |
FlowMap: Path Generation for Automated Vehicles in Open Space Using Traffic Flow. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICRA ![In: IEEE International Conference on Robotics and Automation, ICRA 2023, London, UK, May 29 - June 2, 2023, pp. 1616-1622, 2023, IEEE, 979-8-3503-2365-8. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
36 | Xiong Wang 0001, Hanyu Liu, Jun Zhang, Jing Ren 0002, Sheng Wang 0006, Shizhong Xu |
FlowMap: A Fine-Grained Flow Measurement Approach for Data-Center Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICC ![In: 2019 IEEE International Conference on Communications, ICC 2019, Shanghai, China, May 20-24, 2019, pp. 1-7, 2019, IEEE, 978-1-5386-8088-9. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
36 | Trung Truong, Qiang Fu 0011, Christopher Lorier |
FlowMap: Improving network management with SDN. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NOMS ![In: 2016 IEEE/IFIP Network Operations and Management Symposium, NOMS 2016, Istanbul, Turkey, April 25-29, 2016, pp. 821-824, 2016, IEEE, 978-1-5090-0223-8. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
36 | Chang Woo Kim, Nikhil Malik, Dipjyoti Saikia, Sueng Yong Park |
An architecture for SDN flowmap inter-operation with legacy protocols. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICTC ![In: International Conference on Information and Communication Technology Convergence, ICTC 2014, Busan, South Korea, October 22-24, 2014, pp. 135-137, 2014, IEEE. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
21 | Wai-Chung Tang, Wing-Hang Lo, Yu-Liang Wu |
Further Improve Excellent Graph-Based FPGA Technology Mapping by Rewiring. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 1049-1052, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
21 | Valavan Manohararajah, Stephen Dean Brown, Zvonko G. Vranesic |
Heuristics for Area Minimization in LUT-Based FPGA Technology Mapping. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(11), pp. 2331-2340, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
21 | Raymond R. Hoare, Ivan S. Kourtev, Alex K. Jones |
Technology Mapping for Field Programmable Gate Arrays using Content-Addressable Memory (CAM). ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 14th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2006), 24-26 April 2006, Napa, CA, USA, Proceedings, pp. 299-300, 2006, IEEE Computer Society, 0-7695-2661-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
21 | Maxim Teslenko, Elena Dubrova |
Hermes: LUT FPGA technology mapping algorithm for area minimization with optimum depth. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2004 International Conference on Computer-Aided Design, ICCAD 2004, San Jose, CA, USA, November 7-11, 2004, pp. 748-751, 2004, IEEE Computer Society / ACM, 0-7803-8702-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
21 | Jason Cong, Yean-Yow Hwang |
Structural gate decomposition for depth-optimal technology mapping in LUT-based FPGA designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 5(2), pp. 193-225, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
computer-aided design of VSLI, FPGA, synthesis, system design, decomposition, technology mapping, simplification, programmable logic, logic optimization, delay minimization |
21 | Jason Cong, Hui Huang 0001 |
Depth optimal incremental mapping for field programmable gate arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 37th Conference on Design Automation, Los Angeles, CA, USA, June 5-9, 2000., pp. 290-293, 2000, ACM. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
21 | Aiguo Lu, Erik L. Dagless, Jonathan M. Saul |
DART: delay and routability driven technology mapping for LUT based FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1995 International Conference on Computer Design (ICCD '95), VLSI in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings, pp. 409-414, 1995, IEEE Computer Society, 0-8186-7165-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
DART, delay driven technology mapping, LUT based FPGAs, two-phased approach, routability directed delay-optimal mapping, stochastic routability analysis, delay-optimal mapping, field programmable gate arrays, delays, logic design, programmable logic arrays, table lookup, minimisation of switching nets |
Displaying result #1 - #20 of 20 (100 per page; Change: )
|
|