Search results for "FlowMap"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
99	Jason Cong, Yuzheng Ding	FlowMap: an optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
78	Wai Shing Lau, Kin-Hong Lee, Kwong-Sak Leung	A hybridized genetic parallel programming based logic circuit synthesizer.	GECCO	2006	DBLP DOI BibTeX RDF	FlowMap, a hybridized genetic parallel programming logic circuit synthesizer, genetic parallel programming, field programmable gate array, technology mapping, LookUp table
63	Wai-Chung Tang, Wing-Hang Lo, Yu-Liang Wu, Shih-Chieh Chang	FPGA technology mapping optimization by rewiring algorithms.	ISCAS (6)	2005	DBLP DOI BibTeX RDF
63	Jason Cong, Yean-Yow Hwang	Simultaneous Depth and Area Minimization in LUT-based FPGA Mapping.	FPGA	1995	DBLP DOI BibTeX RDF
42	Yu-Chen Chen, Hou-Yu Pang, Kuen-Wen Lin, Rung-Bin Lin, Hui-Hsiang Tung, Shih-Chieh Su	Via configurable three-input lookup-tables for structured ASICs.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	via-configurable, layout, look-up-table, vlsi, structured ASIC
42	Vamsi Boppana, Prashant Saxena, Prithviraj Banerjee, W. Kent Fuchs, C. L. Liu 0001	A Parallel Algorithm for the Technology Mapping of LUT-Based FPGAs.	Euro-Par, Vol. I	1996	DBLP DOI BibTeX RDF
42	Hyunchul Shin, Chunghee Kim	Performance-oriented technology mapping for LUT-based FPGA's.	IEEE Trans. Very Large Scale Integr. Syst.	1995	DBLP DOI BibTeX RDF
42	Hannah Honghua Yang, D. F. Wong 0001	Edge-map: optimal performance driven technology mapping for iterative LUT based FPGA designs.	ICCAD	1994	DBLP DOI BibTeX RDF
36	Wenchao Ding 0001, Jieru Zhao, Yubin Chu, Haihui Huang, Tong Qin 0001, Chunjing Xu, Yuxiang Guan, Zhongxue Gan	FlowMap: Path Generation for Automated Vehicles in Open Space Using Traffic Flow.	CoRR	2023	DBLP DOI BibTeX RDF
36	Wenchao Ding 0001, Jieru Zhao, Yubin Chu, Haihui Huang, Tong Qin 0001, Chunjing Xu, Yuxiang Guan, Zhongxue Gan	FlowMap: Path Generation for Automated Vehicles in Open Space Using Traffic Flow.	ICRA	2023	DBLP DOI BibTeX RDF
36	Xiong Wang 0001, Hanyu Liu, Jun Zhang, Jing Ren 0002, Sheng Wang 0006, Shizhong Xu	FlowMap: A Fine-Grained Flow Measurement Approach for Data-Center Networks.	ICC	2019	DBLP DOI BibTeX RDF
36	Trung Truong, Qiang Fu 0011, Christopher Lorier	FlowMap: Improving network management with SDN.	NOMS	2016	DBLP DOI BibTeX RDF
36	Chang Woo Kim, Nikhil Malik, Dipjyoti Saikia, Sueng Yong Park	An architecture for SDN flowmap inter-operation with legacy protocols.	ICTC	2014	DBLP DOI BibTeX RDF
21	Wai-Chung Tang, Wing-Hang Lo, Yu-Liang Wu	Further Improve Excellent Graph-Based FPGA Technology Mapping by Rewiring.	ISCAS	2007	DBLP DOI BibTeX RDF
21	Valavan Manohararajah, Stephen Dean Brown, Zvonko G. Vranesic	Heuristics for Area Minimization in LUT-Based FPGA Technology Mapping.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
21	Raymond R. Hoare, Ivan S. Kourtev, Alex K. Jones	Technology Mapping for Field Programmable Gate Arrays using Content-Addressable Memory (CAM).	FCCM	2006	DBLP DOI BibTeX RDF
21	Maxim Teslenko, Elena Dubrova	Hermes: LUT FPGA technology mapping algorithm for area minimization with optimum depth.	ICCAD	2004	DBLP DOI BibTeX RDF
21	Jason Cong, Yean-Yow Hwang	Structural gate decomposition for depth-optimal technology mapping in LUT-based FPGA designs.	ACM Trans. Design Autom. Electr. Syst.	2000	DBLP DOI BibTeX RDF	computer-aided design of VSLI, FPGA, synthesis, system design, decomposition, technology mapping, simplification, programmable logic, logic optimization, delay minimization
21	Jason Cong, Hui Huang 0001	Depth optimal incremental mapping for field programmable gate arrays.	DAC	2000	DBLP DOI BibTeX RDF
21	Aiguo Lu, Erik L. Dagless, Jonathan M. Saul	DART: delay and routability driven technology mapping for LUT based FPGAs.	ICCD	1995	DBLP DOI BibTeX RDF	DART, delay driven technology mapping, LUT based FPGAs, two-phased approach, routability directed delay-optimal mapping, stochastic routability analysis, delay-optimal mapping, field programmable gate arrays, delays, logic design, programmable logic arrays, table lookup, minimisation of switching nets