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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 429 occurrences of 291 keywords
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Results
Found 709 publication records. Showing 709 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
89 | Alex K. Jones, Debabrata Bagchi, Satrajit Pal, Xiaoyong Tang, Alok N. Choudhary, Prithviraj Banerjee |
PACT HDL: a C compiler targeting ASICs and FPGAs with power and performance optimizations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES 2002, Greenoble, France, October 8-11, 2002, pp. 188-197, 2002, ACM, 1-58113-575-0. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
FPGA, low-power, compiler, SoC, synthesis, pipelining, VHDL, IP, ASIC, high-performance, FSM, Verilog, HDL, levelization |
87 | Farzan Fallah, Srinivas Devadas, Kurt Keutzer |
Functional vector generation for HDL models using linearprogramming and Boolean satisfiability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(8), pp. 994-1002, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
87 | Farzan Fallah, Srinivas Devadas, Kurt Keutzer |
Functional Vector Generation for HDL Models Using Linear Programming and 3-Satisfiability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 35th Conference on Design Automation, Moscone center, San Francico, California, USA, June 15-19, 1998., pp. 528-533, 1998, ACM Press, 0-89791-964-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
low power, synthesis, placement, flip-flops, voltage scaling, codec, MPEG4, level converters, design automatian |
67 | Lin Yuan, Pushkin R. Pari, Gang Qu 0001 |
Soft IP Protection: Watermarking HDL Codes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Information Hiding ![In: Information Hiding, 6th International Workshop, IH 2004, Toronto, Canada, May 23-25, 2004, Revised Selected Papers, pp. 224-238, 2004, Springer, 3-540-24207-4. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
67 | Gunther Lehmann, Bernhard Wunder, Klaus D. Müller-Glaser |
Basic concepts for an HDL reverse engineering tool-set. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1996, San Jose, CA, USA, November 10-14, 1996, pp. 134-141, 1996, IEEE Computer Society / ACM, 0-8186-7597-7. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
VHDL Verilog Hardware Description Reuse Reverse Engineering Hypertext CASE Visualization Productivity Design Process Analysis Control Flow ADA Graphical Symbol, VHDL |
62 | Jian Li 0061, Rajesh K. Gupta 0001 |
Decomposition of timed decision tables and its use in presynthesis optimizations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1997, San Jose, CA, USA, November 9-13, 1997, pp. 22-27, 1997, IEEE Computer Society / ACM, 0-8186-8200-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
TDT decomposition, behavioral HDL description, kernel extraction algorithm, optimized HDL description, presynthesis optimizations, system behavior model, timed decision table decomposition, benchmarks, decision tables, circuit synthesis |
60 | Chien-Nan Jimmy Liu, Jing-Yang Jou |
An Efficient Functional Coverage Test for HDL Descriptions at RTL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings of the IEEE International Conference On Computer Design, VLSI in Computers and Processors, ICCD '99, Austin, Texas, USA, October 10-13, 1999, pp. 325-327, 1999, IEEE Computer Society, 0-7695-0406-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
verification, coverage, FSM, HDL |
58 | Wen-Jong Fang, Peng-Cheng Kao, Allen C.-H. Wu |
A Multi-Level FPGA Synthesis Method Supporting HDL Debugging for Emulation-Based Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 1999 Conference on Asia South Pacific Design Automation, Wanchai, Hong Kong, China, January 18-21, 1999, pp. 351-354, 1999, IEEE Computer Society, 0-7803-5012-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
50 | Marco Ottavi, Luca Schiano, Fabrizio Lombardi, Douglas Tougaw |
HDLQ: A HDL environment for QCA design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM J. Emerg. Technol. Comput. Syst. ![In: ACM J. Emerg. Technol. Comput. Syst. 2(4), pp. 243-261, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
CAD, fault injection, QCA, HDL |
49 | Herbert Dawid, Klaus-Jürgen Koch, Johannes Stahl 0004 |
ADPCM codec: from system level description to versatile HDL model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 1997 International Conference on Application-Specific Systems, Architectures, and Processors (ASAP '97), 14-16 July 1997, Zurich, Switzerland, pp. 458-467, 1997, IEEE Computer Society, 0-8186-7958-1. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
differential pulse code modulation, ADPCM codec, system level description, versatile HDL model, architectural design exploration, fast system simulation, adaptive differential pulse code modulation codec module, power analysis, design verification, behavioral synthesis, design reuse, system complexity, design constraints |
48 | Majid Ahmadi, Ashkan Hosseinzadeh Namin, Karl Leboeuf, Huapeng Wu |
Artificial neural networks activation function HDL coder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EIT ![In: 2009 IEEE International Conference on Electro/Information Technology, EIT 2009, Windsor, Ontario, Canada, June 7-9, 2009, pp. 389-392, 2009, IEEE, 978-1-4244-3355-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
48 | Ronny Frevert, Steffen Rülke, Torsten Schäfer, Frank Dresig |
Use of HDL Code Checkers to Support the IP Entrance Check - A Requirement Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 2002 Euromicro Symposium on Digital Systems Design (DSD 2002), Systems-on-Chip, 4-6 September 2002, Dortmund, Germany, pp. 364-370, 2002, IEEE Computer Society, 0-7695-1790-0. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
48 | Adrian Stoica, Didier Keymeulen, Ricardo Salem Zebulum, Michael I. Ferguson |
On Two New Trends in Evolvable Hardware: Employment of HDL-Based Structuring, and Design of Multi-Functional Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Evolvable Hardware ![In: 4th NASA / DoD Workshop on Evolvable Hardware (EH 2002), 15-18 July 2002, Alexandria, VA, USA, pp. 56-59, 2002, IEEE Computer Society, 0-7695-1718-8. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
48 | Klaus Hofmann, Manfred Glesner, Nicu Sebe, Anca Manuela Manolescu, Santiago Marco, Josep Samitier, Jean-Michel Karam, Bernard Courtois |
Generation of the HDL-A-model of a micromembrane from its finite-element-description. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ED&TC ![In: European Design and Test Conference, ED&TC '97, Paris, France, 17-20 March 1997, pp. 108-112, 1997, IEEE Computer Society, 0-8186-7786-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
42 | Makarand Joshi, Hideaki Kobayashi |
Quantifying design productivity: an effort distribution analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EURO-DAC ![In: Proceedings EURO-DAC'95, European Design Automation Conference with EURO-VHDL, Brighton, England, UK, September 18-22, 1995, pp. 476-481, 1995, IEEE Computer Society, 0-8186-7156-4. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
design productivity, effort-distribution, graphical HDL, textual HDL, human interaction, ISO 9000, design resources, design quality |
41 | Jens Horstmannshoff, Thorsten Grötker, Heinrich Meyr |
Mapping multirate dataflow to complex RT level hardware models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 1997 International Conference on Application-Specific Systems, Architectures, and Processors (ASAP '97), 14-16 July 1997, Zurich, Switzerland, pp. 283-, 1997, IEEE Computer Society, 0-8186-7958-1. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
multirate dataflow mapping, complex RT level hardware models, digital signal processing systems, algorithm development phase, data flow specification, RTL target architecture, HDL code generation, cycle based timing model, ASIC design complexity, multirate dataflow graphs, signal processing, hardware architecture |
41 | H. Fatih Ugurdag, Thomas E. Fuhrman |
Autocircuit: a clock edge general behavioral synthesis system with a direct path to physical datapath. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1996 International Conference on Computer Design (ICCD '96), VLSI in Computers and Processors, October 7-9, 1996, Austin, TX, USA, Proceedings, pp. 514-529, 1996, IEEE Computer Society, 0-8186-7554-3. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
Autocircuit, clock edge general behavioral synthesis system, physical datapaths, next-generation synthesis tool, behavioral HDL input descriptions, data-flow representations, use-trees, raw-states, word-oriented synthesis, unique parameterized netlist representation, high level synthesis, high-level design |
40 | Peter A. Jamieson, Kenneth B. Kent |
Odin II: an open-source verilog HDL synthesis tool for FPGA cad flows (abstract only). ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, FPGA 2010, Monterey, California, USA, February 21-23, 2010, pp. 288, 2010, ACM, 978-1-60558-911-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
fpga, verilog hdl |
39 | Eoin Creedon, Michael Manzke |
Scalable high performance computing on FPGA clusters using message passing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: FPL 2008, International Conference on Field Programmable Logic and Applications, Heidelberg, Germany, 8-10 September 2008, pp. 443-446, 2008, IEEE, 978-1-4244-1961-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
39 | Alex K. Jones, Prithviraj Banerjee |
An automated and power-aware framework for utilization of IP cores in hardware generated from C descriptions targeting FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2003, Monterey, CA, USA, February 23-25, 2003, pp. 244, 2003, ACM, 1-58113-651-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
39 | Tohru Ishihara, Satoshi Komatsu, Makoto Ikeda, Masahiro Fujita, Kunihiro Asada |
Comparative Study On Verilog-Based And C-Based Hardware Design Education. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MSE ![In: 2003 International Conference on Microelectronics Systems Education, MSE 2003, Educating Tomorrow's Microsystems Designers, Anaheim, CA, USA, June 1-2, 2003, pp. 41-42, 2003, IEEE Computer Society, 0-7695-1973-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
39 | Farzan Fallah, Srinivas Devadas, Kurt Keutzer |
OCCOM-efficient computation of observability-based code coveragemetrics for functional verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(8), pp. 1003-1015, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
39 | Farzan Fallah, Srinivas Devadas, Kurt Keutzer |
OCCOM: Efficient Computation of Observability-Based Code Coverage Metrics for Functional Verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 35th Conference on Design Automation, Moscone center, San Francico, California, USA, June 15-19, 1998., pp. 152-157, 1998, ACM Press, 0-89791-964-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
high-level synthesis, telecommunication |
38 | Siva Kumar Sastry Hari, Vishnu Vardhan Reddy Konda, V. Kamakoti 0001, Vivekananda M. Vedula, K. S. Maneperambil |
Automatic Constraint Based Test Generation for Behavioral HDL Models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 16(4), pp. 408-421, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
38 | Yuki Kobayashi, Shinsuke Kobayashi, Koji Okuda, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai |
Synthesizable HDL generation method for configurable VLIW processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, Yokohama, Japan, January 27-30, 2004, pp. 842-845, 2004, IEEE Computer Society, 0-7803-8175-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
38 | Liang Zhang 0012, Michael S. Hsiao, Indradeep Ghosh |
Automatic Design Validation Framework for HDL Descriptions via RTL ATPG. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, pp. 148-153, 2003, IEEE Computer Society, 0-7695-1951-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
38 | Rolf Drechsler, Nicole Drechsler |
GAME-HDL: Implementation of Evolutionary Algorithms Using Hardware Description Languages. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EvoWorkshops ![In: Applications of Evolutionary Computing, EvoWorkshop 2003: EvoBIO, EvoCOP, EvoIASP, EvoMUSART, EvoROB, and EvoSTIM, Essex, UK, April 14-16, 2003, Proceedings, pp. 378-387, 2003, Springer, 3-540-00976-0. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
38 | Arash Saifhashemi, Hossein Pedram |
Verilog HDL, powered by PLI: a suitable framework for describing and modeling asynchronous circuits at all levels of abstraction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 40th Design Automation Conference, DAC 2003, Anaheim, CA, USA, June 2-6, 2003, pp. 330-333, 2003, ACM, 1-58113-688-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
CHP, PLI, CSP, asynchronous circuits, channel, verilog |
38 | Hen-Ming Lin, Jing-Yang Jou |
On tri-state buffer inference in HDL synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, pp. 45-48, 2001, IEEE, 0-7803-6685-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
38 | Wen-Jong Fang, Allen C.-H. Wu |
Integrating HDL Synthesis and Partitioning for Multi-FPGA Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 15(2), pp. 65-72, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
38 | Yatin Vasant Hoskote, Jacob A. Abraham, Donald S. Fussell, John Moondanos |
Automatic verification of implementations of large circuits against HDL specifications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(3), pp. 217-228, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
38 | Rainer Leupers, Peter Marwedel |
Retargetable generation of code selectors from HDL processor models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ED&TC ![In: European Design and Test Conference, ED&TC '97, Paris, France, 17-20 March 1997, pp. 140-144, 1997, IEEE Computer Society, 0-8186-7786-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
38 | Timothy Kam, P. A. Subrahmanyam |
Comparing layouts with HDL models: a formal verification technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(4), pp. 503-509, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
37 | Saman Fröhlich, Rolf Drechsler |
LiM-HDL: HDL-Based Synthesis for In-Memory Computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2022 Design, Automation & Test in Europe Conference & Exhibition, DATE 2022, Antwerp, Belgium, March 14-23, 2022, pp. 1395-1400, 2022, IEEE, 978-3-9819263-6-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
37 | R. Peschke, K. Nishimura, G. Varner |
ARGG-HDL: A High Level Python Based Object-Oriented HDL Framework. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2011.02626, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP BibTeX RDF |
|
32 | Ali Husein El-Mousa, Nasser Anssari, Ashraf Al-Suyyagh, Hamzah Al-Zubi |
The Design of a USART IP Core. ![Search on Bibsonomy](Pics/bibsonomy.png) |
World Congress on Engineering (Selected Papers) ![In: Advances in Electrical Engineering and Computational Science, [revised and extended papers from the World Congress on Engineering, WCE 2008, London, UK, July 2-4, 2008], pp. 365-376, 2008, Springer, 978-90-481-2310-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
addressable USART, multi-drop networks, FPGA, Embedded systems, HDL, IP core |
32 | Jainendra Kumar, Noel R. Strader, Jeff Freeman, Michael Miller |
Emulation verification of the Motorola 68060. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1995 International Conference on Computer Design (ICCD '95), VLSI in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings, pp. 150-158, 1995, IEEE Computer Society, 0-8186-7165-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
emulation verification, Motorola 68060, hardware logic emulation, configurable hardware, circuit verification, pseudo-random verification vectors, software application programs, formal verification, microprocessors, reconfigurable architectures, logic CAD, digital simulation, circuit analysis computing, RTL, hardware description languages, hardware description language, microprocessor chips, HDL, gate-level |
31 | Choudhury A. Rahman, Wael M. Badawy |
A quarter pel full search block motion estimation architecture for H.264/AVC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICME ![In: Proceedings of the 2005 IEEE International Conference on Multimedia and Expo, ICME 2005, July 6-9, 2005, Amsterdam, The Netherlands, pp. 414-417, 2005, IEEE Computer Society, 0-7803-9331-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
CIF frame sequence, quarter pel full search, block motion estimation architecture, H.264-AVC encoder, Xilinx Virtex2 FPGA, field programmable gate array, hardware description language, Verilog HDL |
31 | Sasha Novakovsky, Shy Shyman, Ziyad Hanna |
High capacity and automatic functional extraction tool for industrial VLSI circuit designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, ICCAD 2002, San Jose, California, USA, November 10-14, 2002, pp. 520-525, 2002, ACM / IEEE Computer Society, 0-7803-7607-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Formal Equivalence Verification (FEV), Hardware Description Languages (HDL), Switch Level Analysis, functional abstraction, satisfiability procedures, synthesis, Design For Testability (DFT), logic simulation, Binary Decision Diagrams (BDDs) |
31 | Marcel Jacomet, Roger Wälti, Lukas Winzenried, Jaime Perez, Martin Gysel |
ProTest: A Low Cost Rapid Prototyping Test System for ASICs and FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 6th Asian Test Symposium (ATS '97), 17-18 November 1997, Akita, Japan, pp. 138-142, 1997, IEEE Computer Society, 0-8186-8209-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
test bench, test machine, CAT-tool, ProTest, FPGA, VHDL, rapid prototyping, Verilog-HDL |
29 | Jacob N. Allen, Hoda S. Abdel-Aty-Zohdy, Robert L. Ewing |
Agile hardware development with rapid hardware definition language. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EIT ![In: 2009 IEEE International Conference on Electro/Information Technology, EIT 2009, Windsor, Ontario, Canada, June 7-9, 2009, pp. 383-388, 2009, IEEE, 978-1-4244-3355-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
29 | Indradeep Ghosh |
High Level Test Generation for Custom Hardware: An Industrial Perspective. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 14th Asian Test Symposium (ATS 2005), 18-21 December 2005, Calcutta, India, pp. 458, 2005, IEEE Computer Society, 0-7695-2481-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
29 | Masaharu Imai, Akira Kitajima |
Verification Challenges in Configurable Processor Design with ASIP Meister. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHARME ![In: Correct Hardware Design and Verification Methods, 13th IFIP WG 10.5 Advanced Research Working Conference, CHARME 2005, Saarbrücken, Germany, October 3-6, 2005, Proceedings, pp. 2, 2005, Springer, 3-540-29105-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
29 | Kausik Datta, Partha Pratim Das |
Assertion Based Verification Using HDVL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 17th International Conference on VLSI Design (VLSI Design 2004), with the 3rd International Conference on Embedded Systems Design, 5-9 January 2004, Mumbai, India, pp. 319-, 2004, IEEE Computer Society, 0-7695-2072-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
29 | Lijun Li, Hai Huang, Carl Tropper |
DVS: An Object-Oriented Framework for Distributed Verilog Simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PADS ![In: Proceedings of the 17th Workshop on Parallel and Distributed Simulation, PADS 2003, June 10-13, 2003, San Diego, CA, USA, pp. 173-180, 2003, IEEE Computer Society, 0-7695-1970-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
29 | Raik Brinkmann, Rolf Drechsler |
RTL-Datapath Verification using Integer Linear Programming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC/VLSI Design ![In: Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), and the 15th International Conference on VLSI Design (VLSI Design 2002), Bangalore, India, January 7-11, 2002, pp. 741-746, 2002, IEEE Computer Society, 0-7695-1299-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
29 | Philippe Poure, Fabrice Aubépart, Francis Braun |
A Design Methodology for Hardware Prototyping of Integrated AC Drive Control: Application to Direct Torque Control of an Induction Machine. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE International Workshop on Rapid System Prototyping ![In: Proceedings of the 11th IEEE International Workshop on Rapid System Prototyping (RSP 2000), Paris, France, June 21-23, 2000, pp. 90-, 2000, IEEE Computer Society, 0-7695-0668-2. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
29 | Marius Pirvu, Laxmi N. Bhuyan, Rabi N. Mahapatra |
Hierarchical Simulation of a Multiprocessor Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, ICCD '00, Austin, Texas, USA, September 17-20, 2000, pp. 585-588, 2000, IEEE Computer Society, 0-7695-0801-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
29 | Richard Goering, Clifford E. Cummings, Steven E. Schulz, Simon Davidman, John Sanguinetti, Joachim Kunkel, Oz Levia |
The future of system design languages (panel session). ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 37th Conference on Design Automation, Los Angeles, CA, USA, June 5-9, 2000., pp. 438-439, 2000, ACM. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
29 | B. Romanowicz, M. Laudon, P. Lerch, Philippe Renaud, Hans Peter Amann, A. Boegli, Vincent Moser, Fausto Pellandini |
Modeling and simulation of electromechanical transducers in microsystems using an analog hardware description language. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ED&TC ![In: European Design and Test Conference, ED&TC '97, Paris, France, 17-20 March 1997, pp. 119-123, 1997, IEEE Computer Society, 0-8186-7786-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
29 | Stan Y. Liao, Steven W. K. Tjiang, Rajesh K. Gupta 0001 |
An Efficient Implementation of Reactivity for Modeling Hardware in the Scenic Design Environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 34st Conference on Design Automation, Anaheim, California, USA, Anaheim Convention Center, June 9-13, 1997., pp. 70-75, 1997, ACM Press, 0-89791-920-3. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
C++ |
29 | Robert Piloty, Mario Barbacci, Dominique Borrione, Donald L. Dietmeyer, Fredrick J. Hill, Patrick Skelly |
CONLAN: a formal construction method for hardware description languages: basic principles. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AFIPS National Computer Conference ![In: American Federation of Information Processing Societies: 1980 National Computer Conference, 19-22 May 1980, Anaheim, California, USA, pp. 209-217, 1980, AFIPS Press, 978-1-4503-7923-6. The full citation details ...](Pics/full.jpeg) |
1980 |
DBLP DOI BibTeX RDF |
|
28 | Tai-Ying Jiang, Chien-Nan Jimmy Liu, Jing-Yang Jou |
Accurate Rank Ordering of Error Candidates for Efficient HDL Design Debugging. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(2), pp. 272-284, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
28 | Kyuho Shim, Young-Rae Cho, Namdo Kim, Hyuncheol Baik, Kyungkuk Kim, Dusung Kim, Jaebum Kim, Byeongun Min, Kyumyung Choi, Maciej J. Ciesielski, Seiyang Yang |
A fast two-pass HDL simulation with on-demand dump. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 13th Asia South Pacific Design Automation Conference, ASP-DAC 2008, Seoul, Korea, January 21-24, 2008, pp. 422-427, 2008, IEEE, 978-1-4244-1921-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
28 | Encarnación Castillo, Uwe Meyer-Bäse, Antonio García 0001, Luis Parrilla 0001, Antonio Lloris-Ruíz |
IPP@HDL: Efficient Intellectual Property Protection Scheme for IP Cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 15(5), pp. 578-591, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
28 | Panagiotis D. Vouzis, Caroline Collange, Mark G. Arnold |
Cotransformation Provides Area and Accuracy Improvement in an HDL Library for LNS Subtraction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: Tenth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2007), 29-31 August 2007, Lübeck, Germany, pp. 85-93, 2007, IEEE Computer Society, 0-7695-2978-X. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
28 | Encarnación Castillo, Luis Parrilla 0001, Antonio García 0001, Uwe Meyer-Bäse, Antonio Lloris-Ruíz |
Intellectual Property Protection of HDL IP Cores Through Automated Sognature Hosting. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: FPL 2007, International Conference on Field Programmable Logic and Applications, Amsterdam, The Netherlands, 27-29 August 2007, pp. 183-188, 2007, IEEE, 1-4244-1060-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
28 | Koen Bertels, Georgi Kuzmanov, Elena Moscu Panainte, Georgi Gaydadjiev, Yana Yankova, Vlad Mihai Sima, Kamana Sigdel, Roel Meeuws, Stamatis Vassiliadis |
HARTES Toolchain Early Evaluation: Profiling, Compilation and HDL Generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: FPL 2007, International Conference on Field Programmable Logic and Applications, Amsterdam, The Netherlands, 27-29 August 2007, pp. 402-408, 2007, IEEE, 1-4244-1060-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
28 | Margrit R. Krug, Marcelo Lubaszewski, Marcelo de Souza Moraes |
Improving ATPG Gate-Level Fault Coverage by using Test Vectors generated from Behavioral HDL Descriptions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: IFIP VLSI-SoC 2006, IFIP WG 10.5 International Conference on Very Large Scale Integration of System-on-Chip, Nice, France, 16-18 October 2006, pp. 314-319, 2006, IEEE. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
28 | Hessa Al-Junaid, Tom J. Kazmierski |
HDL models of ferromagnetic core hysteresis using timeless discretisation of the magnetic slope. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006, pp. 644-645, 2006, European Design and Automation Association, Leuven, Belgium, 3-9810801-1-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
28 | Robert M. Senger, Eric D. Marsman, Gordy A. Carichner, Sundus Kubba, Michael S. McCorquodale, Richard B. Brown |
Low-latency, HDL-synthesizable dynamic clock frequency controller with self-referenced hybrid clocking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
28 | Mihai Udrescu, Lucian Prodan, Mircea Vladutiu |
The Bubble Bit Technique as Improvement of HDL-Based Quantum Circuits Simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Annual Simulation Symposium ![In: Proceedings 38th Annual Simulation Symposium (ANSS-38 2005), 4-6 April 2005, San Diego, CA, USA, pp. 217-224, 2005, IEEE Computer Society, 0-7695-2322-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
28 | Tai-Ying Jiang, Chien-Nan Jimmy Liu, Jing-Yang Jou |
Estimating likelihood of correctness for error candidates to assist debugging faulty HDL designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (6) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 5682-5685, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
28 | Elena Dubrova |
Linear-time algorithm for computing minimum checkpoint sets for simulation-based verification of HDL programs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (3) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 2212-2215, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
28 | Raymond Hoare, Shen Chih Tung |
Combining Mentor Graphics? HDL Designer FPGA Flow with a Reconfigurable System on a Programmable Chip, Educational Opportunity or Insanity? ![Search on Bibsonomy](Pics/bibsonomy.png) |
MSE ![In: 2003 International Conference on Microelectronics Systems Education, MSE 2003, Educating Tomorrow's Microsystems Designers, Anaheim, CA, USA, June 1-2, 2003, pp. 128-130, 2003, IEEE Computer Society, 0-7695-1973-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
28 | Farzan Fallah, Pranav Ashar, Srinivas Devadas |
Functional vector generation for sequential HDL models under an observability-based code coverage metric. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 10(6), pp. 919-923, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
28 | Jian Li 0061, Rajesh K. Gupta 0001 |
HDL presynthesis optimizations using a tabular model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 8(4), pp. 369-378, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
28 | Chien-Nan Jimmy Liu, Jing-Yang Jou |
An Automatic Controller Extractor for HDL Descriptions at the RTL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 17(3), pp. 72-77, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
28 | Ivan Blunno, Luciano Lavagno |
Automated Synthesis of Micro-Pipelines from Behavioral Verilog HDL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000), 2-6 April 2000, Eilat, Israel, pp. 84-92, 2000, IEEE Computer Society, 0-7695-0586-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
28 | Marcelino B. Santos, João Paulo Teixeira 0001 |
Defect-Oriented Mixed-Level Fault Simulation of Digital Systems-on-a-Chip Using HDL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1999 Design, Automation and Test in Europe (DATE '99), 9-12 March 1999, Munich, Germany, pp. 549-, 1999, IEEE Computer Society / ACM, 0-7695-0078-1. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
28 | Hsiao-Pin Su, Allen C.-H. Wu, Youn-Long Lin |
Performance-driven soft-macro clustering and placement by preserving HDL design hierarchy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 1998 International Symposium on Physical Design, ISPD 1998, Monterey, CA, USA, April 6-8, 1998, pp. 12-17, 1998, ACM, 1-58113-021-X. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
28 | Rajesh K. Gupta 0001, Daniel Gajski, Randy Allen, Yatin Trivedi |
Opportunities and pitfalls in HDL-based system design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1996 International Conference on Computer Design (ICCD '96), VLSI in Computers and Processors, October 7-9, 1996, Austin, TX, USA, Proceedings, pp. 56-57, 1996, IEEE Computer Society, 0-8186-7554-3. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
textual Hardware Description Languages, system designs, VHDL, modeling language, hardware description languages, Verilog, HDLs, hardware systems |
28 | Yaohan Chu, Donald L. Dietmeyer, James R. Duley, Fredrick J. Hill, Mario Barbacci, Charles W. Rose, Greg M. Ordy, Bill Johnson, Martin Roberts |
Three Decades of HDLs: Part I, CDL Through TI-HDL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 9(2), pp. 69-81, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
22 | Brian Butka, Janusz Zalewski, Andrew J. Kornecki |
Issues in Tool Qualification for Safety-Critical Hardware: What Formal Approaches Can and Cannot Do. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAFECOMP ![In: Computer Safety, Reliability, and Security, 28th International Conference, SAFECOMP 2009, Hamburg, Germany, September 15-18, 2009. Proceedings, pp. 201-214, 2009, Springer, 978-3-642-04467-0. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Tool Qualification, Formal Methods, Safety-Critical Systems, Hardware Design, HDL, PLD |
22 | Christopher T. Johnston, Paul J. Lyons, Donald G. Bailey |
User evaluation and overview of a visual language for real time image processing on FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHINZ ![In: Proceedings of the 10th ACM SIGCHI New Zealand Chapter's International Conference on Computer-Human Interaction, CHINZ 2009, Auckland, New Zealand, July 6-7, 2009, pp. 85-92, 2009, ACM, 978-1-60558-574-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
FPGA, image processing, visual programming language, HDL |
22 | Alexander B. Smirnov, Alexander Taubin, Ming Su, Mark G. Karpovsky |
An Automated Fine-Grain Pipelining Using Domino Style Asynchronous Library. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACSD ![In: Fifth International Conference on Application of Concurrency to System Design (ACSD 2005), 6-9 June 2005, St. Malo, France, pp. 68-76, 2005, IEEE Computer Society, 0-7695-2363-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
asynchronous EDA, QDI, synthesis, ASIC, HDL |
22 | Dave Protheroe, Francesco Pessolano |
An Objective Measure of Digital System Design Quality. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 1st International Symposium on Quality of Electronic Design (ISQED 2000), 20-22 March 2000, San Jose, CA, USA, pp. 227-233, 2000, IEEE Computer Society, 0-7695-0525-2. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Design, Specification, Metrics, Quality, VHDL, Digital, Circuit, HDL |
22 | Sy Wong, Gertrude Levine |
Kernel Ada to Unify Hardware and Software Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGAda ![In: Proceedings of the ACM SIGAda Annual International Conference on Ada Technology, SIGAda 1998, Washington, DC, USA, November 8-12, 1998, pp. 28-38, 1998, ACM, 1-58113-033-3. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
Ada, Ada, VHDL, EDA, hardware description language, HDL |
21 | Azam Beg, Faheem Ahmed, Piers Campbell |
Hybrid OCR Techniques for Cursive Script Languages - A Review and Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CICSyN ![In: Second International Conference on Computational Intelligence, Communication Systems and Networks, CICSyN 2010, Liverpool, UK, 28-30 July, 2010, pp. 101-105, 2010, IEEE Computer Society, 978-1-4244-7837-8. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
hand-writing recognition, Arabic OCR, Farsi/Persian OCR, Urdu OCR, HDL models, optical character recognition, hardware implementation, Text recognition |
21 | Xiumin Wang, Yang Zhang, Qiang Ye, Shihua Yang |
A New Algorithm for Designing Square Root Calculators Based on FPGA with Pipeline Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HIS (1) ![In: 9th International Conference on Hybrid Intelligent Systems (HIS 2009), August 12-14, 2009, Shenyang, China, pp. 99-102, 2009, IEEE Computer Society, 978-0-7695-3745-0. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
FPGA, algorithm, pipeline, square root, Verilog HDL |
21 | Yang Zhang, Xiumin Wang, Yuduo Wang |
A New Design of HDB3 Encoder and Decoder Based on FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HIS (1) ![In: 9th International Conference on Hybrid Intelligent Systems (HIS 2009), August 12-14, 2009, Shenyang, China, pp. 210-213, 2009, IEEE Computer Society, 978-0-7695-3745-0. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
HDB3, FPGA, encoder, decoder, Verilog HDL |
21 | K. Najeeb, Vishnu Vardhan Reddy Konda, Siva Kumar Sastry Hari, V. Kamakoti 0001, Vivekananda M. Vedula |
Power Virus Generation Using Behavioral Models of Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 25th IEEE VLSI Test Symposium (VTS 2007), 6-10 May 2007, Berkeley, California, USA, pp. 35-42, 2007, IEEE Computer Society, 0-7695-2812-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Dynamic power dissipation, Power virus, Integer Constraint Solvers, Hardware Description Languages (HDL), Behavioral Models |
21 | Salvador Mir, Libor Rufer, Bernard Courtois |
On-chip testing of embedded transducers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 17th International Conference on VLSI Design (VLSI Design 2004), with the 3rd International Conference on Embedded Systems Design, 5-9 January 2004, Mumbai, India, pp. 463-, 2004, IEEE Computer Society, 0-7695-2072-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
failure mechanisms, A-HDL, fault modeling, fault simulation, defects, MEMS, self-test |
21 | Takao Onoye, Yukihiro Nakamura, Atsuhito Shigiya, Keishi Chikamura, Kosuke Tsujino, Tomonori Izumi, Hirofumi Yamamoto |
System-Level Design of IEEE1394 Bus Segment Bridge. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSS ![In: Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), October 2-4, 2002, Kyoto, Japan, pp. 74-79, 2002, ACM / IEEE Computer Society, 1-58113-576-9. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
HW/SW co-simulation, IEEE1394, PLI, bus bridge, C/C++, verilog-HDL |
20 | Mark Horowitz, Metha Jeeradit, Frances Lau, Sabrina Liao, ByongChan Lim, James Mao |
Fortifying analog models with equivalence checking and coverage analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 47th Design Automation Conference, DAC 2010, Anaheim, California, USA, July 13-18, 2010, pp. 425-430, 2010, ACM, 978-1-4503-0002-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
analog validation, model-first design, design methodology, fault coverage, equivalence checking, formal validation |
20 | Karin Avnit, Vijay D'Silva, Arcot Sowmya, S. Ramesh, Sri Parameswaran |
Provably correct on-chip communication: A formal approach to automatic protocol converter synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 14(2), pp. 19:1-19:41, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
converter synthesis, protocol compatibility, System-on-chip, automatic design |
20 | Florian Eibensteiner, Rainer Findenig, Markus Pfaff |
SynPSL: Behavioral Synthesis of PSL Assertions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROCAST ![In: Computer Aided Systems Theory - EUROCAST 2009, 12th International Conference, Las Palmas de Gran Canaria, Spain, February 15-20, 2009, Revised Selected Papers, pp. 69-74, 2009, Springer, 978-3-642-04771-8. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Synthesis, PSL, Assertion-based Verification |
20 | Michael T. Frederick, Arun K. Somani |
Beyond the arithmetic constraint: depth-optimal mapping of logic chains in LUT-based FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 16th International Symposium on Field Programmable Gate Arrays, FPGA 2008, Monterey, California, USA, February 24-26, 2008, pp. 37-46, 2008, ACM, 978-1-59593-934-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
carry chain, depth optimal mapping, logic chain |
20 | Sankalita Saha, Jason Schlessman, Sebastian Puthenpurayil, Shuvra S. Bhattacharyya, Wayne H. Wolf |
An Optimized Message Passing Framework for Parallel Implementation of Signal Processing Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2008, Munich, Germany, March 10-14, 2008, pp. 1220-1225, 2008, ACM, 978-3-9810801-3-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
20 | Leran Wang, Tom J. Kazmierski, Bashir M. Al-Hashimi, Stephen P. Beeby, Russel N. Torah |
Integrated approach to energy harvester mixed technology modelling and performance optimisation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2008, Munich, Germany, March 10-14, 2008, pp. 704-709, 2008, ACM, 978-3-9810801-3-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
20 | Karl Meier, Alessandro Forin |
Hardware Compilation from Machine Code with M2V. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 16th IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2008, 14-15 April 2008, Stanford, Palo Alto, California, USA, pp. 293-295, 2008, IEEE Computer Society, 978-0-7695-3307-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
20 | Sangeetha Sudhakrishnan, Liying Su, Jose Renau |
Processor Verification with hwBugHunt. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 9th International Symposium on Quality of Electronic Design (ISQED 2008), 17-19 March 2008, San Jose, CA, USA, pp. 224-229, 2008, IEEE Computer Society, 978-0-7695-3117-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
20 | Kyuho Shim, Kesava R. Talupuru, Maciej J. Ciesielski, Seiyang Yang |
Simulation Acceleration with HW Re-Compilation Avoidance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 21st International Conference on VLSI Design (VLSI Design 2008), 4-8 January 2008, Hyderabad, India, pp. 487-491, 2008, IEEE Computer Society, 0-7695-3083-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
20 | John R. Shell, Yonglian Wang, Nazeih M. Botros |
Biological Mechanism on a Chip: Modeling and Realization of Growth Hormone Secretion Mechanism. ![Search on Bibsonomy](Pics/bibsonomy.png) |
BIBE ![In: Proceedings of the 7th IEEE International Conference on Bioinformatics and Bioengineering, BIBE 2007, October 14-17, 2007, Harvard Medical School, Boston, MA, USA, pp. 546-552, 2007, IEEE Computer Society, 978-1-4244-1509-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
20 | Yan Lin Aung, Douglas L. Maskell, Timothy F. Oliver, Bertil Schmidt, William Bong |
C-Based Design Methodology for FPGA Implementation of ClustalW MSA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PRIB ![In: Pattern Recognition in Bioinformatics, Second IAPR International Workshop, PRIB 2007, Singapore, October 1-2, 2007, Proceedings, pp. 11-18, 2007, Springer, 978-3-540-75285-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
ClustalW, FPGA, multiple sequence alignment, sequence analysis |
20 | Walid A. Najjar |
Compiling code accelerators for FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2007 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2007, Salzburg, Austria, September 30 - October 3, 2007, pp. 1-2, 2007, ACM. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
FPGA code acceleration |
20 | Jen-Chieh Ou, Daniel G. Saab, Qiang Qiang, Jacob A. Abraham |
Reducing verification overhead with RTL slicing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, Stresa, Lago Maggiore, Italy, March 11-13, 2007, pp. 399-404, 2007, ACM, 978-1-59593-605-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
verification, test, CAD |
20 | Vahid Lari, Mehdi Dehbashi, Seyed Ghassem Miremadi, Navid Farazmand |
Assessment of Message Missing Failures in FlexRay-Based Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PRDC ![In: 13th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC 2007), 17-19 December, 2007, Melbourne, Victoria, Australia, pp. 191-194, 2007, IEEE Computer Society, 0-7695-3054-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
20 | Hessa Al-Junaid, Tom J. Kazmierski, Peter R. Wilson, Jerzy Baranowski |
Timeless Discretization of Magnetization Slope in the Modeling of Ferromagnetic Hysteresis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(12), pp. 2757-2764, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
20 | Liang Zhang 0012, Indradeep Ghosh, Michael S. Hsiao |
A Framework for Automatic Design Validation of RTL Circuits Using ATPG and Observability-Enhanced Tag Coverage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(11), pp. 2526-2538, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
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