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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 80 occurrences of 60 keywords
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Results
Found 78 publication records. Showing 78 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
78 | Shuqing Zhao, Daniel D. Gajski |
Structural operational semantics for supporting multi-cycle operations in RTL HDLs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MEMOCODE ![In: 3rd ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2005), 11-14 July 2005, Verona, Italy, Proceedings, pp. 45-53, 2005, IEEE Computer Society, 0-7803-9227-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
78 | Yaohan Chu, Donald L. Dietmeyer, James R. Duley, Fredrick J. Hill, Mario Barbacci, Charles W. Rose, Greg M. Ordy, Bill Johnson, Martin Roberts |
Three Decades of HDLs: Part I, CDL Through TI-HDL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 9(2), pp. 69-81, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
78 | Dominique Borrione, Robert Piloty, Dwight D. Hill, Karl J. Lieberherr, Philip Moorby |
Three Decades of HDLs: Part II, Conlan Through Verilog. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 9(3), pp. 54-63, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
60 | Rajesh K. Gupta 0001, Daniel Gajski, Randy Allen, Yatin Trivedi |
Opportunities and pitfalls in HDL-based system design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1996 International Conference on Computer Design (ICCD '96), VLSI in Computers and Processors, October 7-9, 1996, Austin, TX, USA, Proceedings, pp. 56-57, 1996, IEEE Computer Society, 0-8186-7554-3. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
textual Hardware Description Languages, system designs, VHDL, modeling language, hardware description languages, Verilog, HDLs, hardware systems |
48 | Edmund M. Clarke, Masahiro Fujita, Sreeranga P. Rajan, Thomas W. Reps, Subash Shankar, Tim Teitelbaum |
Program slicing for VHDL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Softw. Tools Technol. Transf. ![In: Int. J. Softw. Tools Technol. Transf. 4(1), pp. 125-137, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Model checking, Formal verification, VHDL, Program slicing, Hardware description languages |
46 | R. James Duckworth |
Embedded System Design with FPGAs Using HDLs (Lessons Learned and Pitfalls to Be Avoided). ![Search on Bibsonomy](Pics/bibsonomy.png) |
MSE ![In: 2005 International Conference on Microelectronics Systems Education, MSE 2005, Anaheim, CA, USA, June 12-13, 2005, pp. 35-36, 2005, IEEE Computer Society, 0-7695-2374-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
46 | Mihai Udrescu, Lucian Prodan, Mircea Vladutiu |
Using HDLs for describing quantum circuits: a framework for efficient quantum algorithm simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Conf. Computing Frontiers ![In: Proceedings of the First Conference on Computing Frontiers, 2004, Ischia, Italy, April 14-16, 2004, pp. 96-110, 2004, ACM, 1-58113-741-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
bubble logic, simulation, views, hardware description languages, quantum algorithms, quantum circuits, entanglement |
32 | Walid A. Najjar |
Compiling code accelerators for FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2007 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2007, Salzburg, Austria, September 30 - October 3, 2007, pp. 1-2, 2007, ACM. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
FPGA code acceleration |
32 | Raymond Hoare, Shen Chih Tung |
Combining Mentor Graphics? HDL Designer FPGA Flow with a Reconfigurable System on a Programmable Chip, Educational Opportunity or Insanity? ![Search on Bibsonomy](Pics/bibsonomy.png) |
MSE ![In: 2003 International Conference on Microelectronics Systems Education, MSE 2003, Educating Tomorrow's Microsystems Designers, Anaheim, CA, USA, June 1-2, 2003, pp. 128-130, 2003, IEEE Computer Society, 0-7695-1973-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
32 | Katsuyuki Ochiai, Hiroe Iwasaki, Jiro Naganuma, Makoto Endo, Takeshi Ogura |
High-speed Software-based Platform for Embedded Software of a Single-chip MPEG-2 Video Encoder LSI with HDTV Scalabilit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1999 Design, Automation and Test in Europe (DATE '99), 9-12 March 1999, Munich, Germany, pp. 303-308, 1999, IEEE Computer Society / ACM, 0-7695-0078-1. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
32 | Edmund M. Clarke, Masahiro Fujita, Sreeranga P. Rajan, Thomas W. Reps, Subash Shankar, Tim Teitelbaum |
Program Slicing of Hardware Description Languages. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHARME ![In: Correct Hardware Design and Verification Methods, 10th IFIP WG 10.5 Advanced Research Working Conference, CHARME '99, Bad Herrenalb, Germany, September 27-29, 1999, Proceedings, pp. 298-312, 1999, Springer, 3-540-66559-5. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
30 | Sheng-Hong Wang, Hunter James Coffman, Kenneth Mayer, Sakshi Garg 0002, Jose Renau |
A Multi-threaded Fast Hardware Compiler for HDLs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CC ![In: Proceedings of the 32nd ACM SIGPLAN International Conference on Compiler Construction, CC 2023, Montréal, QC, Canada, February 25-26, 2023, pp. 25-36, 2023, ACM, 979-8-4007-0088-0. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
30 | Haven Blake Skinner, Rafael Trapani Possignolo, Sheng-Hong Wang, Jose Renau |
LiveSim: A Fast Hot Reload Simulator for HDLs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPASS ![In: IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS 2020, Boston, MA, USA, August 23-25, 2020, pp. 126-135, 2020, IEEE, 978-1-7281-4798-7. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
30 | Haven Blake Skinner, Rafael Trapani Possignolo, Jose Renau |
Liam: an actor based programming model for HDLs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MEMOCODE ![In: Proceedings of the 15th ACM-IEEE International Conference on Formal Methods and Models for System Design, MEMOCODE 2017, Vienna, Austria, September 29 - October 02, 2017, pp. 185-188, 2017, ACM, 978-1-4503-5093-8. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
30 | Robert Wille, Oliver Keszöcze, Lars Othmer, Michael Kirkedal Thomsen, Rolf Drechsler |
Initial Ideas for Automatic Design and Verification of Control Logic in Reversible HDLs - Work in Progress Report. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RC ![In: Reversible Computation - 8th International Conference, RC 2016, Bologna, Italy, July 7-8, 2016, Proceedings, pp. 160-166, 2016, Springer, 978-3-319-40577-3. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
30 | Mohsen Ghasempour, Jonathan Heathcote, Javier Navaridas, Luis A. Plana, Jim D. Garside, Mikel Luján |
Accelerating Interconnect Analysis Using High-Level HDLs and FPGA, SpiNNaker as a Case Study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 23rd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2015, Vancouver, BC, Canada, May 2-6, 2015, pp. 96, 2015, IEEE Computer Society, 978-1-4799-9969-9. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
30 | Gongyu Wang, Herman Lam, Alan D. George, Glen Edwards |
Performance and productivity evaluation of hybrid-threading HLS versus HDLs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPEC ![In: 2015 IEEE High Performance Extreme Computing Conference, HPEC 2015, Waltham, MA, USA, September 15-17, 2015, pp. 1-7, 2015, IEEE, 978-1-4673-9286-0. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
30 | Zainalabedin Navabi |
HDLs evolve as they affect design methodology for a higher abstraction and a better integration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DTIS ![In: 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, DTIS 2015, Napoli, Italy, April 21-23, 2015, pp. 1, 2015, IEEE, 978-1-4799-1999-4. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
30 | Jung-Lin Yang, Jau-Cheng Wei, Shin-Nung Lu |
HDLs Modeling Technique for Burst-Mode and Extended Burst-Mode Asynchronous Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. ![In: IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 93-A(12), pp. 2590-2599, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
30 | John A. Nestor |
Teaching Computer Organization with HDLs: An Incremental Approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MSE ![In: 2005 International Conference on Microelectronics Systems Education, MSE 2005, Anaheim, CA, USA, June 12-13, 2005, pp. 77-78, 2005, IEEE Computer Society, 0-7695-2374-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
30 | Chun Hok Ho, Kuen Hung Tsoi, Jackson H. C. Yeung, Yuet Ming Lam, Kin-Hong Lee, Philip Heng Wai Leong, Ralf Ludewig, Peter Zipf, Alberto García Ortiz, Manfred Glesner |
Arbitrary function approximation in HDLs with application to the N-body problem. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPT ![In: Proceedings of the 2003 IEEE International Conference on Field-Programmable Technology, Tokyo, Japan, FPT 2003, December 15-17, 2003, pp. 84-91, 2003, IEEE. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
30 | Zvonko G. Vranesic, Stephen Dean Brown |
Use of HDLs in teaching of computer hardware courses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WCAE ![In: Proceedings of the 2003 workshop on Computer architecture education - Held in conjunction with the 30th International Symposium on Computer Architecture, WCAE@ISCA 2003, San Diego, California, USA, June 8, 2003, pp. 16, 2003, ACM, 978-1-4503-4732-7. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
30 | Tai-Ying Jiang, Chien-Nan Jimmy Liu, Jing-Yang Jou |
Effective Error Diagnosis for RTL Designs in HDLs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, pp. 362-367, 2002, IEEE Computer Society, 0-7695-1825-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
30 | Chien-Nan Jimmy Liu, I-Ling Chen, Jing-Yang Jou |
An efficient design-for-verification technique for HDLs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of ASP-DAC 2001, Asia and South Pacific Design Automation Conference 2001, January 30-February 2, 2001, Yokohama, Japan, pp. 103-108, 2001, ACM, 0-7803-6634-4. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
30 | Luciano Lavagno, Nanette Collins |
DAC 97 Panel: Next-Generation HDLs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 14(3), pp. 7-8, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP BibTeX RDF |
|
30 | Sanjiv Narayan, Daniel D. Gajski |
Features supporting system-level specification in HDLs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EURO-DAC ![In: Proceedings of the European Design Automation Conference 1993, EURO-DAC '93 with EURO-VHDL'93, Hamburg, Germany, September 20-24, 1993, pp. 540-545, 1993, IEEE Computer Society, 0-8186-4350-1. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
30 | Serge Maginot |
Evaluation criteria of HDLs: VHDL compared to Verilog, UDL/I & M. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EURO-DAC ![In: Proceedings of the conference on European design automation, EURO-DAC '92, Hamburg, Germany, September 7-10, 1992, pp. 746-751, 1992, IEEE Computer Society Press, 0-8186-2780-8. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
30 | J. R. Armstrong |
Chip-level modeling with HDLs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test ![In: IEEE Des. Test 5(1), pp. 8-18, 1988. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
|
30 | W. J. Chen, G. N. Reddy |
A computer aided design automation system for developing microprogrammed processors: a design approach through HDLs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 20st Annual Workshop and Symposium on Microprogramming and Microarchitecture, 1987, Colorado Springs, Colorado, USA, December 1-4, 1987, pp. 31-35, 1987, ACM/IEEE, 0-89791-250-0. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
|
28 | James Lapalme, El Mostapha Aboulhamid, Gabriela Nicolescu, Luc Charest, François R. Boyer, J. P. David, Guy Bois |
ESys.Net: a new solution for embedded systems modeling and simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES ![In: Proceedings of the 2004 ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'04), Washington, DC, USA, June 11-13, 2004, pp. 107-114, 2004, ACM, 1-58113-806-7. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
CIL, ESys.Net, attribute programming, component-based programming, simulation, Java, modeling, embedded systems, C++, framework, system on chip, VHDL, SystemC, hardware/software codesign, C#, Net, Verilog, HDLs, SystemVerilog |
28 | Sumit Ghosh |
In Search of the Origin of VHDL's Delta Delays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 3rd International Symposium on Quality of Electronic Design, ISQED 2002, San Jose, CA, USA, March 18-21, 2002, pp. 310-315, 2002, IEEE Computer Society, 0-7695-1561-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Delta delay, simulation accuracy, BCL, Conlan, continuous systems, simulation, timing, discrete event simulation, VHDL, hardware, hardware description language, HDLs |
28 | Salvador Mir, Benoît Charlot, Bernard Courtois |
Extending Fault-Based Testing to Microelectromechanical Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 16(3), pp. 279-288, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
nodal simulation, fault modeling, fault simulation, defects, MEMS, HDLs, failure modes |
28 | Salvador Mir, Benoît Charlot, Gabriela Nicolescu, Philippe Coste, Fabien Parrain, Nacer-Eddine Zergainoh, Bernard Courtois, Ahmed Amine Jerraya, Márta Rencz |
Towards design and validation of mixed-technology SOCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 10th ACM Great Lakes Symposium on VLSI 2000, Chicago, Illinois, USA, March 2-4, 2000, pp. 29-33, 2000, ACM, 1-58113-251-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
design, verification, MEMS, SOCs, architecture exploration, HDLs, cosimulation |
16 | Tai-Ying Jiang, Chien-Nan Jimmy Liu, Jing-Yang Jou |
Accurate Rank Ordering of Error Candidates for Efficient HDL Design Debugging. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(2), pp. 272-284, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
16 | Naoki Iwasaki, Katsumi Wasaki |
A Meta Hardware Description Language Melasy for Model-Checking Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITNG ![In: Fifth International Conference on Information Technology: New Generations (ITNG 2008), 7-8 April 2008, Las Vegas, Nevada, USA, pp. 273-278, 2008, IEEE Computer Society, 978-0-7695-3099-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Hardware/Software co-design and co-verification, Model Checking, Haskell, Design-for-test, Hardware Compilers |
16 | John Curreri, Seth Koehler, Brian Holland, Alan D. George |
Performance Analysis with High-Level Languages for High-Performance Reconfigurable Computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 16th IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2008, 14-15 April 2008, Stanford, Palo Alto, California, USA, pp. 23-30, 2008, IEEE Computer Society, 978-0-7695-3307-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
16 | Wolfgang Ecker, Volkan Esen, Lars Schönberg, Thomas Steininger, Michael Velten, Michael Hull |
Interactive presentation: Impact of description language, abstraction layer, and value representation on simulation performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2007 Design, Automation and Test in Europe Conference and Exposition, DATE 2007, Nice, France, April 16-20, 2007, pp. 767-772, 2007, EDA Consortium, San Jose, CA, USA, 978-3-9810801-2-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
16 | Oana Boncalo, Mihai Udrescu, Lucian Prodan, Mircea Vladutiu, Alexandru Amaricai |
Saboteur-Based Fault Injection for Quantum Circuits Fault Tolerance Assessment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: Tenth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2007), 29-31 August 2007, Lübeck, Germany, pp. 634-640, 2007, IEEE Computer Society, 0-7695-2978-X. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
16 | Oana Boncalo, Mihai Udrescu, Lucian Prodan, Mircea Vladutiu, Alexandru Amaricai |
Simulated Fault Injection for Quantum Circuits Based on Simulator Commands. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SACI ![In: 4th International Symposium on Applied Computational Intelligence and Informatics, SACI 2007, Timisoara, Romania, May 17-18, 2007, pp. 245-250, 2007, IEEE, 1-4244-1234-X. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
16 | Oana Boncalo, Mihai Udrescu, Lucian Prodan, Mircea Vladutiu, Alexandru Amaricai |
Using Simulated Fault Injection for Fault Tolerance Assessment of Quantum Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Annual Simulation Symposium ![In: Proceedings 40th Annual Simulation Symposium (ANSS-40 2007), 26-28 March 2007, Norfolk, Virginia, USA, pp. 213-220, 2007, IEEE Computer Society, 978-0-7695-2814-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
16 | Sara Bocchio, Elvinia Riccobene, Alberto Rosti, Patrizia Scandurra |
Process State Machines for Behavioral Modeling of Embedded Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIES ![In: IEEE Second International Symposium on Industrial Embedded Systems, SIES 2007, Hotel Costa da Caparica, Lisbon, Portugal, July 4-6, 2007, pp. 274-281, 2007, IEEE, 1-4244-0840-7. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
16 | Ould-cheikh Mourad, Si-Mohamed Lotfy, Noureddine Mehallegue, Ahmed Bouridane, Camel Tanougast |
AES Embedded Hardware Implementation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AHS ![In: Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007), August 5-8, 2007, University of Edinburgh, Scotland, United Kingdom, pp. 103-109, 2007, IEEE Computer Society, 0-7695-2866-X. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
16 | Gildas Genest, Richard Chamberlain, Robin J. Bruce |
Programming an FPGA-based Super Computer Using a C-to-VHDL Compiler: DIME-C. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AHS ![In: Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007), August 5-8, 2007, University of Edinburgh, Scotland, United Kingdom, pp. 280-286, 2007, IEEE Computer Society, 0-7695-2866-X. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
16 | Tim Schattkowsky, Jan Hendrik Hausmann, Gregor Engels |
Using UML Activities for System-on-Chip Design and Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MoDELS ![In: Model Driven Engineering Languages and Systems, 9th International Conference, MoDELS 2006, Genova, Italy, October 1-6, 2006, Proceedings, pp. 737-752, 2006, Springer, 3-540-45772-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
16 | Bruno Girodias, El Mostapha Aboulhamid, Gabriela Nicolescu |
A Platform for Refinement of OS Services for Embedded Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA 2006), 17-19 January 2006, Kuala Lumpur, Malaysia, pp. 227-236, 2006, IEEE Computer Society, 0-7695-2500-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
16 | Nirav Dave, Man Cheuk Ng, Arvind |
Automatic synthesis of cache-coherence protocol processors using Bluespec. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MEMOCODE ![In: 3rd ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2005), 11-14 July 2005, Verona, Italy, Proceedings, pp. 25-34, 2005, IEEE Computer Society, 0-7803-9227-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
16 | Zhi Guo, Betul Buyukkurt, Walid A. Najjar, Kees A. Vissers |
Optimized Generation of Data-Path from C Codes for FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2005 Design, Automation and Test in Europe Conference and Exposition (DATE 2005), 7-11 March 2005, Munich, Germany, pp. 112-117, 2005, IEEE Computer Society, 0-7695-2288-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
16 | Bernhard Peischl, Franz Wotawa |
Error traces in model-based debugging of hardware description languages. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AADEBUG ![In: Proceedings of the Sixth International Workshop on Automated Debugging, AADEBUG 2005, Monterey, California, USA, September 19-21, 2005, pp. 43-48, 2005, ACM, 1-59593-050-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
conditional dependency, error trace, potential influence, fault localization, automated debugging, software debugging, source-level debugging |
16 | Gabriel Popescu, Leonid B. Goldgeisser |
Modeling and simulation of mixed signal systems using a multi-lingual simulator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 5178-5181, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
16 | Kam S. Tso, Ann T. Tai, Savio N. Chau, Leon Alkalai |
On Automating Failure Mode Analysis and Enhancing its Integrity. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PRDC ![In: 11th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC 2005), 12-14 December, 2005, Changsha, Hunan, China, pp. 287-294, 2005, IEEE Computer Society, 0-7695-2492-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
16 | Erich Marschner, Victor Berman |
The continuing evolution of EDA standards. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 21(5), pp. 450-451, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
16 | Tom Fitzpatric |
System Verilog for VHDL Users. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France, pp. 1334-1341, 2004, IEEE Computer Society, 0-7695-2085-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
16 | He Hu 0001, Da-you Liu, Xiaoyong Du 0001 |
Semi-automatic hardware design using ontologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICARCV ![In: 8th International Conference on Control, Automation, Robotics and Vision, ICARCV 2004, Kunming, China, 6-9 December 2004, Proceedings, pp. 792-797, 2004, IEEE, 0-7803-8653-1. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
16 | Jan Borgosz |
Object Oriented Programming Paradigms for the VHDL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field Programmable Logic and Application, 14th International Conference , FPL 2004, Leuven, Belgium, August 30-September 1, 2004, Proceedings, pp. 1107-1109, 2004, Springer, 3-540-22989-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
16 | Rafael Castro-López, Francisco V. Fernández 0001, Fernando Medeiro, Ángel Rodríguez-Vázquez |
Behavioural Modelling and Simulation of SigmaDelta Modulators Using Hardware Description Languages. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2003 Design, Automation and Test in Europe Conference and Exposition (DATE 2003), 3-7 March 2003, Munich, Germany, pp. 10168-10175, 2003, IEEE Computer Society, 0-7695-1870-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
16 | Eric W. Johnson |
Extensive Introduction to VHDL and PLDs in the Sophomore Year. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MSE ![In: 2003 International Conference on Microelectronics Systems Education, MSE 2003, Educating Tomorrow's Microsystems Designers, Anaheim, CA, USA, June 1-2, 2003, pp. 23-24, 2003, IEEE Computer Society, 0-7695-1973-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
16 | Joanne DeGroat, Arun Raman, Bakr Younis |
A Design Project for System Design with SystemC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MSE ![In: 2003 International Conference on Microelectronics Systems Education, MSE 2003, Educating Tomorrow's Microsystems Designers, Anaheim, CA, USA, June 1-2, 2003, pp. 108-109, 2003, IEEE Computer Society, 0-7695-1973-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
16 | Leonid B. Goldgeisser |
Creating implicit homotopy methods using Hardware Description Languages. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (3) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 200-203, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
16 | Rafael Castro-López, Francisco V. Fernández 0001, Fernando Medeiro, Ángel Rodríguez-Vázquez |
Accurate VHDL-based simulation of Sigma-Delta modulators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 632-635, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
16 | Hamid R. Zarandi, Seyed Ghassem Miremadi, Ali Reza Ejlali |
Dependability Analysis Using a Fault Injection Tool Based on Synthesizability of HDL Models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 3-5 November 2003, Boston, MA, USA, Proceedings, pp. 485-492, 2003, IEEE Computer Society, 0-7695-2042-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
16 | Grant Martin |
UML for Embedded Systems Specification and Design: Motivation and Overview. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2002 Design, Automation and Test in Europe Conference and Exposition (DATE 2002), 4-8 March 2002, Paris, France, pp. 773-775, 2002, IEEE Computer Society, 0-7695-1471-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
16 | Qi Jing, Tamal Mukherjee, Gary K. Fedder |
Schematic-based lumped parameterized behavioral modeling for suspended MEMS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, ICCAD 2002, San Jose, California, USA, November 10-14, 2002, pp. 367-373, 2002, ACM / IEEE Computer Society, 0-7803-7607-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
electrostatic gap, nonlinear beam, schematic-based, behavioral, parameterized, MEMS, lumped |
16 | Richard Sharp |
Functional Design Using Behavioural and Structural Components. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FMCAD ![In: Formal Methods in Computer-Aided Design, 4th International Conference, FMCAD 2002, Portland, OR, USA, November 6-8, 2002, Proceedings, pp. 324-341, 2002, Springer, 3-540-00116-6. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
16 | Subir K. Roy, S. Ramesh, Supratik Chakraborty, Tsuneo Nakata, Sreeranga P. Rajan |
Functional Verification of System on Chips-Practices, Issues and Challenges (Tutorial Abstract). ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC/VLSI Design ![In: Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), and the 15th International Conference on VLSI Design (VLSI Design 2002), Bangalore, India, January 7-11, 2002, pp. 11-13, 2002, IEEE Computer Society, 0-7695-1299-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
16 | Robert Rinker, M. Carter, A. Patel, Monica Chawathe, Charlie Ross, Jeffrey Hammes, Walid A. Najjar, A. P. Wim Böhm |
An automated process for compiling dataflow graphs into reconfigurable hardware. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 9(1), pp. 130-139, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
16 | Stefan Höreth |
A word-level graph manipulation package. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Softw. Tools Technol. Transf. ![In: Int. J. Softw. Tools Technol. Transf. 3(2), pp. 182-192, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
Word-level, TUDD, BDD, Decision diagrams, BMD |
16 | Scott McMillan, Cameron Patterson |
JBitsTM Implementations of the Advanced Encryption Standard (Rijndael). ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, 11th International Conference, FPL 2001, Belfast, Northern Ireland, UK, August 27-29, 2001, Proceedings, pp. 162-171, 2001, Springer, 3-540-42499-7. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
16 | Richard Sharp, Alan Mycroft |
A Higher-Level Language for Hardware Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHARME ![In: Correct Hardware Design and Verification Methods, 11th IFIP WG 10.5 Advanced Research Working Conference, CHARME 2001, Livingston, Scotland, UK, September 4-7, 2001, Proceedings, pp. 228-243, 2001, Springer, 3-540-42541-1. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
16 | Jian Li 0061, Rajesh K. Gupta 0001 |
HDL presynthesis optimizations using a tabular model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 8(4), pp. 369-378, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
16 | Kanna Shimizu, David L. Dill, Alan J. Hu |
Monitor-Based Formal Specification of PCI. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FMCAD ![In: Formal Methods in Computer-Aided Design, Third International Conference, FMCAD 2000, Austin, Texas, USA, November 1-3, 2000, Proceedings, pp. 335-353, 2000, Springer, 3-540-41219-0. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
16 | Basant Rajan, R. K. Shyamasundar |
Modeling VHDL in Multiclock ESTEREL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 13th International Conference on VLSI Design (VLSI Design 2000), 4-7 January 2000, Calcutta, India, pp. 76-83, 2000, IEEE Computer Society, 0-7695-0487-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
16 | Stefan Höreth, Rolf Drechsler |
Formal Verification of Word-Level Specifications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1999 Design, Automation and Test in Europe (DATE '99), 9-12 March 1999, Munich, Germany, pp. 52-57, 1999, IEEE Computer Society / ACM, 0-7695-0078-1. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
16 | Ryuichi Takahashi, Noriyoshi Yoshida |
Diagonal Examples for Design Space Exploration in an Educational Environment CITY-1. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MSE ![In: IEEE International Conference on Microelectronic Systems Education, MSE 1999, Arlington, Virginia, USA, July 19-21, 1999, pp. 71-73, 1999, IEEE Computer Society, 0-7695-0312-8. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
16 | Nicholas McKay, Satnam Singh |
Debugging Techniques for Dynamically Reconfigurable Hardware. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 7th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '99), 21-23 April 1999, Napa, CA, USA, pp. 114-122, 1999, IEEE Computer Society, 0-7695-0375-6. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
16 | J. Fischer, C. Müller, H. Kurz |
A Co-simulation Concept for an Efficient Analysis of Complex Logic Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, From FPGAs to Computing Paradigm, 8th International Workshop, FPL'98, Tallinn, Estonia, August 31 - September 3, 1998, Proceedings, pp. 495-499, 1998, Springer, 3-540-64948-4. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
16 | Rajesh K. Gupta 0001, Stan Y. Liao |
Using a Programming Language for Digital System Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 14(2), pp. 72-80, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
16 | Kamran Zarrineh, Vivek Chickermane, Gareth Nicholls, Mike Palmer |
A Design For Test Perspective on I/O Management. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1996 International Conference on Computer Design (ICCD '96), VLSI in Computers and Processors, October 7-9, 1996, Austin, TX, USA, Proceedings, pp. 46-53, 1996, IEEE Computer Society, 0-8186-7554-3. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
I/O pads, High Level Synthesis, Design For Test, Boundary Scan |
16 | Ali Assi 0001, Bozena Kaminska |
Modeling of communication protocols in VHDL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 5th Great Lakes Symposium on VLSI (GLS-VLSI '95), March 16-18, 1995, The State University of New York at Buffalo, USA, pp. 168-171, 1995, IEEE Computer Society, 0-8186-7035-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
ISO/CCITT class O, VLSI, VLSI, high level synthesis, VHDL, transport protocols, transport protocol, communication protocols, hardware description languages, hardware implementations, high level design, ISO standards |
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