Search results for "HDLs"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
78	Shuqing Zhao, Daniel D. Gajski	Structural operational semantics for supporting multi-cycle operations in RTL HDLs.	MEMOCODE	2005	DBLP DOI BibTeX RDF
78	Yaohan Chu, Donald L. Dietmeyer, James R. Duley, Fredrick J. Hill, Mario Barbacci, Charles W. Rose, Greg M. Ordy, Bill Johnson, Martin Roberts	Three Decades of HDLs: Part I, CDL Through TI-HDL.	IEEE Des. Test Comput.	1992	DBLP DOI BibTeX RDF
78	Dominique Borrione, Robert Piloty, Dwight D. Hill, Karl J. Lieberherr, Philip Moorby	Three Decades of HDLs: Part II, Conlan Through Verilog.	IEEE Des. Test Comput.	1992	DBLP DOI BibTeX RDF
60	Rajesh K. Gupta 0001, Daniel Gajski, Randy Allen, Yatin Trivedi	Opportunities and pitfalls in HDL-based system design.	ICCD	1996	DBLP DOI BibTeX RDF	textual Hardware Description Languages, system designs, VHDL, modeling language, hardware description languages, Verilog, HDLs, hardware systems
48	Edmund M. Clarke, Masahiro Fujita, Sreeranga P. Rajan, Thomas W. Reps, Subash Shankar, Tim Teitelbaum	Program slicing for VHDL.	Int. J. Softw. Tools Technol. Transf.	2002	DBLP DOI BibTeX RDF	Model checking, Formal verification, VHDL, Program slicing, Hardware description languages
46	R. James Duckworth	Embedded System Design with FPGAs Using HDLs (Lessons Learned and Pitfalls to Be Avoided).	MSE	2005	DBLP DOI BibTeX RDF
46	Mihai Udrescu, Lucian Prodan, Mircea Vladutiu	Using HDLs for describing quantum circuits: a framework for efficient quantum algorithm simulation.	Conf. Computing Frontiers	2004	DBLP DOI BibTeX RDF	bubble logic, simulation, views, hardware description languages, quantum algorithms, quantum circuits, entanglement
32	Walid A. Najjar	Compiling code accelerators for FPGAs.	CASES	2007	DBLP DOI BibTeX RDF	FPGA code acceleration
32	Raymond Hoare, Shen Chih Tung	Combining Mentor Graphics? HDL Designer FPGA Flow with a Reconfigurable System on a Programmable Chip, Educational Opportunity or Insanity?	MSE	2003	DBLP DOI BibTeX RDF
32	Katsuyuki Ochiai, Hiroe Iwasaki, Jiro Naganuma, Makoto Endo, Takeshi Ogura	High-speed Software-based Platform for Embedded Software of a Single-chip MPEG-2 Video Encoder LSI with HDTV Scalabilit.	DATE	1999	DBLP DOI BibTeX RDF
32	Edmund M. Clarke, Masahiro Fujita, Sreeranga P. Rajan, Thomas W. Reps, Subash Shankar, Tim Teitelbaum	Program Slicing of Hardware Description Languages.	CHARME	1999	DBLP DOI BibTeX RDF
30	Sheng-Hong Wang, Hunter James Coffman, Kenneth Mayer, Sakshi Garg 0002, Jose Renau	A Multi-threaded Fast Hardware Compiler for HDLs.	CC	2023	DBLP DOI BibTeX RDF
30	Haven Blake Skinner, Rafael Trapani Possignolo, Sheng-Hong Wang, Jose Renau	LiveSim: A Fast Hot Reload Simulator for HDLs.	ISPASS	2020	DBLP DOI BibTeX RDF
30	Haven Blake Skinner, Rafael Trapani Possignolo, Jose Renau	Liam: an actor based programming model for HDLs.	MEMOCODE	2017	DBLP DOI BibTeX RDF
30	Robert Wille, Oliver Keszöcze, Lars Othmer, Michael Kirkedal Thomsen, Rolf Drechsler	Initial Ideas for Automatic Design and Verification of Control Logic in Reversible HDLs - Work in Progress Report.	RC	2016	DBLP DOI BibTeX RDF
30	Mohsen Ghasempour, Jonathan Heathcote, Javier Navaridas, Luis A. Plana, Jim D. Garside, Mikel Luján	Accelerating Interconnect Analysis Using High-Level HDLs and FPGA, SpiNNaker as a Case Study.	FCCM	2015	DBLP DOI BibTeX RDF
30	Gongyu Wang, Herman Lam, Alan D. George, Glen Edwards	Performance and productivity evaluation of hybrid-threading HLS versus HDLs.	HPEC	2015	DBLP DOI BibTeX RDF
30	Zainalabedin Navabi	HDLs evolve as they affect design methodology for a higher abstraction and a better integration.	DTIS	2015	DBLP DOI BibTeX RDF
30	Jung-Lin Yang, Jau-Cheng Wei, Shin-Nung Lu	HDLs Modeling Technique for Burst-Mode and Extended Burst-Mode Asynchronous Circuits.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2010	DBLP DOI BibTeX RDF
30	John A. Nestor	Teaching Computer Organization with HDLs: An Incremental Approach.	MSE	2005	DBLP DOI BibTeX RDF
30	Chun Hok Ho, Kuen Hung Tsoi, Jackson H. C. Yeung, Yuet Ming Lam, Kin-Hong Lee, Philip Heng Wai Leong, Ralf Ludewig, Peter Zipf, Alberto García Ortiz, Manfred Glesner	Arbitrary function approximation in HDLs with application to the N-body problem.	FPT	2003	DBLP DOI BibTeX RDF
30	Zvonko G. Vranesic, Stephen Dean Brown	Use of HDLs in teaching of computer hardware courses.	WCAE	2003	DBLP DOI BibTeX RDF
30	Tai-Ying Jiang, Chien-Nan Jimmy Liu, Jing-Yang Jou	Effective Error Diagnosis for RTL Designs in HDLs.	Asian Test Symposium	2002	DBLP DOI BibTeX RDF
30	Chien-Nan Jimmy Liu, I-Ling Chen, Jing-Yang Jou	An efficient design-for-verification technique for HDLs.	ASP-DAC	2001	DBLP DOI BibTeX RDF
30	Luciano Lavagno, Nanette Collins	DAC 97 Panel: Next-Generation HDLs.	IEEE Des. Test Comput.	1997	DBLP BibTeX RDF
30	Sanjiv Narayan, Daniel D. Gajski	Features supporting system-level specification in HDLs.	EURO-DAC	1993	DBLP DOI BibTeX RDF
30	Serge Maginot	Evaluation criteria of HDLs: VHDL compared to Verilog, UDL/I & M.	EURO-DAC	1992	DBLP DOI BibTeX RDF
30	J. R. Armstrong	Chip-level modeling with HDLs.	IEEE Des. Test	1988	DBLP DOI BibTeX RDF
30	W. J. Chen, G. N. Reddy	A computer aided design automation system for developing microprogrammed processors: a design approach through HDLs.	MICRO	1987	DBLP DOI BibTeX RDF
28	James Lapalme, El Mostapha Aboulhamid, Gabriela Nicolescu, Luc Charest, François R. Boyer, J. P. David, Guy Bois	ESys.Net: a new solution for embedded systems modeling and simulation.	LCTES	2004	DBLP DOI BibTeX RDF	CIL, ESys.Net, attribute programming, component-based programming, simulation, Java, modeling, embedded systems, C++, framework, system on chip, VHDL, SystemC, hardware/software codesign, C#, Net, Verilog, HDLs, SystemVerilog
28	Sumit Ghosh	In Search of the Origin of VHDL's Delta Delays.	ISQED	2002	DBLP DOI BibTeX RDF	Delta delay, simulation accuracy, BCL, Conlan, continuous systems, simulation, timing, discrete event simulation, VHDL, hardware, hardware description language, HDLs
28	Salvador Mir, Benoît Charlot, Bernard Courtois	Extending Fault-Based Testing to Microelectromechanical Systems.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	nodal simulation, fault modeling, fault simulation, defects, MEMS, HDLs, failure modes
28	Salvador Mir, Benoît Charlot, Gabriela Nicolescu, Philippe Coste, Fabien Parrain, Nacer-Eddine Zergainoh, Bernard Courtois, Ahmed Amine Jerraya, Márta Rencz	Towards design and validation of mixed-technology SOCs.	ACM Great Lakes Symposium on VLSI	2000	DBLP DOI BibTeX RDF	design, verification, MEMS, SOCs, architecture exploration, HDLs, cosimulation
16	Tai-Ying Jiang, Chien-Nan Jimmy Liu, Jing-Yang Jou	Accurate Rank Ordering of Error Candidates for Efficient HDL Design Debugging.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2009	DBLP DOI BibTeX RDF
16	Naoki Iwasaki, Katsumi Wasaki	A Meta Hardware Description Language Melasy for Model-Checking Systems.	ITNG	2008	DBLP DOI BibTeX RDF	Hardware/Software co-design and co-verification, Model Checking, Haskell, Design-for-test, Hardware Compilers
16	John Curreri, Seth Koehler, Brian Holland, Alan D. George	Performance Analysis with High-Level Languages for High-Performance Reconfigurable Computing.	FCCM	2008	DBLP DOI BibTeX RDF
16	Wolfgang Ecker, Volkan Esen, Lars Schönberg, Thomas Steininger, Michael Velten, Michael Hull	Interactive presentation: Impact of description language, abstraction layer, and value representation on simulation performance.	DATE	2007	DBLP DOI BibTeX RDF
16	Oana Boncalo, Mihai Udrescu, Lucian Prodan, Mircea Vladutiu, Alexandru Amaricai	Saboteur-Based Fault Injection for Quantum Circuits Fault Tolerance Assessment.	DSD	2007	DBLP DOI BibTeX RDF
16	Oana Boncalo, Mihai Udrescu, Lucian Prodan, Mircea Vladutiu, Alexandru Amaricai	Simulated Fault Injection for Quantum Circuits Based on Simulator Commands.	SACI	2007	DBLP DOI BibTeX RDF
16	Oana Boncalo, Mihai Udrescu, Lucian Prodan, Mircea Vladutiu, Alexandru Amaricai	Using Simulated Fault Injection for Fault Tolerance Assessment of Quantum Circuits.	Annual Simulation Symposium	2007	DBLP DOI BibTeX RDF
16	Sara Bocchio, Elvinia Riccobene, Alberto Rosti, Patrizia Scandurra	Process State Machines for Behavioral Modeling of Embedded Systems.	SIES	2007	DBLP DOI BibTeX RDF
16	Ould-cheikh Mourad, Si-Mohamed Lotfy, Noureddine Mehallegue, Ahmed Bouridane, Camel Tanougast	AES Embedded Hardware Implementation.	AHS	2007	DBLP DOI BibTeX RDF
16	Gildas Genest, Richard Chamberlain, Robin J. Bruce	Programming an FPGA-based Super Computer Using a C-to-VHDL Compiler: DIME-C.	AHS	2007	DBLP DOI BibTeX RDF
16	Tim Schattkowsky, Jan Hendrik Hausmann, Gregor Engels	Using UML Activities for System-on-Chip Design and Synthesis.	MoDELS	2006	DBLP DOI BibTeX RDF
16	Bruno Girodias, El Mostapha Aboulhamid, Gabriela Nicolescu	A Platform for Refinement of OS Services for Embedded Systems.	DELTA	2006	DBLP DOI BibTeX RDF
16	Nirav Dave, Man Cheuk Ng, Arvind	Automatic synthesis of cache-coherence protocol processors using Bluespec.	MEMOCODE	2005	DBLP DOI BibTeX RDF
16	Zhi Guo, Betul Buyukkurt, Walid A. Najjar, Kees A. Vissers	Optimized Generation of Data-Path from C Codes for FPGAs.	DATE	2005	DBLP DOI BibTeX RDF
16	Bernhard Peischl, Franz Wotawa	Error traces in model-based debugging of hardware description languages.	AADEBUG	2005	DBLP DOI BibTeX RDF	conditional dependency, error trace, potential influence, fault localization, automated debugging, software debugging, source-level debugging
16	Gabriel Popescu, Leonid B. Goldgeisser	Modeling and simulation of mixed signal systems using a multi-lingual simulator.	ISCAS (5)	2005	DBLP DOI BibTeX RDF
16	Kam S. Tso, Ann T. Tai, Savio N. Chau, Leon Alkalai	On Automating Failure Mode Analysis and Enhancing its Integrity.	PRDC	2005	DBLP DOI BibTeX RDF
16	Erich Marschner, Victor Berman	The continuing evolution of EDA standards.	IEEE Des. Test Comput.	2004	DBLP DOI BibTeX RDF
16	Tom Fitzpatric	System Verilog for VHDL Users.	DATE	2004	DBLP DOI BibTeX RDF
16	He Hu 0001, Da-you Liu, Xiaoyong Du 0001	Semi-automatic hardware design using ontologies.	ICARCV	2004	DBLP DOI BibTeX RDF
16	Jan Borgosz	Object Oriented Programming Paradigms for the VHDL.	FPL	2004	DBLP DOI BibTeX RDF
16	Rafael Castro-López, Francisco V. Fernández 0001, Fernando Medeiro, Ángel Rodríguez-Vázquez	Behavioural Modelling and Simulation of SigmaDelta Modulators Using Hardware Description Languages.	DATE	2003	DBLP DOI BibTeX RDF
16	Eric W. Johnson	Extensive Introduction to VHDL and PLDs in the Sophomore Year.	MSE	2003	DBLP DOI BibTeX RDF
16	Joanne DeGroat, Arun Raman, Bakr Younis	A Design Project for System Design with SystemC.	MSE	2003	DBLP DOI BibTeX RDF
16	Leonid B. Goldgeisser	Creating implicit homotopy methods using Hardware Description Languages.	ISCAS (3)	2003	DBLP DOI BibTeX RDF
16	Rafael Castro-López, Francisco V. Fernández 0001, Fernando Medeiro, Ángel Rodríguez-Vázquez	Accurate VHDL-based simulation of Sigma-Delta modulators.	ISCAS (4)	2003	DBLP DOI BibTeX RDF
16	Hamid R. Zarandi, Seyed Ghassem Miremadi, Ali Reza Ejlali	Dependability Analysis Using a Fault Injection Tool Based on Synthesizability of HDL Models.	DFT	2003	DBLP DOI BibTeX RDF
16	Grant Martin	UML for Embedded Systems Specification and Design: Motivation and Overview.	DATE	2002	DBLP DOI BibTeX RDF
16	Qi Jing, Tamal Mukherjee, Gary K. Fedder	Schematic-based lumped parameterized behavioral modeling for suspended MEMS.	ICCAD	2002	DBLP DOI BibTeX RDF	electrostatic gap, nonlinear beam, schematic-based, behavioral, parameterized, MEMS, lumped
16	Richard Sharp	Functional Design Using Behavioural and Structural Components.	FMCAD	2002	DBLP DOI BibTeX RDF
16	Subir K. Roy, S. Ramesh, Supratik Chakraborty, Tsuneo Nakata, Sreeranga P. Rajan	Functional Verification of System on Chips-Practices, Issues and Challenges (Tutorial Abstract).	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF
16	Robert Rinker, M. Carter, A. Patel, Monica Chawathe, Charlie Ross, Jeffrey Hammes, Walid A. Najjar, A. P. Wim Böhm	An automated process for compiling dataflow graphs into reconfigurable hardware.	IEEE Trans. Very Large Scale Integr. Syst.	2001	DBLP DOI BibTeX RDF
16	Stefan Höreth	A word-level graph manipulation package.	Int. J. Softw. Tools Technol. Transf.	2001	DBLP DOI BibTeX RDF	Word-level, TUDD, BDD, Decision diagrams, BMD
16	Scott McMillan, Cameron Patterson	JBitsTM Implementations of the Advanced Encryption Standard (Rijndael).	FPL	2001	DBLP DOI BibTeX RDF
16	Richard Sharp, Alan Mycroft	A Higher-Level Language for Hardware Synthesis.	CHARME	2001	DBLP DOI BibTeX RDF
16	Jian Li 0061, Rajesh K. Gupta 0001	HDL presynthesis optimizations using a tabular model.	IEEE Trans. Very Large Scale Integr. Syst.	2000	DBLP DOI BibTeX RDF
16	Kanna Shimizu, David L. Dill, Alan J. Hu	Monitor-Based Formal Specification of PCI.	FMCAD	2000	DBLP DOI BibTeX RDF
16	Basant Rajan, R. K. Shyamasundar	Modeling VHDL in Multiclock ESTEREL.	VLSI Design	2000	DBLP DOI BibTeX RDF
16	Stefan Höreth, Rolf Drechsler	Formal Verification of Word-Level Specifications.	DATE	1999	DBLP DOI BibTeX RDF
16	Ryuichi Takahashi, Noriyoshi Yoshida	Diagonal Examples for Design Space Exploration in an Educational Environment CITY-1.	MSE	1999	DBLP DOI BibTeX RDF
16	Nicholas McKay, Satnam Singh	Debugging Techniques for Dynamically Reconfigurable Hardware.	FCCM	1999	DBLP DOI BibTeX RDF
16	J. Fischer, C. Müller, H. Kurz	A Co-simulation Concept for an Efficient Analysis of Complex Logic Designs.	FPL	1998	DBLP DOI BibTeX RDF
16	Rajesh K. Gupta 0001, Stan Y. Liao	Using a Programming Language for Digital System Design.	IEEE Des. Test Comput.	1997	DBLP DOI BibTeX RDF
16	Kamran Zarrineh, Vivek Chickermane, Gareth Nicholls, Mike Palmer	A Design For Test Perspective on I/O Management.	ICCD	1996	DBLP DOI BibTeX RDF	I/O pads, High Level Synthesis, Design For Test, Boundary Scan
16	Ali Assi 0001, Bozena Kaminska	Modeling of communication protocols in VHDL.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	ISO/CCITT class O, VLSI, VLSI, high level synthesis, VHDL, transport protocols, transport protocol, communication protocols, hardware description languages, hardware implementations, high level design, ISO standards