Search results for "HDTV"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
101	Joonbok Lee, Kilnam Chon	Compressed High Definition Television (HDTV) over IPv6.	SAINT Workshops	2006	DBLP DOI BibTeX RDF
93	Nam Ling, Nien-Tsu Wang	A Real-Time Video Decoder for Digital HDTV.	J. VLSI Signal Process.	2003	DBLP DOI BibTeX RDF	HDTV video decoder, MPEG-2 MP@HL decoder, digital TV, HDTV, video decoding
93	Ti-Hao Chiang, Huifang Sun, Joel W. Zdepski	Spatial scalable HDTV coding.	ICIP	1995	DBLP DOI BibTeX RDF	spatial scalable HDTV coding, two-layer digital HDTV service, enhancement layer, base layer, top layer video signal, upsampling, bit stream scaling, compression, data compression, efficiency, video coding, bandwidth, image resolution, image sampling, digital television, quality requirement, picture quality, spatial resolution, high definition television
89	Tetsuro Kuge	Development of JPEG2000 HDTV Program Production System.	ICIP	2006	DBLP DOI BibTeX RDF
85	Eva Baaren, Lidwien van de Wijngaert, Erik Huizer	'I Want My HDTV'? Underlying Factors of Perceived Usefulness for High Definition Television.	EuroITV	2008	DBLP DOI BibTeX RDF	Adoption, Diffusion of Innovations, HDTV, Perceived Usefulness
73	Eva Baaren, Lidwien van de Wijngaert, Erik Huizer	"Who's Afraid of High Def?" Institutional Factors Influencing HDTV Diffusion in the Netherlands.	ICDS	2008	DBLP DOI BibTeX RDF	Innovation, Technology, New Media, HDTV, Diffusion theory
68	Dirkjan Joor, Wilco Beekhuizen, Lidwien van de Wijngaert, Pascal Ijegalu	What You Expect Is What You See.	EuroITV	2008	DBLP DOI BibTeX RDF	value-expectancy theory, Framing, Diffusion of innovation, HDTV
61	Frederik Vanhaverbeke, Marc Moeneclaey, Koenraad Laevens, Natalie Degrande, Danny De Vleeschauwer	Comparison of Two Forward Error Correction Approaches for Packet Protection in HDTV with Variable Bit Rate Transmission.	ICN	2008	DBLP DOI BibTeX RDF	FEC, variable bit rate, HDTV
61	Yuhuang Ye, Yuanjiu Li, Kaixiong Su	Architecture and Software Implementation of HDTV Video Decoder on a Singlechip, MPEG Decoder.	CGIV	2006	DBLP DOI BibTeX RDF	MPEG-2, HDTV, set top box, video decoder
61	Jiun-In Guo, Jui-Cheng Yen	An Efficient IDCT Processor Design for HDTV Applications.	J. VLSI Signal Process.	2003	DBLP DOI BibTeX RDF	inverse discrete cosine transform (IDCT), adder-based implementation, common sub-expression sharing, HDTV, cyclic convolution
61	Jae-Tack Yoo, Ganesh Gopalakrishnan, Kent F. Smith, V. John Mathews	High speed counterflow-clocked pipelining illustrated on the design of HDTV subband vector quantizer chips.	ARVLSI	1995	DBLP DOI BibTeX RDF	counterflow-clocked pipelining, HDTV subband vector quantizer chips, clock skew problems, back-propagating clock signals, high speed clocks, dynamic latches, composition rules, two-dimensional data-flow, image compression chip set, subband VQ, VLSI, timing, image coding, pipeline processing, digital signal processing chips, vector quantisation, telecommunication computing, clock distribution, VLSI chips, high definition television
53	Vagner S. Rosa, Altamiro Amadeu Susin, Sergio Bampi	An HDTV H.264 deblocking filter in FPGA with RGB video output.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
53	Jun Xin, Ming-Ting Sun, Kang Wook Chun, Byung Sun Choi	Motion re-estimation for HDTV to SDTV transcoding.	ISCAS (4)	2002	DBLP DOI BibTeX RDF
53	Dongxiao Li, Qingdong Yao, Peng Liu 0016, Li Zhou	A bus arbitration scheme for HDTV decoder SoC.	APCCAS (2)	2002	DBLP DOI BibTeX RDF
49	Gustavo Girão, Sílvio R. F. de Araújo, Monica Magalhães Pereira, Ivan Saraiva Silva	Implementation of a HDTV transport stream multiplexer based on ITU-T H.222.0 recommendation.	WebMedia	2006	DBLP DOI BibTeX RDF	TS multiplexer, transport layer, FPGA implementation, digital television, HDTV
49	Chitra Dorai, Vikrant Kobla	Extracting Motion Annotations from MPEG-2 Compressed Video for HDTV Content Management Applications.	ICMCS, Vol. 1	1999	DBLP DOI BibTeX RDF	SDTV, perceived visual motion, global motion annotation, flow representation, MPEG-2, video content analysis, Digital television, HDTV, content-based indexing and retrieval
49	JongMoo Sohn, JongIck Lee, MoonKey Lee, InHwa Hong, ByungRyul Lee	Jitter Reduction in CBR HDTV Transport Stream Packet Communications over Lossy ATM Network.	ICCCN	1998	DBLP DOI BibTeX RDF	CBR HDTV, De-jitter, lossy ATM Network, Sequence Numbering
49	Anthony Vetro, Huifang Sun, Jay Bao, Tommy Poon	Frequency Domain Down Conversion of HDTV Using Adaptive Motion Compensation.	ICIP (1)	1997	DBLP DOI BibTeX RDF	adaptive motion compensation, NTSC monitor, frequency domain down-conversion, HDTV signal, frequency synthesis algorithm, down-conversion decoder, adaptive motion compensation algorithm, complexity, image sequences, image quality, digital TV, DCT coefficients, high definition television
48	Dragomir Milojevic, Luc J. M. Montperrus, Diederik Verkest	Power Dissipation of the Network-on-Chip in Multi-Processor System-on-Chip Dedicated for Video Coding Applications.	J. Signal Process. Syst.	2009	DBLP DOI BibTeX RDF	Multi-processor systems-on-chip (MPSoC), Real-time video encoding, AVC/H.264, Low-power VLSI implementation, decoding, Networks-on-chip (NoC)
48	Frank Marlowe	High Definition Television Broadcast Technology -A Nist/atp Project.	Workshop on Digital and Computational Video	2001	DBLP DOI BibTeX RDF
41	Marcelo Schiavon Porto, Sergio Bampi, Altamiro Amadeu Susin, Luciano Volcan Agostini	Architectural design for the new QSDS with dynamic iteration control motion estimation algorithm targeting HDTV.	SBCCI	2008	DBLP DOI BibTeX RDF	motion estimation, architectural design, fast algorithm
41	Hiroe Iwasaki, Jiro Naganuma, Koyo Nitta, Ken Nakamura, Takeshi Yoshitome, Mitsuo Ogura, Yasuyuki Nakajima, Yutaka Tashiro, Takayuki Onishi, Mitsuo Ikeda, Toshihiro Minami, Makoto Endo, Yoshiyuki Yashima	Single-Chip MPEG-2 422P@HL CODEC LSI With Multichip Configuration for Large Scale Processing Beyond HDTV Level.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
41	Junhao Zheng, Lei Deng, Peng Zhang, Don Xie	An Efficient VLSI Architecture for Motion Compensation of AVS HDTV Decoder.	J. Comput. Sci. Technol.	2006	DBLP DOI BibTeX RDF	motion compensation, VLSI architecture, AVS
41	Arnaldo Azevedo, Bruno Zatt, Luciano Volcan Agostini, Sergio Bampi	Motion Compensation Decoder Architecture for H.264/AVC Main Profile Targeting HDTV.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
41	Luciano Volcan Agostini, Arnaldo Azevedo, Vagner S. Rosa, Eduardo A. Berriel, Tatiana Gadelha Serra dos Santos, Sergio Bampi, Altamiro Amadeu Susin	FPGA Design of A H.264/AVC Main Profile Decoder for HDTV.	FPL	2006	DBLP DOI BibTeX RDF
41	Han Chen, Kai Li 0001, Bin Wei	Memory Performance Optimizations For Real-Time Software HDTV Decoding.	J. VLSI Signal Process.	2005	DBLP DOI BibTeX RDF	CPI, concurrency, cache, locality, prefetching, motion compensation, MPEG-2, decompression
41	Kazuhiro Kamimura, Teruyuki Hasegawa, Haruo Hoshino, Shigehiro Ano, Toru Hasegawa	A Practical Multicast Transmission Control Method for Multi-channel HDTV IP Broadcasting System.	PCM (2)	2005	DBLP DOI BibTeX RDF
41	Hiroe Iwasaki, Jiro Naganuma, Koyo Nitta, Ken Nakamura, Takeshi Yoshitome, Mitsuo Ogura, Yasuyuki Nakajima, Yutaka Tashiro, Takayuki Onishi, Mitsuo Ikeda, Makoto Endo	Single-Chip MPEG-2 422P@HL CODEC LSI with Multi-Chip Configuration for Large Scale Processing beyond HDTV Level.	DATE	2003	DBLP DOI BibTeX RDF
41	Jae Hong Park, Jung-Min Choi, Min Ho Kim, Jong-Wha Chong	An Efficient Equalizer Architecture Using Tap Allocation Memory for HDTV Channel.	IWSOC	2003	DBLP DOI BibTeX RDF
41	Kosuke Yoshioka, Hiroyuki Oka, Hideshi Nishida, Ryuji Matsuura, Tokuzo Kiyohara	An architectural extension to the media core processor for HDTV applications.	APCCAS (1)	2002	DBLP DOI BibTeX RDF
41	L. Zhou, Q. D. Yao, P. Liu, D. X. Li	Influence of buffers on RISC core performance [HDTV source decoder system].	APCCAS (2)	2002	DBLP DOI BibTeX RDF
41	Takashi Miyazaki, Takao Nishitani, Masato Edahiro, Ikuko Ono, Kaoru Mitsuhashi	DCT/IDCT processor for HDTV developed with dsp silicon compiler.	J. VLSI Signal Process.	1993	DBLP DOI BibTeX RDF
37	Gwanggil Jeon, Jungjun Kim, Jongmin You, Jechang Jeong	Fuzzy Rule Based Edge-Sensitive Line Average Algorithm in Interlaced HDTV Sequences.	IbPRIA (2)	2007	DBLP DOI BibTeX RDF	Deinterlacing, edge-sensitive interpolation, fuzzy technique, HDTV
36	Shinichi Sakaida, Kazuhisa Iguchi, Nao Nakajima, Yukihiro Nishida, Atsuro Ichigaya, Eisuke Nakasu, Masaaki Kurozumi, Seiichi Gohshi	The Super Hi-Vision Codec.	ICIP (1)	2007	DBLP DOI BibTeX RDF
36	Stéphane Péchard, Mathieu Carnec, Patrick Le Callet, Dominique Barba	From SD to HD Television: Effects of H.264 Distortions Versus Display Size on Quality of Experience.	ICIP	2006	DBLP DOI BibTeX RDF
36	Thomas A. DeFanti	Extreme Multimedia.	ISM	2005	DBLP DOI BibTeX RDF
35	Jesús Macías, Pablo Pérez 0001, Jaime J. Ruiz	Optimal Size of an HDTV Set During the Transition Period From SDTV to HDTV.	Bell Labs Tech. J.	2013	DBLP DOI BibTeX RDF
35	Nagato Narita, Masaru Kanazawa	Analysis of Psychological Factors for HDTV/3-D HDTV and Evaluation Method of Their Overall Impressions.	IEEE Trans. Broadcast.	2013	DBLP DOI BibTeX RDF
35	Nils Walravens, Caroline Pauwels	From high hopes to high deficit and back: A historic overview of Europe's HDTV policy and reflections towards the future of HDTV.	Telematics Informatics	2011	DBLP DOI BibTeX RDF
35	Joshan Meenowa, David S. Hands, Rhea Young, Damien Bayart	Subjective assessment of HDTV content: comparison of quality across HDTV formats.	Human Vision and Electronic Imaging	2010	DBLP DOI BibTeX RDF
35	Nils Walravens, Caroline Pauwels	From high hopes to high deficit and back: a historic overview of Europe's hdtv policy and reflections towards the future of HDTV.	EuroITV	2009	DBLP DOI BibTeX RDF
35	Kai Öistämö	Signal processing of HDTV, II, Proceedings of the Third International Workshop on HDTV, Turin, Italy, 30 August-1 September 1989 : by Leonardo CHIARLIGLIONE (editor), CSELT, Italy. Publishers: Elsevier Science Publishers, Sara Burgerhartsstraat 25, P.O. Box 211, 1000 AE Amsterdam, Netherlands, 1990, xx+899 pp., ISBN 0-444-88833-0.	Signal Process.	1991	DBLP DOI BibTeX RDF
32	Xiaotong Zhang, Lei Zhang, Jian Zhou	A High Performance Strategy for Constructing Dynamic MIB.	ITNG	2008	DBLP DOI BibTeX RDF	SNMP, HDTV, AVL tree, MIB
32	Wonyong Sung, Youngho Ahn, Eunjoo Hwang	VLSI Implementation of An Adaptive Equalizer for ATSC Digital TV Receivers.	J. VLSI Signal Process.	2005	DBLP DOI BibTeX RDF	adaptive equalizer, HDTV receiver, VSB modulation, VLSI implementation
32	Santanu Dutta, Deepak Singh, Essam Abu-Ghoush, Vijay Mehra	Architecture and Implementation of a High-Definition Video Co-Processor for Digital Television Applications.	VLSI Design	2000	DBLP DOI BibTeX RDF	ATSC standard, picture processing, VLSI design, video processing, Digital television, HDTV, media processor
32	Osama K. Alshaykh, Homer H. Chen	Minimum-drift digital video down-conversion.	ACM Multimedia (1)	1999	DBLP DOI BibTeX RDF	SDTV, MPEG-2, HDTV, format conversion
32	Chok-Kwan Cheung, Lai-Man Po	A hierarchical block motion estimation algorithm using partial distortion measure.	ICIP (3)	1997	DBLP DOI BibTeX RDF	hierarchical block motion estimation algorithm, partial distortion measure, hierarchical block matching algorithms, MSE performance, three-step search, high motion estimation accuracy, real-time video conferencing applications, encoding speed, motion estimation, MPEG-2, parameter selections, HDTV
32	Kei Karasawa, Makoto Iwata, Hiroaki Terada	Direct Generation of Data-Driven Program for Stream-Oriented Processing.	IEEE PACT	1997	DBLP DOI BibTeX RDF	Parallel processing system specifications, Multiple data streams, Direct program generation, Data-driven paradigm, HDTV signal decoder
32	Vasily G. Moshnyaga, Keikichi Tamaru	A Memory Efficient Array Architecture for Real-Time Motion Estimation.	IPPS	1997	DBLP DOI BibTeX RDF	array architecture, real-time motion estimation, video picture, video memory distribution, HDTV picture format, motion estimation, video-coding, VLSI implementation, memory requirements
32	Luc Vandendorpe, Paul Delogne, David Boucquey	Generalized interpolators for advanced movement-compensated 50 Hz-60 Hz conversion of interlaced sequences.	ICIP	1995	DBLP DOI BibTeX RDF	frequency convertors, generalized interpolators, movement-compensated conversion, interlaced sequences, TV signals, HDTV signals, static interpolation filter, bandlimited television signals, movement-oriented filtering, interlaced TV standards, nonuniform sampling theory, target field segmentation, 60 Hz, 50 Hz, image segmentation, motion estimation, interpolation, interpolation, motion compensation, motion compensation, transcoders, video signal processing, telecommunication standards, image sampling, television standards, television standards, motion estimation algorithm, high definition television
32	Hayit Greenspan, Sofia Akber	Nonlinear edge enhancement.	ICIP	1995	DBLP DOI BibTeX RDF	nonlinear edge enhancement, nonlinear image enhancement, parameter sensitivity, global scheme, adaptive local parametrization, enhancement algorithm, frequency spectrum, blurred input, high-spatial frequencies, edge detection, parameter estimation, parameter estimation, bandwidth, image enhancement, nonlinear filters, nonlinear filtering, image resolution, image resolution, filtering theory, adaptive signal processing, image sampling, HDTV, videotelephony, videophone, sampling rate, high definition television
29	Thaísa Leal da Silva, Fábio I. Pereira, Altamiro Amadeu Susin, Sergio Bampi, Luciano Volcan Agostini	High performance and low cost architecture for H.264/AVC CAVLD targeting HDTV.	SBCCI	2009	DBLP DOI BibTeX RDF	CAVLD, H.264/AVC, video compression, hardware architectures
29	He Wang, Guowei Teng, Zhangyao Zhang, Guozhong Wang	A low cost hardware oriented motion estimation algorithm for HDTV.	GEC Summit	2009	DBLP DOI BibTeX RDF	RDO, hardware oriented algorithm, motion estimation, low cost
29	Yiqing Huang 0002, Qin Liu 0002, Satoshi Goto, Takeshi Ikenaga	Reconfigurable SAD tree architecture based on adaptive sub-sampling in HDTV application.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	reconfigurable architecture, h.264, vlsi
29	Roger F. Woods, John V. McCanny, John G. McWhirter	From Bit Level Systolic Arrays to HDTV Processor Chips.	J. Signal Process. Syst.	2008	DBLP DOI BibTeX RDF	SoC architectures, DSP systems, pipelining, systolic arrays
29	Yu Li, Yun He	Bandwidth Optimized and High Performance Interpolation Architecture in Motion Compensation for H.264/AVC HDTV Decoder.	J. Signal Process. Syst.	2008	DBLP DOI BibTeX RDF	video coding, H.264/AVC, motion compensation, VLSI design
29	Bruno Zatt, Altamiro Amadeu Susin, Sergio Bampi, Luciano Volcan Agostini	High throughput architecture for H.264/AVC motion compensation sample interpolator for HDTV.	SBCCI	2008	DBLP DOI BibTeX RDF	video coding, H.264/AVC, motion compensation, hardware architectures
29	Bruno Zatt, Altamiro Amadeu Susin, Sergio Bampi, Luciano Volcan Agostini	HP422-MoCHA: A H.264/AVC High Profile motion compensation architecture for HDTV.	ISCAS	2008	DBLP DOI BibTeX RDF
29	Jintao Wang, Rui Lv, Pengdong Gao, Yongquan Lu, Chu Qiu, Wenhua Yu	The Design of HDTV H.264 Encoding System Based on Multi-DSPs Architecture.	CSSE (4)	2008	DBLP DOI BibTeX RDF
29	A. A. S. Sluyterman, Wilhelmus H. A. Brüls	Utilizing HDTV Displays to its Full Potential and its Impact on Video Compression.	ICIP (1)	2007	DBLP DOI BibTeX RDF
29	Avishek Saha, Santosh Ghosh	A Speed-Area Optimization of Full Search Block Matching Hardware with Applications in High-Definition TVs (HDTV).	HiPC	2007	DBLP DOI BibTeX RDF
29	Kentaro Kawakami, Mitsuhiko Kuroda, Hiroshi Kawaguchi 0001, Masahiko Yoshimoto	Power and Memory Bandwidth Reduction of an H.264/AVC HDTV Decoder LSI with Elastic Pipeline Architecture.	ASP-DAC	2007	DBLP DOI BibTeX RDF
29	Hongqi Hu, Jiadong Xu, Zhemin Duan, Jingnan Sun	High Efficiency Synchronous DRAM Controller for H.264 HDTV Encoder.	SiPS	2007	DBLP DOI BibTeX RDF
29	Tsun-Hsien Wang, Ching-Te Chiu	Low Power Design of High Performance Memory Access Architecture for HDTV Decoder.	ICME	2007	DBLP DOI BibTeX RDF
29	Arnaldo Azevedo, Bruno Zatt, Luciano Volcan Agostini, Sergio Bampi	MoCHA: a Bi-Predictive Motion Compensation Hardware for H.264/AVC Decoder Targeting HDTV.	ISCAS	2007	DBLP DOI BibTeX RDF
29	Yu Li, Yanmei Qu, Yun He	Memory Cache Based Motion Compensation Architecture for HDTV H.264/AVC Decoder.	ISCAS	2007	DBLP DOI BibTeX RDF
29	Wagston T. Staehler, Eduardo A. Berriel, Altamiro Amadeu Susin, Sergio Bampi	Architecture of an HDTV Intraframe Predictor for a H.264 Decoder.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
29	Peng Zhang 0018, Wen Gao 0001, Di Wu 0022, Don Xie	An Efficient Reference Frame Storage Scheme for H.264 HDTV Decoder.	ICME	2006	DBLP DOI BibTeX RDF
29	Changqi Yang, Satoshi Goto, Takeshi Ikenaga	High performance VLSI architecture of fractional motion estimation in H.264 for HDTV.	ISCAS	2006	DBLP DOI BibTeX RDF
29	Junhao Zheng, Di Wu 0022, Lei Deng 0007, Don Xie, Wen Gao 0001	A Motion Vector Predictor Architecture for AVS and MPEG-2 HDTV Decoder.	PCM	2006	DBLP DOI BibTeX RDF	Motion vector prediction, MPEG, Motion compensation, VLSI architecture, AVS
29	Jiang Xu 0001, Wayne H. Wolf, Jörg Henkel, Srimat T. Chakradhar	H.264 HDTV Decoder Using Application-Specific Networks-On-Chip.	ICME	2005	DBLP DOI BibTeX RDF
29	Bin Yu 0010, Klara Nahrstedt	Internet-based interactive HDTV.	Multim. Syst.	2004	DBLP DOI BibTeX RDF
29	Peter Bellows, Jaroslav Flidr, Ladan Gharai, Colin Perkins, Pawel Chodowiec, Kris Gaj	IPsec-Protected Transport of HDTV over IP.	FPL	2003	DBLP DOI BibTeX RDF
29	Santanu Dutta	Architecture and design of NX-2700: a programmable single-chip HDTV all-format-decode-and-display processor.	IEEE Trans. Very Large Scale Integr. Syst.	2001	DBLP DOI BibTeX RDF
29	Ken Nakamura, Mitsuo Ikeda, Takeshi Yoshitome, Takeshi Ogura	Global Rate Control Scheme for MPEG-2 HDTV Parallel Encoding System.	ITCC	2000	DBLP DOI BibTeX RDF
29	Katsuyuki Ochiai, Hiroe Iwasaki, Jiro Naganuma, Makoto Endo, Takeshi Ogura	High-speed Software-based Platform for Embedded Software of a Single-chip MPEG-2 Video Encoder LSI with HDTV Scalabilit.	DATE	1999	DBLP DOI BibTeX RDF
29	Nien-Tsu Wang, Nam Ling	A Novel Dual-Path Architecture for HDTV Video Decoding.	Data Compression Conference	1999	DBLP DOI BibTeX RDF
29	Hangu Yeo, Yu Hen Hu	A Modular Architecture for Real Time HDTV Motion Estimation with Large Search Range.	Great Lakes Symposium on VLSI	1996	DBLP DOI BibTeX RDF
29	Christian von Reventlow, Maati Talmi, Stefan Wolf, M. Ernst, K. Müller, C. Stoffers	System considerations and the system level design of a chip set for real-time TV and HDTV motion estimation.	J. VLSI Signal Process.	1993	DBLP DOI BibTeX RDF
29	John W. Woods, Thumpudi Naveen	A filter based bit allocation scheme for subband compression of HDTV.	IEEE Trans. Image Process.	1992	DBLP DOI BibTeX RDF
24	André Silva, Eduardo A. C. da Costa, Sérgio J. M. de Almeida, Marcelo Schiavon Porto, Sergio Bampi	High performance motion estimation architecture using efficient adder-compressors.	SBCCI	2009	DBLP DOI BibTeX RDF	adder-compressor, motion estimation, fast algorithm
24	Yizhen Zhang, Chao Xu 0006, Wentao Wang, Liang-Bin Chen	Performance Analysis and Architecture Design for Parallel EBCOT Encoder of JPEG2000.	IEEE Trans. Circuits Syst. Video Technol.	2007	DBLP DOI BibTeX RDF
24	Vagner S. Rosa, Wagston T. Staehler, Arnaldo Azevedo, Bruno Zatt, Roger Endrigo Carvalho Porto, Luciano Volcan Agostini, Sergio Bampi, Altamiro Amadeu Susin	FPGA Prototyping Strategy for a H.264/AVC Video Decoder.	IEEE International Workshop on Rapid System Prototyping	2007	DBLP DOI BibTeX RDF
24	Xianghui Wei, Shen Li, Yang Song 0002, Satoshi Goto	An Irregular Search Window Reuse Scheme for Motion Estimation in MPEG-2 to H.264 Transcoding.	ISCAS	2007	DBLP DOI BibTeX RDF
24	Jiang Xu 0001, Wayne H. Wolf, Jörg Henkel, Srimat T. Chakradhar	A design methodology for application-specific networks-on-chip.	ACM Trans. Embed. Comput. Syst.	2006	DBLP DOI BibTeX RDF	regular topology, architecture, methodology, networks-on-chip, Application-specific
24	Chao-Chung Cheng, Chun-Wei Ku, Tian-Sheuan Chang	A 1280×720 pixels 30 frames/s H.264/MPEG-4 AVC intra encoder.	ISCAS	2006	DBLP DOI BibTeX RDF
24	Hiroyuki Kimiyama, Kenji Shimizu, Tetsuo Kawano, Tsuyoshi Ogura, Mitsuru Maruyama	Real-time Processing Method for an Ultra High-Speed Streaming Server Running PC Linux.	AINA (2)	2004	DBLP DOI BibTeX RDF
24	Lei Deng 0007, Wen Gao 0001, Ming-Zeng Hu, Zhenzhou Ji	An Efficient VLSI Implementation for MC Interpolation of AVS Standard.	PCM (3)	2004	DBLP DOI BibTeX RDF
24	Akihiko Shirai, Kiichi Kobayashi, Masahiro Kawakita, Shoichi Hasegawa, Masayuki Nakajima 0001, Makoto Sato	Entertainment Applications of Human-Scale Virtual Reality Systems.	PCM (3)	2004	DBLP DOI BibTeX RDF
24	Kambiz Ghahremani, Cyrus Shahabi, Shu-Yuen Didi Yao, Roger Zimmermann	Yima: real-time multimedia storage and retrieval.	ACM Multimedia	2002	DBLP DOI BibTeX RDF	multimedia storage, scalable, MPEG-4, video server, continuous media
20	Andrey Belogolovy, Eugine Belyaev, Anton Sergeev, Andrey M. Turlikov	Video Compression for Wireless Transmission: Reducing the Power Consumption of the WPAN Hi-Speed Systems.	NEW2AN	2009	DBLP DOI BibTeX RDF	wireless video transmission, NGmS, 802.15.3c, wireless display, compression, power saving, WPAN, HDTV
20	Christian P. Brackmann, Cauane Blumenberg Silva, Paulo Roberto Gomes Luzzardi	TVMark: benchmarking para TV digital.	IHC	2008	DBLP BibTeX RDF	HDTV e TV interativa, JavaTV, TV digital, TVMark, embedded systems, benchmarking, SBTVD, interactive digital TV
20	Michael R. Macedonia	The Future Arrives ... Finally.	Computer	2007	DBLP DOI BibTeX RDF	Consumer Electronics Show, entertainment computing, Digital TV, HDTV
20	Theo Mayer	The 4K format implications for visualization, VR, command & control and special venue application.	EDT	2007	DBLP DOI BibTeX RDF	1080, 2K, 4K, SXGA, SXRD, XGA, blended arrays, cube walls, edge blend, monitor arrays, projected arrays, special venue, video resolution, visualization, VR, video, command and control, HDTV
20	Michael R. Macedonia	Moving Beyond HD.	Computer	2006	DBLP DOI BibTeX RDF	entertainment computing, HDTV
20		Tools and Products.	IEEE Computer Graphics and Applications	2005	DBLP DOI BibTeX RDF	front-projection screen, high-resolution grahpics, 2D storyboarding, 3D character animation, 3D models, HDTV
20	Kuan-Hung Chen, Kuo-Chuan Chao, Jinn-Shyan Wang, Yuan-Sun Chu, Jiun-In Guo	An efficient spurious power suppression technique (SPST) and its applications on MPEG-4 AVC/H.264 transform coding design.	ISLPED	2005	DBLP DOI BibTeX RDF	MPEG-4/AVC, direct 2-D integer transform, low-power design, H.264, HDTV, digital cinema
20	Marco Antonio Dal Poz, Jose Edinson Aedo Cobo, Wilhelmus A. M. Van Noije, Marcelo Knörich Zuffo	A Simple RISC Microprocessor Core Designed for Digital Set-Top-Box Applications.	ASAP	2000	DBLP DOI BibTeX RDF	FPGA, VHDL, Reconfigurable Computing, Microprocessor, MPEG, RISC, Co-Design, Instruction Set, HDTV, Set-Top-Box, iDCT, cable TV
20	Tsuneo Ikedo	Design and performance evaluation of a pixel cache implemented within application- specific integrated circuits.	Vis. Comput.	1996	DBLP DOI BibTeX RDF	Polygon rendering, Multimedia systems, Graphics processor, HDTV
20	Tsuneo Ikedo	A scalable high-performance graphics processor: GVIP.	Vis. Comput.	1995	DBLP DOI BibTeX RDF	multi-media systems, Polygon rendering, Graphic processor, HDTV