Search results for "HLS"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
80	Vijay Raghunathan, Srivaths Ravi 0001, Ganesh Lakshminarayana	Integrating variable-latency components into high-level synthesis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
79	Apostolos A. Kountouris, Christophe Wolinski	Efficient scheduling of conditional behaviors for high-level synthesis.	ACM Trans. Design Autom. Electr. Syst.	2002	DBLP DOI BibTeX RDF	conditional behavior, scheduling, high level synthesis (HLS), Design automation
72	Daniel Gajski, Todd M. Austin, Steve Svoboda	What input-language is the best choice for high level synthesis (HLS)?	DAC	2010	DBLP DOI BibTeX RDF
72	Mark Oskin, Frederic T. Chong, Matthew K. Farrens	HLS: combining statistical and symbolic simulation to guide microprocessor designs.	ISCA	2000	DBLP DOI BibTeX RDF
70	Nurul Arif Setiawan, Seok-Ju Hong, Jang-Woon Kim, Chil-Woo Lee	Gaussian Mixture Model in Improved HLS Color Space for Human Silhouette Extraction.	ICAT	2006	DBLP DOI BibTeX RDF	Improved HLS, Gaussian Mixture Model, foreground segmentation
67	Wolfgang Kiess, Holger Füßler, Jörg Widmer, Martin Mauve	Hierarchical location service for mobile ad-hoc networks.	ACM SIGMOBILE Mob. Comput. Commun. Rev.	2004	DBLP DOI BibTeX RDF
67	Shantanu Tarafdar, Miriam Leeser	A data-centric approach to high-level synthesis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
67	Kevin Warwick, Nigel R. Ball	Self-organising neural networks for adaptive control.	J. Intell. Robotic Syst.	1996	DBLP DOI BibTeX RDF	self-organising networks, Neural networks, adaptive control
67	Hortensia Mecha, Milagros Fernández, Francisco Tirado, Julio Septién, D. Motes, Katzalin Olcoz	A method for area estimation of data-path in high level synthesis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
53	Chandan Karfa, Dipankar Sarkar 0001, Chittaranjan A. Mandal, Chris Reade	Hand-in-hand verification of high-level synthesis.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	FSMD model, formal verification, high-level synthesis, equivalence checking
53	Chao Huang, Srivaths Ravi 0001, Anand Raghunathan, Niraj K. Jha	Generation of distributed logic-memory architectures through high-level synthesis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
53	Chao Huang, Srivaths Ravi 0001, Anand Raghunathan, Niraj K. Jha	High-level synthesis of distributed logic-memory architectures.	ICCAD	2002	DBLP DOI BibTeX RDF
53	Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau	Incorporating DRAM access modes into high-level synthesis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
53	Cordula Hansen, Arno Kunzmann, Wolfgang Rosenstiel	Verification by Simulation Comparison using Interface Synthesis.	DATE	1998	DBLP DOI BibTeX RDF	Simulation Comparison, Verification, High-Level Synthesis, Interface Synthesis
52	Sriram Govindarajan, Vinoo Srinivasan, Preetham Lakshmikanthan, Ranga Vemuri	A Technique for Dynamic High-Level Exploration During Behavioral-Partitioning for Multi-Device Architectures.	VLSI Design	2000	DBLP DOI BibTeX RDF	Partitioning, High-Level Synthesis (HLS), Exploration
40	Sudipta Kundu, Sorin Lerner, Rajesh Gupta 0001	Validating High-Level Synthesis.	CAV	2008	DBLP DOI BibTeX RDF
40	Rafael Ruiz-Sautua, María C. Molina, Jose Manuel Mendias	Exploiting Bit-Level Delay Calculations to Soften Read-After-Write Dependences in Behavioral Synthesis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
40	Xinghua Ruan, Boyang Yu, Jingdong Xu, Lin Yang	A Secure Privacy-Preserving Hierarchical Location Service for Mobile Ad Hoc Networks.	MSN	2007	DBLP DOI BibTeX RDF
40	Girish Venkataramani, Tobias Bjerregaard, Tiberiu Chelcea, Seth Copen Goldstein	Hardware compilation of application-specific memory-access interconnect.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
40	Chao Huang, Srivaths Ravi 0001, Anand Raghunathan, Niraj K. Jha	Use of Computation-Unit Integrated Memories in High-Level Synthesis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
40	Seng Lin Shee, Sri Parameswaran, Newton Cheung	Novel architecture for loop acceleration: a case study.	CODES+ISSS	2005	DBLP DOI BibTeX RDF	tightly coupled, architecture, ASIP, hardware/software partitioning, coprocessor, loop optimization, latency hiding, loop pipelining, loop acceleration
40	Chao Huang, Srivaths Ravi 0001, Anand Raghunathan, Niraj K. Jha	High-level synthesis using computation-unit integrated memories.	ICCAD	2004	DBLP DOI BibTeX RDF
40	Krzysztof Kuchcinski	Constraints-driven scheduling and resource assignment.	ACM Trans. Design Autom. Electr. Syst.	2003	DBLP DOI BibTeX RDF	scheduling, high-level synthesis, Constraint programming, system-level synthesis, resource assignment
40	Vijay Raghunathan, Anand Raghunathan, Mani B. Srivastava, Milos D. Ercegovac	High-Level Synthesis with SIMD Units.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF	SIMD functional units, High-level synthesis, high performance design
40	Sumit Gupta, Nick Savoiu, Nikil D. Dutt, Rajesh K. Gupta 0001, Alexandru Nicolau, Timothy Kam, Michael Kishinevsky, Shai Rotem	Coordinated transformations for high-level synthesis of high performance microprocessor blocks.	DAC	2002	DBLP DOI BibTeX RDF	high-level synthesis, microprocessor design
40	Kazutoshi Wakabayashi, Takumi Okamoto	C-based SoC design flow and EDA tools: an ASIC and system vendorperspective.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
40	Goran Doncev, Miriam Leeser, Shantanu Tarafdar	High Level Synthesis for Designing Custom Computing Hardware.	FCCM	1998	DBLP DOI BibTeX RDF
40	Seong Yong Ohm, Fadi J. Kurdahi, Nikil D. Dutt	A unified lower bound estimation technique for high-level synthesis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
40	Chih-Tung Chen, Kayhan Küçükçakar	A Source-Level Dynamic Analysis Methodology and Tool for High-Level Synthesis.	ISSS	1997	DBLP DOI BibTeX RDF
40	Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau	Exploiting off-chip memory access modes in high-level synthesis.	ICCAD	1997	DBLP DOI BibTeX RDF	High Level Synthesis, DRAM, Memory Synthesis
40	Deniz Dal, Nazanin Mansouri	A high-level register optimization technique for minimizing leakage and dynamic power.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	power islands, register optimization, partitioning, HLS, high level synthesis, leakage, DSM
39	Seong Yong Ohm, Fadi J. Kurdahi, Nikil D. Dutt, Min Xu	A comprehensive estimation technique for high-level synthesis.	ISSS	1995	DBLP DOI BibTeX RDF	HLS benchmarks, RT level components, RTL datapaths, estimation technique, delays, high level synthesis, high-level synthesis, timing, design space exploration, granularity, hardware description languages, data flow graphs, registers, system buses, timing model, buses, behavioral description, layout area
37	Hannah Badier	Transient obfuscation for HLS security: application to cloud security, birthmarking and hardware Trojan defense. (Offuscation transitoire pour la sécurité HLS: application à la sécurité du cloud, aux filigranes numériques et à la défense contre les virus type chevaux de Troie).		2021	RDF
37	Roberto Giorgi, Farnam Khalili, Marco Procaccini	Translating Timing into an Architecture: The Synergy of COTSon and HLS (Domain Expertise - Designing a Computer Architecture via HLS).	Int. J. Reconfigurable Comput.	2019	DBLP DOI BibTeX RDF
37	Yomna Ben Jmaa	Implémentation temps réel des algorithmes de tri dans les applications de transports intelligents en se basant sur l'outil de synthèse haut niveau HLS. (Real-time implementation of sorting algorithms in intelligent transport applications based on the HLS high-level synthesis tool).		2019	RDF
33	Yishay Mor, Yannis A. Dimitriadis, Christian Köppe (eds.)	Proceedings of the Workshop on Hybrid Learning Spaces - Data, Design, Didactics co-located with 14th European Conference on Technology Enhanced Learning (EC-TEL 2019), Delft, the Netherlands, September 16, 2019.	HLS-D3@EC-TEL	2020	DBLP BibTeX RDF
33	Liat Eyal, Einat Gil	Design patterns for teaching in academic settings in future learning spaces (FLS) (extended abstract).	HLS-D3@EC-TEL	2019	DBLP BibTeX RDF
33	Christian Köppe, Rody Middelkoop	On Using Hybrid Pedagogy as Guideline for Improving Assessment Design.	HLS-D3@EC-TEL	2019	DBLP BibTeX RDF
33	Laia Albó, Davinia Hernández-Leo	How Educators Value Design Analytics for Blended Learning (extended abstract).	HLS-D3@EC-TEL	2019	DBLP BibTeX RDF
33	Yishay Mor, Yannis Dimitriadis 0001, Christian Köppe	Workshop Report: Hybrid Learning Spaces - Data, Design, Didactics.	HLS-D3@EC-TEL	2019	DBLP BibTeX RDF
33	Alice Veldkamp, Joke Daemen, Stijn Teekens, Stefan Koelewijn, Marie-Christine P. J. Knippels, Wouter R. van Joolingen	Escape boxes: bringing escape room experience into the classroom (extended abstract).	HLS-D3@EC-TEL	2019	DBLP BibTeX RDF
33	Alex Young Pedersen	Towards a Conceptualization of Hybrid Educational Spaces (HES) (extended abstract).	HLS-D3@EC-TEL	2019	DBLP BibTeX RDF
33	Estíbaliz Fraca, Maria Kambouri, Nicole Yuen, Rozina Bakirtzoglou, Gavin Mair, Ashley Highmore, Carys Hubbard, Manolis Mavrikis	A Hybrid Learning Space for Physically-Active Mathematics: the case of Numberfit.	HLS-D3@EC-TEL	2019	DBLP BibTeX RDF
33	John Cook, Yishay Mor, Patricia Santos 0001	Three cases of hybridity in learning spaces: towards a design for a Zone of Possibility (extended abstract).	HLS-D3@EC-TEL	2019	DBLP BibTeX RDF
33	Marianna Ioannou, Andri Ioannou, Yiannis Georgiou, Michael Boloudakis	Orchestrating the Technology-Enhanced Embodied Learning Classroom via Learning Stations Rotation: A case study (extended abstract).	HLS-D3@EC-TEL	2019	DBLP BibTeX RDF
33	Sergio Serrano-Iglesias, Eduardo Gómez-Sánchez, Miguel L. Bote-Lorenzo, Juan I. Asensio-Pérez, Adolfo Ruiz-Calleja, Guillermo Vega-Gorgojo, Yannis Dimitriadis 0001	Personalizing the connection between formal and informal learning in Smart Learning Environments.	HLS-D3@EC-TEL	2019	DBLP BibTeX RDF
33	Ellen Rusman, Barbara van den Broek	'Bridging' social contexts to learn from everyday life (mis)communication incidents: theoretical framing of the design of a digital reflection tool for primary school children with language impairments.	HLS-D3@EC-TEL	2019	DBLP BibTeX RDF
32	Ping Yuan, Feng Ding 0001, Peter Xiaoping Liu	HLS parameter estimation for multi-input multi-output systems.	ICRA	2008	DBLP DOI BibTeX RDF
32	Gwenolé Corre, Eric Senn, Nathalie Julien, Eric Martin 0001	Memory Aware HLS and the Implementation of Ageing Vectors.	DSD	2004	DBLP DOI BibTeX RDF
32	John Regehr, John A. Stankovic	HLS: A Framework for Composing Soft Real-Time Schedulers.	RTSS	2001	DBLP DOI BibTeX RDF
32	Johnny Öberg, Jouni Isoaho, Peeter Ellervee, Axel Jantsch, Ahmed Hemani	A Rule-Based Approach for Improving Allocation of Filter Structures in HLS.	VLSI Design	1996	DBLP DOI BibTeX RDF	CDFG, CDFG Transformations, Filter structures, Optimisations, High-Level Synthesis, Allocation, Rule-Based
27	Eunjoo Choi, Changsik Shin, Youngsoo Shin	ssr HLShbox-ssr pg: High-Level Synthesis of Power-Gated Circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2009	DBLP DOI BibTeX RDF
27	Denis Dubé, Jacob Beard, Hans Vangheluwe	Rapid Development of Scoped User Interfaces.	HCI (1)	2009	DBLP DOI BibTeX RDF
27	Ebtisam Amar, Selma Boumerdassi	Enhancing location services with prediction.	IWCMC	2009	DBLP DOI BibTeX RDF	mobile ad hoc networks, prediction, hierarchical, location service, position-based routing
27	Chandrajit L. Bajaj, Guoliang Xu, Qin Zhang 0005	Higher-Order Level-Set Method and Its Application in Biomolecular Surfaces Construction.	J. Comput. Sci. Technol.	2008	DBLP DOI BibTeX RDF	higher-order spline level-set, geometric partial differential equation, biomolecular surface
27	Pushkar Tripathi, Rohan Jain, Srikanth Kurra, Preeti Ranjan Panda	REWIRED - Register Write Inhibition by Resource Dedication.	ASP-DAC	2008	DBLP DOI BibTeX RDF
27	Yaoxing Shang, Shuai Wu, Zongxia Jiao, Xiaodong Wang	Study on Ultimate Performance of Light-duty Electro-Hydraulic Torque-Load Simulator.	RAM	2008	DBLP DOI BibTeX RDF
27	Chao Huang, Srivaths Ravi 0001, Anand Raghunathan, Niraj K. Jha	Generation of Heterogeneous Distributed Architectures for Memory-Intensive Applications Through High-Level Synthesis.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
27	Chen He, Margarida F. Jacome	Defect-Aware High-Level Synthesis Targeted at Reconfigurable Nanofabrics.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
27	Srikanth Kurra, Neeraj Kumar Singh 0004, Preeti Ranjan Panda	The impact of loop unrolling on controller delay in high level synthesis.	DATE	2007	DBLP DOI BibTeX RDF
27	Maik Boden, Thomas Fiebig, Torsten Meibner, Steffen Rülke, Jürgen Becker 0001	High-Level Synthesis of HW Tasks Targeting Run-Time Reconfigurable FPGAs.	IPDPS	2007	DBLP DOI BibTeX RDF
27	Jongyoon Jung, Taewhan Kim	Timing variation-aware high-level synthesis.	ICCAD	2007	DBLP DOI BibTeX RDF
27	Hadda Cherroun, Alain Darte, Paul Feautrier	Scheduling under resource constraints using dis-equations.	DATE	2006	DBLP DOI BibTeX RDF
27	Heiner Giefers, Achim Rettberg	Energy aware multiple clock domain scheduling for a bit-serial, self-timed architecture.	SBCCI	2006	DBLP DOI BibTeX RDF	high-level synthesis, low power design, voltage scaling, bit-serial architecture
27	Youn Tae Kim, Hyeon Bae, Sungshin Kim, Kwang-Baek Kim, Hoon Kang	Natural Color Recognition Using Fuzzification and a Neural Network for Industrial Applications.	ISNN (2)	2006	DBLP DOI BibTeX RDF
27	Rehab F. Abdel-Kader	Resource-constrained loop scheduling in high-level synthesis.	ACM Southeast Regional Conference (2)	2005	DBLP DOI BibTeX RDF	scheduling, high-level synthesis, force-directed scheduling
27	Youngsik Kim, Shekhar Kopuri, Nazanin Mansouri	Automated Formal Verification of Scheduling Process Using Finite State Machines with Datapath (FSMD).	ISQED	2004	DBLP DOI BibTeX RDF
27	Ivan Augé, François Donnet, Frédéric Pétrot	Retiming Finite State Machines to Control Hardened Data-Paths.	SBCCI	2003	DBLP DOI BibTeX RDF
27	Chao Huang, Srivaths Ravi 0001, Anand Raghunathan, Niraj K. Jha	Synthesis of Heterogeneous Distributed Architectures for Memory-Intensive Applications.	ICCAD	2003	DBLP DOI BibTeX RDF
27	Saeed Safari, Hadi Esmaeilzadeh, Amir-Hossein Jahangir	A novel improvement technique for high-level test synthesis.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
27	Olga Peñalba, José M. Mendías, Román Hermida	Source Code Transformation to Improve Conditional Hardware Reuse.	DSD	2002	DBLP DOI BibTeX RDF
27	Ravishankar Rao, Mark Oskin, Frederic T. Chong	HLSpower: Hybrid Statistical Modeling of the Superscalar Power-Performance Design Space.	HiPC	2002	DBLP DOI BibTeX RDF
27	Krzysztof Kuchcinski, Christophe Wolinski	Synthesis of Conditional Behaviors Using Hierarchical Conditional Dependency Graphs and Constraint Logic Programming.	DSD	2001	DBLP DOI BibTeX RDF
27	Apostolos A. Kountouris, Christophe Wolinski	Hierarchical Conditional Dependency Graphs as a Unifying Design Representation in the CODESIS High-Level Synthesis System.	ISSS	2000	DBLP DOI BibTeX RDF
27	Kamal S. Khouri, Niraj K. Jha	Leakage Power Analysis and Reduction during Behavioral Synthesis.	ICCD	2000	DBLP DOI BibTeX RDF
27	Kia Bazargan, Abhishek Ranjan, Majid Sarrafzadeh	Fast and accurate estimation of floorplans in logic/high-level synthesis.	ACM Great Lakes Symposium on VLSI	2000	DBLP DOI BibTeX RDF
27	Min Xu, Fadi J. Kurdahi	Accurate prediction of quality metrics for logic level designs targeted toward lookup-table-based FPGAs.	IEEE Trans. Very Large Scale Integr. Syst.	1999	DBLP DOI BibTeX RDF
27	Apostolos A. Kountouris, Christophe Wolinski	High Level Pre-Synthesis Optimization Steps Using Hierarchical Conditional Dependency Graphs.	EUROMICRO	1999	DBLP DOI BibTeX RDF
27	Shantanu Tarafdar, Miriam Leeser	The DT-Model: High-Level Synthesis Using Data Transfers.	DAC	1998	DBLP DOI BibTeX RDF	high-level synthesis, telecommunication
27	Bengt Svantesson, Ahmed Hemani, Peeter Ellervee, Adam Postula, Johnny Öberg, Axel Jantsch, Hannu Tenhunen	A Novell Allocation Strategy for Control and Memory Intensive Telecommunication Circiuts.	VLSI Design	1996	DBLP DOI BibTeX RDF	Application specific High-Level Synthesis, High-Level Synthesis for telecommunication, ATM
27	Preeti Ranjan Panda, Nikil D. Dutt	1995 high level synthesis design repository.	ISSS	1995	DBLP DOI BibTeX RDF	1995 high level synthesis design repository, VHDL language, behavioral finite state machines, behavioral level, computational complexity, high level synthesis, finite state machines, VHDL, microprocessors, hardware description languages, microprocessor chips, floating point units
26	Jason Cong, Muhuan Huang, Yi Zou	Accelerating Fluid Registration Algorithm on Multi-FPGA Platforms.	FPL	2011	DBLP DOI BibTeX RDF	fluid registration, FPGA, HLS
26	Hariharan Sankaran, Srinivas Katkoori	Bus Binding, Re-ordering, and Encoding for Crosstalk-Producing Switching Activity Minimization during High Level Synthesis.	DELTA	2008	DBLP DOI BibTeX RDF	Simulated Annealing, HLS, Encoding, Crosstalk, Binding, Reordering
26	Mehrdad Reshadi, Bita Gorjiara, Daniel Gajski	C-based design flow: a case study on G.729A for voice over internet protocol (VoIP).	DAC	2008	DBLP DOI BibTeX RDF	C-based design flow, C-to-RTL, G729A, NISC, HLS, VoIP, ASIP
25	Rosilde Corvino, Stéphane Mancini, Roberto Guizzetti	Automatic generation of a parallel tile processing unit for algorithms with non-affine array references.	IFMT	2008	DBLP DOI BibTeX RDF	computations scheduling, design space exploration (DSE), non-affine array references, super-tiling, mapping, high-level synthesis (HLS), tiling
25	Chittaranjan A. Mandal, R. M. Zimmer	A Genetic Algorithm for the Synthesis of Structured Data Paths.	VLSI Design	2000	DBLP DOI BibTeX RDF	Data Path Synthesis (DPS), Scheduling, High-Level Synthesis (HLS), Allocation
18	Rahul Chaurasia, Anirban Sengupta	Multi-cut based architectural obfuscation and handprint biometric signature for securing transient fault detectable IP cores during HLS.	Integr.	2024	DBLP DOI BibTeX RDF
18	Sanshuang Jin, Yunkun Zhao, Ruizhe Wu, Fangfang Wu, Tianyu Zhou, Baogen Sun, Jigang Wang	Two-Dimensional Visible Synchrotron Radiation Interferometry for Measuring Transverse Beam-Profile at HLS-II.	IEEE Instrum. Meas. Mag.	2024	DBLP DOI BibTeX RDF
18	Hanchen Ye, David Z. Pan, Chris Leary, Deming Chen, Xiaoqing Xu	Subgraph Extraction-based Feedback-guided Iterative Scheduling for HLS.	CoRR	2024	DBLP DOI BibTeX RDF
18	Md Rubel Ahmed, Toshiaki Koike-Akino, Kieran Parsons, Ye Wang	AutoHLS: Learning to Accelerate Design Space Exploration for HLS Designs.	CoRR	2024	DBLP DOI BibTeX RDF
18	Louis-Noël Pouchet, Emily Tucker, Niansong Zhang, Hongzheng Chen, Debjit Pal, Gabriel Rodríguez 0001, Zhiru Zhang	Formal Verification of Source-to-Source Transformations for HLS.	FPGA	2024	DBLP DOI BibTeX RDF
18	Daiki Furukawa, Taito Manabe, Yuichiro Shibata, Tomohiro Ueno, Kentaro Sano	HLS Implementation of a Building Cube Stencil Computation Framework for an FPGA Accelerator.	ICCE	2024	DBLP DOI BibTeX RDF
18	Haruto Ikehara, Taito Manabe, Yuichiro Shibata, Tomohiro Ueno, Kentaro Sano	A Productive HLS Simulation Approach for Multi-FPGA Systems.	ICCE	2024	DBLP DOI BibTeX RDF
18	Licheng Guo, Yuze Chi, Jason Lau, Linghao Song, Xingyu Tian, Moazin Khatti, Weikang Qiao, Jie Wang 0022, Ecenur Ustun, Zhenman Fang, Zhiru Zhang, Jason Cong	TAPA: A Scalable Task-parallel Dataflow Programming Framework for Modern FPGAs with Co-optimization of HLS and Physical Design.	ACM Trans. Reconfigurable Technol. Syst.	2023	DBLP DOI BibTeX RDF
18	Michael Guilherme Jordan, Bernardo Neuhaus Lignati, Guilherme Korol, Mateus Beck Rutzig, Antonio Carlos Schneider Beck	MVSym: Efficient symbiotic exploitation of HLS-kernel multi-versioning for collaborative CPU-FPGA cloud systems.	Integr.	2023	DBLP DOI BibTeX RDF
18	Lu Xiao, Zheng Xiao, Fan Wu, Yunchuan Qin, Kenli Li 0001	Optimization on operation sorting for HLS scheduling algorithms.	Integr.	2023	DBLP DOI BibTeX RDF
18	B. B. Shabarinath, Muralidhar Pullakandam	SoC-based real-time SVM classification with integrated training using HLS and PYNQ.	Microprocess. Microsystems	2023	DBLP DOI BibTeX RDF
18	Sayandip De, Muhammad Shafique 0001, Henk Corporaal	Delay Prediction for ASIC HLS: Comparing Graph-Based and Nongraph-Based Learning Models.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2023	DBLP DOI BibTeX RDF
18	Nan Wu, Yuan Xie 0001, Cong Hao	IronMan-Pro: Multiobjective Design Space Exploration in HLS via Reinforcement Learning and Graph Neural Network-Based Modeling.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2023	DBLP DOI BibTeX RDF
18	Zhe Lin, Tingyuan Liang, Jieru Zhao, Sharad Sinha, Wei Zhang 0012	HL-Pow: Learning-Assisted Pre-RTL Power Modeling and Optimization for FPGA HLS.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2023	DBLP DOI BibTeX RDF