Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
80 | Vijay Raghunathan, Srivaths Ravi 0001, Ganesh Lakshminarayana |
Integrating variable-latency components into high-level synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(10), pp. 1105-1117, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
79 | Apostolos A. Kountouris, Christophe Wolinski |
Efficient scheduling of conditional behaviors for high-level synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 7(3), pp. 380-412, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
conditional behavior, scheduling, high level synthesis (HLS), Design automation |
72 | Daniel Gajski, Todd M. Austin, Steve Svoboda |
What input-language is the best choice for high level synthesis (HLS)? ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 47th Design Automation Conference, DAC 2010, Anaheim, California, USA, July 13-18, 2010, pp. 857-858, 2010, ACM, 978-1-4503-0002-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
72 | Mark Oskin, Frederic T. Chong, Matthew K. Farrens |
HLS: combining statistical and symbolic simulation to guide microprocessor designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 27th International Symposium on Computer Architecture (ISCA 2000), June 10-14, 2000, Vancouver, BC, Canada, pp. 71-82, 2000, IEEE Computer Society, 978-1-58113-232-8. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
70 | Nurul Arif Setiawan, Seok-Ju Hong, Jang-Woon Kim, Chil-Woo Lee |
Gaussian Mixture Model in Improved HLS Color Space for Human Silhouette Extraction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICAT ![In: Advances in Artificial Reality and Tele-Existence, 16th International Conference on Artificial Reality and Telexistence, ICAT 2006, Hangzhou, China, November 29 - December 1, 2006, Proceedings, pp. 732-741, 2006, Springer, 3-540-49776-5. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Improved HLS, Gaussian Mixture Model, foreground segmentation |
67 | Wolfgang Kiess, Holger Füßler, Jörg Widmer, Martin Mauve |
Hierarchical location service for mobile ad-hoc networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM SIGMOBILE Mob. Comput. Commun. Rev. ![In: ACM SIGMOBILE Mob. Comput. Commun. Rev. 8(4), pp. 47-58, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
67 | Shantanu Tarafdar, Miriam Leeser |
A data-centric approach to high-level synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(11), pp. 1251-1267, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
67 | Kevin Warwick, Nigel R. Ball |
Self-organising neural networks for adaptive control. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Intell. Robotic Syst. ![In: J. Intell. Robotic Syst. 15(2), pp. 153-163, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
self-organising networks, Neural networks, adaptive control |
67 | Hortensia Mecha, Milagros Fernández, Francisco Tirado, Julio Septién, D. Motes, Katzalin Olcoz |
A method for area estimation of data-path in high level synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(2), pp. 258-265, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
53 | Chandan Karfa, Dipankar Sarkar 0001, Chittaranjan A. Mandal, Chris Reade |
Hand-in-hand verification of high-level synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, Stresa, Lago Maggiore, Italy, March 11-13, 2007, pp. 429-434, 2007, ACM, 978-1-59593-605-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
FSMD model, formal verification, high-level synthesis, equivalence checking |
53 | Chao Huang, Srivaths Ravi 0001, Anand Raghunathan, Niraj K. Jha |
Generation of distributed logic-memory architectures through high-level synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(11), pp. 1694-1711, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
53 | Chao Huang, Srivaths Ravi 0001, Anand Raghunathan, Niraj K. Jha |
High-level synthesis of distributed logic-memory architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, ICCAD 2002, San Jose, California, USA, November 10-14, 2002, pp. 564-571, 2002, ACM / IEEE Computer Society, 0-7803-7607-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
53 | Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau |
Incorporating DRAM access modes into high-level synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(2), pp. 96-109, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
53 | Cordula Hansen, Arno Kunzmann, Wolfgang Rosenstiel |
Verification by Simulation Comparison using Interface Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1998 Design, Automation and Test in Europe (DATE '98), February 23-26, 1998, Le Palais des Congrès de Paris, Paris, France, pp. 436-443, 1998, IEEE Computer Society, 0-8186-8359-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
Simulation Comparison, Verification, High-Level Synthesis, Interface Synthesis |
52 | Sriram Govindarajan, Vinoo Srinivasan, Preetham Lakshmikanthan, Ranga Vemuri |
A Technique for Dynamic High-Level Exploration During Behavioral-Partitioning for Multi-Device Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 13th International Conference on VLSI Design (VLSI Design 2000), 4-7 January 2000, Calcutta, India, pp. 212-219, 2000, IEEE Computer Society, 0-7695-0487-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Partitioning, High-Level Synthesis (HLS), Exploration |
40 | Sudipta Kundu, Sorin Lerner, Rajesh Gupta 0001 |
Validating High-Level Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAV ![In: Computer Aided Verification, 20th International Conference, CAV 2008, Princeton, NJ, USA, July 7-14, 2008, Proceedings, pp. 459-472, 2008, Springer, 978-3-540-70543-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
40 | Rafael Ruiz-Sautua, María C. Molina, Jose Manuel Mendias |
Exploiting Bit-Level Delay Calculations to Soften Read-After-Write Dependences in Behavioral Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(9), pp. 1589-1601, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
40 | Xinghua Ruan, Boyang Yu, Jingdong Xu, Lin Yang |
A Secure Privacy-Preserving Hierarchical Location Service for Mobile Ad Hoc Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MSN ![In: Mobile Ad-Hoc and Sensor Networks, Third International Conference, MSN 2007, Beijing, China, December 12-14, 2007, Proceedings, pp. 760-771, 2007, Springer, 978-3-540-77023-7. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
40 | Girish Venkataramani, Tobias Bjerregaard, Tiberiu Chelcea, Seth Copen Goldstein |
Hardware compilation of application-specific memory-access interconnect. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(5), pp. 756-771, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
40 | Chao Huang, Srivaths Ravi 0001, Anand Raghunathan, Niraj K. Jha |
Use of Computation-Unit Integrated Memories in High-Level Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(10), pp. 1969-1989, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
40 | Seng Lin Shee, Sri Parameswaran, Newton Cheung |
Novel architecture for loop acceleration: a case study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2005, Jersey City, NJ, USA, September 19-21, 2005, pp. 297-302, 2005, ACM, 1-59593-161-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
tightly coupled, architecture, ASIP, hardware/software partitioning, coprocessor, loop optimization, latency hiding, loop pipelining, loop acceleration |
40 | Chao Huang, Srivaths Ravi 0001, Anand Raghunathan, Niraj K. Jha |
High-level synthesis using computation-unit integrated memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2004 International Conference on Computer-Aided Design, ICCAD 2004, San Jose, CA, USA, November 7-11, 2004, pp. 783-790, 2004, IEEE Computer Society / ACM, 0-7803-8702-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
40 | Krzysztof Kuchcinski |
Constraints-driven scheduling and resource assignment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 8(3), pp. 355-383, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
scheduling, high-level synthesis, Constraint programming, system-level synthesis, resource assignment |
40 | Vijay Raghunathan, Anand Raghunathan, Mani B. Srivastava, Milos D. Ercegovac |
High-Level Synthesis with SIMD Units. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC/VLSI Design ![In: Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), and the 15th International Conference on VLSI Design (VLSI Design 2002), Bangalore, India, January 7-11, 2002, pp. 407-413, 2002, IEEE Computer Society, 0-7695-1299-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
SIMD functional units, High-level synthesis, high performance design |
40 | Sumit Gupta, Nick Savoiu, Nikil D. Dutt, Rajesh K. Gupta 0001, Alexandru Nicolau, Timothy Kam, Michael Kishinevsky, Shai Rotem |
Coordinated transformations for high-level synthesis of high performance microprocessor blocks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 39th Design Automation Conference, DAC 2002, New Orleans, LA, USA, June 10-14, 2002, pp. 898-903, 2002, ACM, 1-58113-461-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
high-level synthesis, microprocessor design |
40 | Kazutoshi Wakabayashi, Takumi Okamoto |
C-based SoC design flow and EDA tools: an ASIC and system vendorperspective. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(12), pp. 1507-1522, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
40 | Goran Doncev, Miriam Leeser, Shantanu Tarafdar |
High Level Synthesis for Designing Custom Computing Hardware. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 6th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '98), 15-17 April 1998, Napa Valley, CA, USA, pp. 326-328, 1998, IEEE Computer Society, 0-8186-8900-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
40 | Seong Yong Ohm, Fadi J. Kurdahi, Nikil D. Dutt |
A unified lower bound estimation technique for high-level synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(5), pp. 458-472, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
40 | Chih-Tung Chen, Kayhan Küçükçakar |
A Source-Level Dynamic Analysis Methodology and Tool for High-Level Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSS ![In: Proceedings of the 10th International Symposium on System Synthesis, ISSS '97, Antwerp, Belgium, September 17-19, 1997., pp. 134-140, 1997, ACM / IEEE Computer Society, 0-8186-7949-2. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
40 | Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau |
Exploiting off-chip memory access modes in high-level synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1997, San Jose, CA, USA, November 9-13, 1997, pp. 333-340, 1997, IEEE Computer Society / ACM, 0-8186-8200-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
High Level Synthesis, DRAM, Memory Synthesis |
40 | Deniz Dal, Nazanin Mansouri |
A high-level register optimization technique for minimizing leakage and dynamic power. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, Stresa, Lago Maggiore, Italy, March 11-13, 2007, pp. 517-520, 2007, ACM, 978-1-59593-605-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
power islands, register optimization, partitioning, HLS, high level synthesis, leakage, DSM |
39 | Seong Yong Ohm, Fadi J. Kurdahi, Nikil D. Dutt, Min Xu |
A comprehensive estimation technique for high-level synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSS ![In: Proceedings of the 8th International Symposium on System Synthesis (ISSS 1995), September 13-15, 1995, Cannes, France, pp. 122-127, 1995, ACM, 0-89791-771-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
HLS benchmarks, RT level components, RTL datapaths, estimation technique, delays, high level synthesis, high-level synthesis, timing, design space exploration, granularity, hardware description languages, data flow graphs, registers, system buses, timing model, buses, behavioral description, layout area |
37 | Hannah Badier |
Transient obfuscation for HLS security: application to cloud security, birthmarking and hardware Trojan defense. (Offuscation transitoire pour la sécurité HLS: application à la sécurité du cloud, aux filigranes numériques et à la défense contre les virus type chevaux de Troie). ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2021 |
RDF |
|
37 | Roberto Giorgi, Farnam Khalili, Marco Procaccini |
Translating Timing into an Architecture: The Synergy of COTSon and HLS (Domain Expertise - Designing a Computer Architecture via HLS). ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Reconfigurable Comput. ![In: Int. J. Reconfigurable Comput. 2019, pp. 2624938:1-2624938:18, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
37 | Yomna Ben Jmaa |
Implémentation temps réel des algorithmes de tri dans les applications de transports intelligents en se basant sur l'outil de synthèse haut niveau HLS. (Real-time implementation of sorting algorithms in intelligent transport applications based on the HLS high-level synthesis tool). ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2019 |
RDF |
|
33 | Yishay Mor, Yannis A. Dimitriadis, Christian Köppe (eds.) |
Proceedings of the Workshop on Hybrid Learning Spaces - Data, Design, Didactics co-located with 14th European Conference on Technology Enhanced Learning (EC-TEL 2019), Delft, the Netherlands, September 16, 2019. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HLS-D3@EC-TEL ![CEUR-WS.org The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP BibTeX RDF |
|
33 | Liat Eyal, Einat Gil |
Design patterns for teaching in academic settings in future learning spaces (FLS) (extended abstract). ![Search on Bibsonomy](Pics/bibsonomy.png) |
HLS-D3@EC-TEL ![In: Proceedings of the Workshop on Hybrid Learning Spaces - Data, Design, Didactics co-located with 14th European Conference on Technology Enhanced Learning (EC-TEL 2019), Delft, the Netherlands, September 16, 2019., pp. 60-62, 2019, CEUR-WS.org. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP BibTeX RDF |
|
33 | Christian Köppe, Rody Middelkoop |
On Using Hybrid Pedagogy as Guideline for Improving Assessment Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HLS-D3@EC-TEL ![In: Proceedings of the Workshop on Hybrid Learning Spaces - Data, Design, Didactics co-located with 14th European Conference on Technology Enhanced Learning (EC-TEL 2019), Delft, the Netherlands, September 16, 2019., pp. 29-40, 2019, CEUR-WS.org. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP BibTeX RDF |
|
33 | Laia Albó, Davinia Hernández-Leo |
How Educators Value Design Analytics for Blended Learning (extended abstract). ![Search on Bibsonomy](Pics/bibsonomy.png) |
HLS-D3@EC-TEL ![In: Proceedings of the Workshop on Hybrid Learning Spaces - Data, Design, Didactics co-located with 14th European Conference on Technology Enhanced Learning (EC-TEL 2019), Delft, the Netherlands, September 16, 2019., pp. 53-55, 2019, CEUR-WS.org. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP BibTeX RDF |
|
33 | Yishay Mor, Yannis Dimitriadis 0001, Christian Köppe |
Workshop Report: Hybrid Learning Spaces - Data, Design, Didactics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HLS-D3@EC-TEL ![In: Proceedings of the Workshop on Hybrid Learning Spaces - Data, Design, Didactics co-located with 14th European Conference on Technology Enhanced Learning (EC-TEL 2019), Delft, the Netherlands, September 16, 2019., pp. 1-14, 2019, CEUR-WS.org. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP BibTeX RDF |
|
33 | Alice Veldkamp, Joke Daemen, Stijn Teekens, Stefan Koelewijn, Marie-Christine P. J. Knippels, Wouter R. van Joolingen |
Escape boxes: bringing escape room experience into the classroom (extended abstract). ![Search on Bibsonomy](Pics/bibsonomy.png) |
HLS-D3@EC-TEL ![In: Proceedings of the Workshop on Hybrid Learning Spaces - Data, Design, Didactics co-located with 14th European Conference on Technology Enhanced Learning (EC-TEL 2019), Delft, the Netherlands, September 16, 2019., pp. 67-70, 2019, CEUR-WS.org. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP BibTeX RDF |
|
33 | Alex Young Pedersen |
Towards a Conceptualization of Hybrid Educational Spaces (HES) (extended abstract). ![Search on Bibsonomy](Pics/bibsonomy.png) |
HLS-D3@EC-TEL ![In: Proceedings of the Workshop on Hybrid Learning Spaces - Data, Design, Didactics co-located with 14th European Conference on Technology Enhanced Learning (EC-TEL 2019), Delft, the Netherlands, September 16, 2019., pp. 63-66, 2019, CEUR-WS.org. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP BibTeX RDF |
|
33 | Estíbaliz Fraca, Maria Kambouri, Nicole Yuen, Rozina Bakirtzoglou, Gavin Mair, Ashley Highmore, Carys Hubbard, Manolis Mavrikis |
A Hybrid Learning Space for Physically-Active Mathematics: the case of Numberfit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HLS-D3@EC-TEL ![In: Proceedings of the Workshop on Hybrid Learning Spaces - Data, Design, Didactics co-located with 14th European Conference on Technology Enhanced Learning (EC-TEL 2019), Delft, the Netherlands, September 16, 2019., pp. 15-24, 2019, CEUR-WS.org. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP BibTeX RDF |
|
33 | John Cook, Yishay Mor, Patricia Santos 0001 |
Three cases of hybridity in learning spaces: towards a design for a Zone of Possibility (extended abstract). ![Search on Bibsonomy](Pics/bibsonomy.png) |
HLS-D3@EC-TEL ![In: Proceedings of the Workshop on Hybrid Learning Spaces - Data, Design, Didactics co-located with 14th European Conference on Technology Enhanced Learning (EC-TEL 2019), Delft, the Netherlands, September 16, 2019., pp. 56-59, 2019, CEUR-WS.org. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP BibTeX RDF |
|
33 | Marianna Ioannou, Andri Ioannou, Yiannis Georgiou, Michael Boloudakis |
Orchestrating the Technology-Enhanced Embodied Learning Classroom via Learning Stations Rotation: A case study (extended abstract). ![Search on Bibsonomy](Pics/bibsonomy.png) |
HLS-D3@EC-TEL ![In: Proceedings of the Workshop on Hybrid Learning Spaces - Data, Design, Didactics co-located with 14th European Conference on Technology Enhanced Learning (EC-TEL 2019), Delft, the Netherlands, September 16, 2019., pp. 25-28, 2019, CEUR-WS.org. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP BibTeX RDF |
|
33 | Sergio Serrano-Iglesias, Eduardo Gómez-Sánchez, Miguel L. Bote-Lorenzo, Juan I. Asensio-Pérez, Adolfo Ruiz-Calleja, Guillermo Vega-Gorgojo, Yannis Dimitriadis 0001 |
Personalizing the connection between formal and informal learning in Smart Learning Environments. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HLS-D3@EC-TEL ![In: Proceedings of the Workshop on Hybrid Learning Spaces - Data, Design, Didactics co-located with 14th European Conference on Technology Enhanced Learning (EC-TEL 2019), Delft, the Netherlands, September 16, 2019., pp. 47-52, 2019, CEUR-WS.org. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP BibTeX RDF |
|
33 | Ellen Rusman, Barbara van den Broek |
'Bridging' social contexts to learn from everyday life (mis)communication incidents: theoretical framing of the design of a digital reflection tool for primary school children with language impairments. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HLS-D3@EC-TEL ![In: Proceedings of the Workshop on Hybrid Learning Spaces - Data, Design, Didactics co-located with 14th European Conference on Technology Enhanced Learning (EC-TEL 2019), Delft, the Netherlands, September 16, 2019., pp. 41-46, 2019, CEUR-WS.org. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP BibTeX RDF |
|
32 | Ping Yuan, Feng Ding 0001, Peter Xiaoping Liu |
HLS parameter estimation for multi-input multi-output systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICRA ![In: 2008 IEEE International Conference on Robotics and Automation, ICRA 2008, May 19-23, 2008, Pasadena, California, USA, pp. 857-861, 2008, IEEE. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
32 | Gwenolé Corre, Eric Senn, Nathalie Julien, Eric Martin 0001 |
Memory Aware HLS and the Implementation of Ageing Vectors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 2004 Euromicro Symposium on Digital Systems Design (DSD 2004), Architectures, Methods and Tools, 31 August - 3 September 2004, Rennes, France, pp. 88-95, 2004, IEEE Computer Society, 0-7695-2203-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
32 | John Regehr, John A. Stankovic |
HLS: A Framework for Composing Soft Real-Time Schedulers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RTSS ![In: Proceedings of the 22nd IEEE Real-Time Systems Symposium (RTSS 2001), London, UK, 2-6 December 2001, pp. 3-14, 2001, IEEE Computer Society, 0-7695-1420-0. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
32 | Johnny Öberg, Jouni Isoaho, Peeter Ellervee, Axel Jantsch, Ahmed Hemani |
A Rule-Based Approach for Improving Allocation of Filter Structures in HLS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 9th International Conference on VLSI Design (VLSI Design 1996), 3-6 January 1996, Bangalore, India, pp. 133-139, 1996, IEEE Computer Society, 0-8186-7228-5. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
CDFG, CDFG Transformations, Filter structures, Optimisations, High-Level Synthesis, Allocation, Rule-Based |
27 | Eunjoo Choi, Changsik Shin, Youngsoo Shin |
ssr HLShbox-ssr pg: High-Level Synthesis of Power-Gated Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(3), pp. 451-456, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
27 | Denis Dubé, Jacob Beard, Hans Vangheluwe |
Rapid Development of Scoped User Interfaces. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HCI (1) ![In: Human-Computer Interaction. New Trends, 13th International Conference, HCI International 2009, San Diego, CA, USA, July 19-24, 2009, Proceedings, Part I, pp. 816-825, 2009, Springer, 978-3-642-02573-0. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
27 | Ebtisam Amar, Selma Boumerdassi |
Enhancing location services with prediction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IWCMC ![In: Proceedings of the International Conference on Wireless Communications and Mobile Computing: Connecting the World Wirelessly, IWCMC 2009, Leipzig, Germany, June 21-24, 2009, pp. 1025-1029, 2009, ACM, 978-1-60558-569-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
mobile ad hoc networks, prediction, hierarchical, location service, position-based routing |
27 | Chandrajit L. Bajaj, Guoliang Xu, Qin Zhang 0005 |
Higher-Order Level-Set Method and Its Application in Biomolecular Surfaces Construction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Comput. Sci. Technol. ![In: J. Comput. Sci. Technol. 23(6), pp. 1026-1036, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
higher-order spline level-set, geometric partial differential equation, biomolecular surface |
27 | Pushkar Tripathi, Rohan Jain, Srikanth Kurra, Preeti Ranjan Panda |
REWIRED - Register Write Inhibition by Resource Dedication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 13th Asia South Pacific Design Automation Conference, ASP-DAC 2008, Seoul, Korea, January 21-24, 2008, pp. 28-31, 2008, IEEE, 978-1-4244-1921-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
27 | Yaoxing Shang, Shuai Wu, Zongxia Jiao, Xiaodong Wang |
Study on Ultimate Performance of Light-duty Electro-Hydraulic Torque-Load Simulator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RAM ![In: 2008 IEEE Conference on Robotics, Automation and Mechatronics, RAM 2008, 21-24 September 2008, Chengdu, China, pp. 387-392, 2008, IEEE. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
27 | Chao Huang, Srivaths Ravi 0001, Anand Raghunathan, Niraj K. Jha |
Generation of Heterogeneous Distributed Architectures for Memory-Intensive Applications Through High-Level Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 15(11), pp. 1191-1204, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
27 | Chen He, Margarida F. Jacome |
Defect-Aware High-Level Synthesis Targeted at Reconfigurable Nanofabrics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(5), pp. 817-833, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
27 | Srikanth Kurra, Neeraj Kumar Singh 0004, Preeti Ranjan Panda |
The impact of loop unrolling on controller delay in high level synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2007 Design, Automation and Test in Europe Conference and Exposition, DATE 2007, Nice, France, April 16-20, 2007, pp. 391-396, 2007, EDA Consortium, San Jose, CA, USA, 978-3-9810801-2-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
27 | Maik Boden, Thomas Fiebig, Torsten Meibner, Steffen Rülke, Jürgen Becker 0001 |
High-Level Synthesis of HW Tasks Targeting Run-Time Reconfigurable FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), Proceedings, 26-30 March 2007, Long Beach, California, USA, pp. 1-8, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
27 | Jongyoon Jung, Taewhan Kim |
Timing variation-aware high-level synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2007 International Conference on Computer-Aided Design, ICCAD 2007, San Jose, CA, USA, November 5-8, 2007, pp. 424-428, 2007, IEEE Computer Society, 1-4244-1382-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
27 | Hadda Cherroun, Alain Darte, Paul Feautrier |
Scheduling under resource constraints using dis-equations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006, pp. 1067-1072, 2006, European Design and Automation Association, Leuven, Belgium, 3-9810801-1-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
27 | Heiner Giefers, Achim Rettberg |
Energy aware multiple clock domain scheduling for a bit-serial, self-timed architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2006, Ouro Preto, MG, Brazil, August 28 - September 1, 2006, pp. 113-118, 2006, ACM. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
high-level synthesis, low power design, voltage scaling, bit-serial architecture |
27 | Youn Tae Kim, Hyeon Bae, Sungshin Kim, Kwang-Baek Kim, Hoon Kang |
Natural Color Recognition Using Fuzzification and a Neural Network for Industrial Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISNN (2) ![In: Advances in Neural Networks - ISNN 2006, Third International Symposium on Neural Networks, Chengdu, China, May 28 - June 1, 2006, Proceedings, Part III, pp. 991-996, 2006, Springer, 3-540-34482-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
27 | Rehab F. Abdel-Kader |
Resource-constrained loop scheduling in high-level synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Southeast Regional Conference (2) ![In: Proceedings of the 43nd Annual Southeast Regional Conference, 2005, Kennesaw, Georgia, Alabama, USA, March 18-20, 2005, Volume 2, pp. 195-200, 2005, ACM. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
scheduling, high-level synthesis, force-directed scheduling |
27 | Youngsik Kim, Shekhar Kopuri, Nazanin Mansouri |
Automated Formal Verification of Scheduling Process Using Finite State Machines with Datapath (FSMD). ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 5th International Symposium on Quality of Electronic Design (ISQED 2004), 22-24 March 2004, San Jose, CA, USA, pp. 110-115, 2004, IEEE Computer Society, 0-7695-2093-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
27 | Ivan Augé, François Donnet, Frédéric Pétrot |
Retiming Finite State Machines to Control Hardened Data-Paths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 16th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2003, Sao Paulo, Brazil, September 8-11, 2003, pp. 41-46, 2003, IEEE Computer Society, 0-7695-2009-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
27 | Chao Huang, Srivaths Ravi 0001, Anand Raghunathan, Niraj K. Jha |
Synthesis of Heterogeneous Distributed Architectures for Memory-Intensive Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2003 International Conference on Computer-Aided Design, ICCAD 2003, San Jose, CA, USA, November 9-13, 2003, pp. 46-53, 2003, IEEE Computer Society / ACM, 1-58113-762-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
27 | Saeed Safari, Hadi Esmaeilzadeh, Amir-Hossein Jahangir |
A novel improvement technique for high-level test synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 609-612, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
27 | Olga Peñalba, José M. Mendías, Román Hermida |
Source Code Transformation to Improve Conditional Hardware Reuse. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 2002 Euromicro Symposium on Digital Systems Design (DSD 2002), Systems-on-Chip, 4-6 September 2002, Dortmund, Germany, pp. 324-331, 2002, IEEE Computer Society, 0-7695-1790-0. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
27 | Ravishankar Rao, Mark Oskin, Frederic T. Chong |
HLSpower: Hybrid Statistical Modeling of the Superscalar Power-Performance Design Space. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HiPC ![In: High Performance Computing - HiPC 2002, 9th International Conference, Bangalore, India, December 18-21, 2002, Proceedings, pp. 620-629, 2002, Springer, 3-540-00303-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
27 | Krzysztof Kuchcinski, Christophe Wolinski |
Synthesis of Conditional Behaviors Using Hierarchical Conditional Dependency Graphs and Constraint Logic Programming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: Euromicro Symposium on Digital Systems Design 2001 (Euro-DSD 2001), 4-6 September 2001, Warsaw, Poland, pp. 220-227, 2001, IEEE Computer Society, 0-7695-1239-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
27 | Apostolos A. Kountouris, Christophe Wolinski |
Hierarchical Conditional Dependency Graphs as a Unifying Design Representation in the CODESIS High-Level Synthesis System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSS ![In: Proceedings of the 13th International Symposium on System Synthesis, ISSS'00, Madrid, Spain, September 20-22, 2000., pp. 66-72, 2000, ACM / IEEE Computer Society, 0-7695-0765-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
27 | Kamal S. Khouri, Niraj K. Jha |
Leakage Power Analysis and Reduction during Behavioral Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, ICCD '00, Austin, Texas, USA, September 17-20, 2000, pp. 561-564, 2000, IEEE Computer Society, 0-7695-0801-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
27 | Kia Bazargan, Abhishek Ranjan, Majid Sarrafzadeh |
Fast and accurate estimation of floorplans in logic/high-level synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 10th ACM Great Lakes Symposium on VLSI 2000, Chicago, Illinois, USA, March 2-4, 2000, pp. 95-100, 2000, ACM, 1-58113-251-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
27 | Min Xu, Fadi J. Kurdahi |
Accurate prediction of quality metrics for logic level designs targeted toward lookup-table-based FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 7(4), pp. 411-418, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
27 | Apostolos A. Kountouris, Christophe Wolinski |
High Level Pre-Synthesis Optimization Steps Using Hierarchical Conditional Dependency Graphs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROMICRO ![In: 25th EUROMICRO '99 Conference, Informatics: Theory and Practice for the New Millenium, 8-10 September 1999, Milan, Italy, pp. 1290-, 1999, IEEE Computer Society, 0-7695-0321-7. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
27 | Shantanu Tarafdar, Miriam Leeser |
The DT-Model: High-Level Synthesis Using Data Transfers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 35th Conference on Design Automation, Moscone center, San Francico, California, USA, June 15-19, 1998., pp. 114-117, 1998, ACM Press, 0-89791-964-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
high-level synthesis, telecommunication |
27 | Bengt Svantesson, Ahmed Hemani, Peeter Ellervee, Adam Postula, Johnny Öberg, Axel Jantsch, Hannu Tenhunen |
A Novell Allocation Strategy for Control and Memory Intensive Telecommunication Circiuts. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 9th International Conference on VLSI Design (VLSI Design 1996), 3-6 January 1996, Bangalore, India, pp. 23-28, 1996, IEEE Computer Society, 0-8186-7228-5. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
Application specific High-Level Synthesis, High-Level Synthesis for telecommunication, ATM |
27 | Preeti Ranjan Panda, Nikil D. Dutt |
1995 high level synthesis design repository. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSS ![In: Proceedings of the 8th International Symposium on System Synthesis (ISSS 1995), September 13-15, 1995, Cannes, France, pp. 170-174, 1995, ACM, 0-89791-771-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
1995 high level synthesis design repository, VHDL language, behavioral finite state machines, behavioral level, computational complexity, high level synthesis, finite state machines, VHDL, microprocessors, hardware description languages, microprocessor chips, floating point units |
26 | Jason Cong, Muhuan Huang, Yi Zou |
Accelerating Fluid Registration Algorithm on Multi-FPGA Platforms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: International Conference on Field Programmable Logic and Applications, FPL 2011, September 5-7, Chania, Crete, Greece, pp. 50-57, 2011, IEEE Computer Society, 978-1-4577-1484-9. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
fluid registration, FPGA, HLS |
26 | Hariharan Sankaran, Srinivas Katkoori |
Bus Binding, Re-ordering, and Encoding for Crosstalk-Producing Switching Activity Minimization during High Level Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008, Hong Kong, January 23-25, 2008, pp. 454-457, 2008, IEEE Computer Society, 978-0-7695-3110-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Simulated Annealing, HLS, Encoding, Crosstalk, Binding, Reordering |
26 | Mehrdad Reshadi, Bita Gorjiara, Daniel Gajski |
C-based design flow: a case study on G.729A for voice over internet protocol (VoIP). ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008, pp. 72-75, 2008, ACM, 978-1-60558-115-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
C-based design flow, C-to-RTL, G729A, NISC, HLS, VoIP, ASIP |
25 | Rosilde Corvino, Stéphane Mancini, Roberto Guizzetti |
Automatic generation of a parallel tile processing unit for algorithms with non-affine array references. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IFMT ![In: Proceedings of the 1st international forum on Next-generation multicore/manycore technologies, IFMT 2008, Cairo, Egypt, November 24-25, 2008, pp. 11, 2008, ACM, 978-1-60558-407-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
computations scheduling, design space exploration (DSE), non-affine array references, super-tiling, mapping, high-level synthesis (HLS), tiling |
25 | Chittaranjan A. Mandal, R. M. Zimmer |
A Genetic Algorithm for the Synthesis of Structured Data Paths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 13th International Conference on VLSI Design (VLSI Design 2000), 4-7 January 2000, Calcutta, India, pp. 206-211, 2000, IEEE Computer Society, 0-7695-0487-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Data Path Synthesis (DPS), Scheduling, High-Level Synthesis (HLS), Allocation |
18 | Rahul Chaurasia, Anirban Sengupta |
Multi-cut based architectural obfuscation and handprint biometric signature for securing transient fault detectable IP cores during HLS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 95, pp. 102114, March 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
18 | Sanshuang Jin, Yunkun Zhao, Ruizhe Wu, Fangfang Wu, Tianyu Zhou, Baogen Sun, Jigang Wang |
Two-Dimensional Visible Synchrotron Radiation Interferometry for Measuring Transverse Beam-Profile at HLS-II. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Instrum. Meas. Mag. ![In: IEEE Instrum. Meas. Mag. 27(1), pp. 37-42, February 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
18 | Hanchen Ye, David Z. Pan, Chris Leary, Deming Chen, Xiaoqing Xu |
Subgraph Extraction-based Feedback-guided Iterative Scheduling for HLS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2401.12343, 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
18 | Md Rubel Ahmed, Toshiaki Koike-Akino, Kieran Parsons, Ye Wang |
AutoHLS: Learning to Accelerate Design Space Exploration for HLS Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2403.10686, 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
18 | Louis-Noël Pouchet, Emily Tucker, Niansong Zhang, Hongzheng Chen, Debjit Pal, Gabriel Rodríguez 0001, Zhiru Zhang |
Formal Verification of Source-to-Source Transformations for HLS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the 2024 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2024, Monterey, CA, USA, March 3-5, 2024, pp. 97-107, 2024, ACM. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
18 | Daiki Furukawa, Taito Manabe, Yuichiro Shibata, Tomohiro Ueno, Kentaro Sano |
HLS Implementation of a Building Cube Stencil Computation Framework for an FPGA Accelerator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCE ![In: IEEE International Conference on Consumer Electronics, ICCE 2024, Las Vegas, NV, USA, January 6-8, 2024, pp. 1-6, 2024, IEEE, 979-8-3503-2413-6. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
18 | Haruto Ikehara, Taito Manabe, Yuichiro Shibata, Tomohiro Ueno, Kentaro Sano |
A Productive HLS Simulation Approach for Multi-FPGA Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCE ![In: IEEE International Conference on Consumer Electronics, ICCE 2024, Las Vegas, NV, USA, January 6-8, 2024, pp. 1-2, 2024, IEEE, 979-8-3503-2413-6. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
18 | Licheng Guo, Yuze Chi, Jason Lau, Linghao Song, Xingyu Tian, Moazin Khatti, Weikang Qiao, Jie Wang 0022, Ecenur Ustun, Zhenman Fang, Zhiru Zhang, Jason Cong |
TAPA: A Scalable Task-parallel Dataflow Programming Framework for Modern FPGAs with Co-optimization of HLS and Physical Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Reconfigurable Technol. Syst. ![In: ACM Trans. Reconfigurable Technol. Syst. 16(4), pp. 63:1-63:31, December 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
18 | Michael Guilherme Jordan, Bernardo Neuhaus Lignati, Guilherme Korol, Mateus Beck Rutzig, Antonio Carlos Schneider Beck |
MVSym: Efficient symbiotic exploitation of HLS-kernel multi-versioning for collaborative CPU-FPGA cloud systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 93, pp. 102052, November 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
18 | Lu Xiao, Zheng Xiao, Fan Wu, Yunchuan Qin, Kenli Li 0001 |
Optimization on operation sorting for HLS scheduling algorithms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 93, pp. 102058, November 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
18 | B. B. Shabarinath, Muralidhar Pullakandam |
SoC-based real-time SVM classification with integrated training using HLS and PYNQ. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microprocess. Microsystems ![In: Microprocess. Microsystems 101, pp. 104878, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
18 | Sayandip De, Muhammad Shafique 0001, Henk Corporaal |
Delay Prediction for ASIC HLS: Comparing Graph-Based and Nongraph-Based Learning Models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(4), pp. 1133-1146, April 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
18 | Nan Wu, Yuan Xie 0001, Cong Hao |
IronMan-Pro: Multiobjective Design Space Exploration in HLS via Reinforcement Learning and Graph Neural Network-Based Modeling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(3), pp. 900-913, March 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
18 | Zhe Lin, Tingyuan Liang, Jieru Zhao, Sharad Sinha, Wei Zhang 0012 |
HL-Pow: Learning-Assisted Pre-RTL Power Modeling and Optimization for FPGA HLS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(11), pp. 3925-3938, November 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|