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Publication years (Num. hits)
1981-1985 (15) 1986-1987 (36) 1988 (30) 1989 (33) 1990 (61) 1991 (45) 1992 (40) 1993 (41) 1994 (47) 1995 (51) 1996 (54) 1997 (42) 1998 (46) 1999 (32) 2000 (41) 2001 (34) 2002 (33) 2003 (53) 2004 (46) 2005 (63) 2006 (64) 2007 (63) 2008 (49) 2009 (36) 2010-2011 (23) 2012-2013 (24) 2014 (15) 2015 (18) 2016 (26) 2017 (31) 2018 (47) 2019 (97) 2020 (132) 2021 (177) 2022 (196) 2023 (310) 2024 (50)
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article(739) book(14) incollection(1) inproceedings(1418) phdthesis(29)
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Found 2201 publication records. Showing 2201 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
94Ciji Isen, Lizy K. John, Eugene John A Tale of Two Processors: Revisiting the RISC-CISC Debate. Search on Bibsonomy SPEC Benchmark Workshop The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
76Liwen Shih Microprogramming heritage of RISC design. Search on Bibsonomy MICRO The full citation details ... 1990 DBLP  BibTeX  RDF
73Krishna V. Palem, Barbara B. Simons Scheduling Time-Critical Instructions on RISC Machines. Search on Bibsonomy ACM Trans. Program. Lang. Syst. The full citation details ... 1993 DBLP  DOI  BibTeX  RDF RISC machine scheduling, NP-complete, latency, compiler optimization, register allocation, greedy algorithm, instruction scheduling, deadline, RISC, pipeline processor
69Michel J. Daydé, Iain S. Duff The RISC BLAS: a blocked implementation of level 3 BLAS for RISC processors. Search on Bibsonomy ACM Trans. Math. Softw. The full citation details ... 1999 DBLP  DOI  BibTeX  RDF matrix-matrix kernels, blocking, loop-unrolling, level 3 BLAS, RISC processors
58Marco Aurélio Cavalcanti Pacheco, Philip C. Treleaven A Risc Architecture to Support Neural Net Simulation. Search on Bibsonomy IWANN The full citation details ... 1993 DBLP  DOI  BibTeX  RDF
56Sung-Soo Lim, Young Hyun Bae, Gyu Tae Jang, Byung-Do Rhee, Sang Lyul Min, Chang Yun Park, Heonshik Shin, Kunsoo Park, Soo-Mook Moon, Chong-Sang Kim An Accurate Worst Case Timing Analysis for RISC Processors. Search on Bibsonomy IEEE Trans. Software Eng. The full citation details ... 1995 DBLP  DOI  BibTeX  RDF pipelined execution, real-time system, Cache memory, worst case execution time, RISC processor
54Farooq Butt Porting the mcc PowerPC C/C++ Compiler into an Interactive Development Environment. Search on Bibsonomy ACM SIGPLAN Notices The full citation details ... 1996 DBLP  DOI  BibTeX  RDF C++
54Charles D. Norton The International Workshop on Parallel C++ (IWPC++), Kanazawa, Ishikawa Prefecture, Japan. Search on Bibsonomy ACM SIGPLAN Notices The full citation details ... 1996 DBLP  DOI  BibTeX  RDF C++
49Sofiène Tahar, Ramayya Kumar Implementational Issues for Verifying RISC-Pipeline Conflicts in HOL. Search on Bibsonomy TPHOLs The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
47Ioannis Panagopoulos, Christos Pavlatos, George K. Papakonstantinou A hardware extension of the RISC microprocessor for Attribute Grammar evaluation. Search on Bibsonomy SAC The full citation details ... 2004 DBLP  DOI  BibTeX  RDF RISC microprocessors, Attribute Grammars, declarative programs
47Krishna V. Palem, Barbara B. Simons Scheduling Time-Critical Instructions on RISC Machines. Search on Bibsonomy POPL The full citation details ... 1990 DBLP  DOI  BibTeX  RDF RISC
47Margaret L. Simmons, Harvey J. Wasserman Performance evaluation of the IBM RISC System/6000: comparison of an optimized scalar processor with two vector processors. Search on Bibsonomy SC The full citation details ... 1990 DBLP  DOI  BibTeX  RDF RISC
47Christopher F. Clark The JADE interpreter: a RISC interpreter for syntax directed editing. Search on Bibsonomy PLDI The full citation details ... 1987 DBLP  DOI  BibTeX  RDF RISC
47Richard B. Kieburtz A RISC Architecture for Symbolic Computation. Search on Bibsonomy ASPLOS The full citation details ... 1987 DBLP  DOI  BibTeX  RDF RISC
45Nikolaos Kavvadias, Spiridon Nikolaidis 0001 Elimination of Overhead Operations in Complex Loop Structures for Embedded Microprocessors. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2008 DBLP  DOI  BibTeX  RDF Optimization, Microprocessors, Hardware description languages, Real-time and embedded systems, Pipeline processors, Control design
43Rishiyur S. Nikhil Can Dataflow Subsume von Neumann Computing? Search on Bibsonomy ISCA The full citation details ... 1989 DBLP  DOI  BibTeX  RDF RISC
42Bob Wilkinson, Lawrence S. Mulholland An Implementation of the BLAS on the i860: A RISC Approach to Software for RISC Devices. Search on Bibsonomy CONPAR The full citation details ... 1992 DBLP  DOI  BibTeX  RDF Fortran, linear algebra, RISC, BLAS, hierarchical memory
40Xiaoyong Chen, Douglas L. Maskell M2E: A Multiple-Input, Multiple-Output Function Extension for RISC-Based Extensible Processors. Search on Bibsonomy ARCS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
40Steffen Köhler, Jens Braunes, Thomas Preußer, Martin Zabel, Rainer G. Spallek Increasing ILP of RISC Microprocessors Through Control-Flow Based Reconfiguration. Search on Bibsonomy FPL The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
40Jiyang Kang, Jongbok Lee, Wonyong Sung A Compiler-Friendly RISC-Based Digital Signal Processor Synthesis and Performance Evaluation. Search on Bibsonomy J. VLSI Signal Process. The full citation details ... 2001 DBLP  DOI  BibTeX  RDF code converter, compiler-friendly, performance evaluation, digital signal processor, architecture synthesis
40Chris R. Jesshope, Bing Luo Micro-Threading: A New Approach to Future RISC. Search on Bibsonomy ACAC The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
40Edgar Holmann, Toyohiko Yoshida, Akira Yamada 0005, Shin-ichi Uramoto Single Chip Dual-Issue RISC Processor for Real-Time MPEG-2 Software Decoding. Search on Bibsonomy J. VLSI Signal Process. The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
40Olivier Maquelin, Herbert H. J. Hum, Guang R. Gao Costs and Benefits of Multithreading with Off-the-Shelf RISC Processors. Search on Bibsonomy Euro-Par The full citation details ... 1995 DBLP  DOI  BibTeX  RDF
40Kai Hwang 0001, Michel Dubois 0001, Dhabaleswar K. Panda 0001, S. Rao, Shisheng Shang, Aydin Üresin, W. Mao, H. Nair, M. Lytwyn, F. Hsieh, J. Liu, Sharad Mehrotra, Chien-Ming Cheng OMP: a RISC-based multiprocessor using orthogonal-access memories and multiple spanning buses. Search on Bibsonomy ICS The full citation details ... 1990 DBLP  DOI  BibTeX  RDF
38Erik Buchanan, Ryan Roemer, Hovav Shacham, Stefan Savage When good instructions go bad: generalizing return-oriented programming to RISC. Search on Bibsonomy CCS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF return-into-libc, return-oriented programming, RISC, SPARC
38Salah Merniz, Mohamed Benmohammed A Scalable Proof Methodology for RISC Processor Designs: A Functional Approach. Search on Bibsonomy ITNG The full citation details ... 2008 DBLP  DOI  BibTeX  RDF State functions, RISC designs, Formal Verification, Functional programming, Micro-architectures
38Yunquan Zhang, Ying Chen, Yuan Tang Block size selection of parallel LU and QR on PVP-based and RISC-based supercomputers. Search on Bibsonomy China HPC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF LU, PVP, optimal parallel block size, RISC, ScaLAPACK, QR
38Tsung-Han Tsai 0001, Ren-Jr Wu, Liang-Gee Chen A Cost-Effective Design for MPEG-2 Audio Decoder with Embedded RISC Core. Search on Bibsonomy J. VLSI Signal Process. The full citation details ... 2001 DBLP  DOI  BibTeX  RDF degrouping, synthesis filterbank, RISC, MPEG-2, multichannel
38Marco Antonio Dal Poz, Jose Edinson Aedo Cobo, Wilhelmus A. M. Van Noije, Marcelo Knörich Zuffo A Simple RISC Microprocessor Core Designed for Digital Set-Top-Box Applications. Search on Bibsonomy ASAP The full citation details ... 2000 DBLP  DOI  BibTeX  RDF FPGA, VHDL, Reconfigurable Computing, Microprocessor, MPEG, RISC, Co-Design, Instruction Set, HDTV, Set-Top-Box, iDCT, cable TV
38Valentina Salapura, Michael Gschwind Hardware/Software Co-Design of a Fuzzy RISC Processor. Search on Bibsonomy DATE The full citation details ... 1998 DBLP  DOI  BibTeX  RDF hardware/software co-evaluation, processor core, MIPS RISC processor, fuzzy processing, fuzzy rule evaluation, instruction set definition, performance evaluation, VHDL, logic synthesis, application specific instruction set processor (ASIP), hardware/software co-design, instruction set architecture, subword parallelism
38Zhen Guo, He Li, Shuling Guo, Dongsheng Wang Design and Simulation of a RISC-Based 32-bit Embedded On-Board Computer. Search on Bibsonomy Asian Test Symposium The full citation details ... 1998 DBLP  DOI  BibTeX  RDF Hardware/Software, Simulation, Design, Embedded System, EDA, RISC
38Kanad Ghose, Pavel Vasek A Fast Capability Extension to a RISC Architecture. Search on Bibsonomy EUROMICRO The full citation details ... 1996 DBLP  DOI  BibTeX  RDF fast capability extension, RISC architecture, capability-based addressing, capability-based machines, simulated executions, security, information sharing, reduced instruction set computing, performance penalty
38Kotaro Shimamura, Shigeya Tanaka, Tetsuya Shimomura, Takashi Hotta, Eiki Kamada, Hideo Sawamoto, Teruhisa Shimizu, Kisaburo Nakazawa A superscalar RISC processor with pseudo vector processing feature. Search on Bibsonomy ICCD The full citation details ... 1995 DBLP  DOI  BibTeX  RDF superscalar RISC processor, pseudo vector processing, architectural extension, floating-point registers, scoreboard-based dependency check, pipeline stage optimization, 267 MFLOPS, 1.2 Gbyte/s, performance evaluation, performance, computer architecture, memory access, reduced instruction set computing, vector processor systems
38Thomas Scholz, Michael Schäfers 0003 An improved dynamic register array concept for high-performance RISC processors. Search on Bibsonomy HICSS (1) The full citation details ... 1995 DBLP  DOI  BibTeX  RDF dynamic register array concept, high-performance RISC processors, processor registers, Multi Windows, Threaded Windows, dynamic register array, dynamic register allocation, general purpose registers, fast context switches, short interrupt latency, exception routines, real time systems, data structures, data structures, interrupts, storage allocation, external memory, registers, reduced instruction set computing
38Manuel L. Anido, David J. Allerton, Ed Zaluska A Three-Port/Three-Access Register File for Concurrent Processing and I/O Communication in a RISC-Like Graphics Engine. Search on Bibsonomy ISCA The full citation details ... 1989 DBLP  DOI  BibTeX  RDF Computer Image Generation, Computer Architecture, VLSI Design, Interprocessor Communication, RISC, Reduced Instruction Set Computers
38William R. Bush, A. Dain Samples, David M. Ungar, Paul N. Hilfinger Compiling Smalltalk-80 to a RISC. Search on Bibsonomy ASPLOS The full citation details ... 1987 DBLP  DOI  BibTeX  RDF RISC, Smalltalk-80
36Chien-Kuo V. Tien, Kelvin Lewis, Hans J. Greub, Tom Tsen, John F. McDonald 0001 Design of a 32 b monolithic microprocessor based on GaAs HMESFET technology. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
34Ioannis Panagopoulos, Christos Pavlatos, George K. Papakonstantinou An Embedded Microprocessor for Intelligent Control. Search on Bibsonomy J. Intell. Robotic Syst. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF embedded systems, logic programming, microprocessor, intelligent control, RISC, declarative programs
34Gaetano Borriello, Andrew R. Cherenson, Peter B. Danzig, Michael N. Nelson RISCs versus CISCs for Prolog: A Case Study. Search on Bibsonomy ASPLOS The full citation details ... 1987 DBLP  DOI  BibTeX  RDF Prolog, RISC, CISC
31Cheol-Hong Moon, Woo-Chun Jang Implementation of LED Array Color Temperature Controlled Lighting System Using RISC IP Core. Search on Bibsonomy ICIC (1) The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
31Josef Börcsök, Ali Hayek, Muhammad Umar Implementation of a 1oo2-RISC-architecture on FPGA for safety systems. Search on Bibsonomy AICCSA The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
31Xuehai Qian, He Huang, Hao Zhang 0009, Guoping Long, Junchao Zhang, Dongrui Fan Design and Implementation of Floating Point Stack on General RISC Architecture. Search on Bibsonomy PDP The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
31Rainer Ohlendorf, Thomas Wild, Michael Meitinger, Holm Rauchfuss, Andreas Herkersdorf Performance Evaluation of RISC-based SoC Platforms in Network Processing Applications. Search on Bibsonomy ICSAMOS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
31Kiyofumi Tanaka Casablanca II: Implementation of a Real-Time RISC. Search on Bibsonomy ASAP The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
31Tay-Jyi Lin, Chie-Min Chao, Chia-Hsien Liu, Pi-Chen Hsiao, Shin-Kai Chen, Li-Chun Lin, Chih-Wei Liu, Chein-Wei Jen A unified processor architecture for RISC & VLIW DSP. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2005 DBLP  DOI  BibTeX  RDF dual-core processor, register organization, variable-length instruction encoding, digital signal processor
31Sascha Wennekers, Christian Siemers Reconfigurable RISC - A New Approach for Space-Efficient Superscalar Microprocessor Architecture. Search on Bibsonomy ARCS The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
31Johann Großschädl Instruction Set Extension for Long Integer Modulo Arithmetic on RISC-Based Smart Cards. Search on Bibsonomy SBAC-PAD The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
31Marc Campbell Evaluating ASIC, DSP, and RISC Architectures for Embedded Applications. Search on Bibsonomy LCTES The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
31Ali Maamar, G. Russell A 32-Bit Risc Processor with Concurrent Error Detection. Search on Bibsonomy EUROMICRO The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
31V. J. Fazio, R. D. Pose Distributed Route Initialization Algorithms for the Monash Secure RISC Multiprocessor. Search on Bibsonomy HICSS (5) The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
31Luigi Carro, Altamiro Amadeu Susin A Risc Architecture to Explore HW/SW Parallelism in HW/SW Co-Design. Search on Bibsonomy ECBS The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
31Pedro Furtado 0001, Henrique Madeira Fault Injection Evaluation of Assigned Signatures in a RISC Processor. Search on Bibsonomy EDCC The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
31Rajiv Gupta 0001, Michael Epstein, Michael Whelan The design of a RISC based multiprocessor chip. Search on Bibsonomy SC The full citation details ... 1990 DBLP  DOI  BibTeX  RDF
31M. Castan, Elliott I. Organick µ3L: An HLL-RISC processor for parallel execution of FP-language programs. Search on Bibsonomy ISCA The full citation details ... 1982 DBLP  BibTeX  RDF FP
31David A. Patterson 0001, Richard S. Piepho RISC assessment: A high-level language experiment. Search on Bibsonomy ISCA The full citation details ... 1982 DBLP  BibTeX  RDF
29Hans Eberle Architektur moderner RISC-Mikroprozessoren. Search on Bibsonomy Inform. Spektrum The full citation details ... 1997 DBLP  DOI  BibTeX  RDF Mikroprozessoren, Pipelineverarbeitung, Cachespeicher, RISC
29Stephanie Dogimont, Martin Gumm, Friederich Mombers, Daniel Mlynek, Alessandro Torielli Conception and design of a RISC CPU for the use as embedded controller within a parallel multimedia architecture. Search on Bibsonomy ASAP The full citation details ... 1997 DBLP  DOI  BibTeX  RDF RISC CPU, parallel multimedia architecture, high performance control structure, parallel motion estimation architecture, MPEG2 coding, combined MIMD-SIMD approach, motion estimation, ASIP, subword parallelism, embedded controller
29Chia-Hsing Chien, Mark A. Franklin, Tienyo Pan, Prithvi Prabhu ARAS: asynchronous RISC architecture simulator. Search on Bibsonomy ASYNC The full citation details ... 1995 DBLP  DOI  BibTeX  RDF asynchronous RISC architecture simulator, ARAS, pipeline instruction simulator, benchmark programs, pipeline configuration, asynchronous pipeline architectures, performance evaluation, parallel architectures, virtual machines, performance measurements, pipeline processing
29John-David Wellman, Edward S. Davidson The resource conflict methodology for early-stage design space exploration of superscalar RISC processors. Search on Bibsonomy ICCD The full citation details ... 1995 DBLP  DOI  BibTeX  RDF resource conflict methodology, early-stage design space exploration, superscalar RISC processors, execution trace driven simulation, hardware element model, analysis program, performance evaluation, virtual machines, computer architecture, reduced instruction set computing, design cycle
29Ramayya Kumar, Sofiène Tahar Formal verification of pipeline conflicts in RISC processors. Search on Bibsonomy EURO-DAC The full citation details ... 1994 DBLP  DOI  BibTeX  RDF RISC
29Hidekazu Terai, Kazutoshi Gemma, Yohsuke Nagao, Yasuo Satoh, Yasuhiro Ohno Basic Concept of Cooperative Timing-driven Design Automation Technology for High-speed RISC Processor HARP-1. Search on Bibsonomy DAC The full citation details ... 1994 DBLP  DOI  BibTeX  RDF RISC
29David H. Bailey RISC microprocessors and scientific computing. Search on Bibsonomy SC The full citation details ... 1993 DBLP  DOI  BibTeX  RDF RISC, Intel i860
29John Wood, Harold C. Grossman Interprocedural register allocation for RISC machines. Search on Bibsonomy ACM Southeast Regional Conference The full citation details ... 1992 DBLP  DOI  BibTeX  RDF Interprocedural Register Allocation, RISC Computer, Webs, Graph Coloring
29Kristy Andrews, Duane Sand Migrating a CISC Computer Family onto RISC via Object Code Translation. Search on Bibsonomy ASPLOS The full citation details ... 1992 DBLP  DOI  BibTeX  RDF RISC, CISC
29C. Brian Hall, Kevin O'Brien Performance Characteristics of Architectural Features of the IBM RISC System/6000. Search on Bibsonomy ASPLOS The full citation details ... 1991 DBLP  DOI  BibTeX  RDF RISC, VAX
29Dileep Bhandarkar, Douglas W. Clark Performance From Architecture: Comparing a RISC and CISC with Similar Hardware Organization. Search on Bibsonomy ASPLOS The full citation details ... 1991 DBLP  DOI  BibTeX  RDF RISC, CISC
29Walter A. Helbig, Veljko M. Milutinovic A DCFL E/D-MESFET GaAs Experimental RISC Machine. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1989 DBLP  DOI  BibTeX  RDF RCA, DCFL E/D-MESFET, RISC machine, GaAs microprocessor, instruction execution sequence, III-V semiconductors, microprocessor chips, instruction set architecture, software environment, reduced instruction set computing, 32 bit, field effect integrated circuits, gallium arsenide
29Yashwant K. Malaiya, Sheng Feng Design of a testable RISC-to-CISC control architecture. Search on Bibsonomy MICRO The full citation details ... 1988 DBLP  BibTeX  RDF RISC
29Manuel Alfonseca 0001, David Selby APL2 - A RISC Business. Search on Bibsonomy APL The full citation details ... 1988 DBLP  DOI  BibTeX  RDF IBM System/370, APL, RISC, IBM PC
29Jack W. Davidson, Joseph V. Gresh Cint: a RISC interpreter for the C programming language. Search on Bibsonomy PLDI The full citation details ... 1987 DBLP  DOI  BibTeX  RDF C, RISC
29Yuval Tamir, Carlo H. Séquin Strategies for Managing the Register File in RISC. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1983 DBLP  DOI  BibTeX  RDF VLSI processor, Cache fetch strategies, register file management, computer architecture, RISC, procedure calls
27Wolfgang Windsteiger, Bruno Buchberger, Markus Rosenkranz Theorema. Search on Bibsonomy The Seventeen Provers of the World The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
27Fei Gao, Suleyman Sair Exploiting Intra-function Correlation with the Global History Stack. Search on Bibsonomy SAMOS The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
27Wayne Lyons Meeting the Embedded Design Needs of Automotive Applications. Search on Bibsonomy DATE The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
27V. Parthasarathy, S. Aram valartha Bharathi, V. Rhymend Uthariaraj Performance Analysis of Embedded Media Applications in Newer ARM Architectures. Search on Bibsonomy ICPP Workshops The full citation details ... 2005 DBLP  DOI  BibTeX  RDF ARM v6, DSP Extensions, Instruction set architecture (ISA), Single Instruction Multiple Data (SIMD)
27Shiliang Hu, James E. Smith 0001 Using Dynamic Binary Translation to Fuse Dependent Instructions. Search on Bibsonomy CGO The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
27Matías J. Garrido, César Sanz, Marcos Jiménez, Juan M. Meneses A Flexible H.263 Video Coder Prototype Based on FPGA. Search on Bibsonomy IEEE International Workshop on Rapid System Prototyping The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
27Rolf B. Hilgendorf, Wolfram Sauer Instruction translation for an experimental S/390 processor. Search on Bibsonomy SIGARCH Comput. Archit. News The full citation details ... 2001 DBLP  DOI  BibTeX  RDF IBM System/390
27Naehyuck Chang, Kwanho Kim, Hyung Gyu Lee Cycle-accurate energy consumption measurement and analysis: case study of ARM7TDMI. Search on Bibsonomy ISLPED The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
27Ryuichi Takahashi, Noriyoshi Yoshida Diagonal Examples for Design Space Exploration in an Educational Environment CITY-1. Search on Bibsonomy MSE The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
27Giuliano Donzellini, Stefano Nervi, Domenico Ponta, Sergio Rossi, Stefano Rovetta Object Oriented ARM7 Coprocessor. Search on Bibsonomy HICSS (3) The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
26Yao-Ming Kuo, Mark F. Flanagan, Francisco Garcia-Herrero, Oscar Ruano, Juan Antonio Maestro Integration of a Real-Time CCSDS 410.0-B-32 Error-Correction Decoder on FPGA-Based RISC-V SoCs Using RISC-V Vector Extension. Search on Bibsonomy IEEE Trans. Aerosp. Electron. Syst. The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
26Nick Brown 0001, Maurice Jamieson, Joseph K. L. Lee, Paul Wang Is RISC-V ready for HPC prime-time: Evaluating the 64-core Sophon SG2042 RISC-V CPU. Search on Bibsonomy CoRR The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
26Loïc Buckwell, Olivier Gilles, Daniel Gracia Pérez, Nikolai Kosmatov Execution at RISC: Stealth JOP Attacks on RISC-V Applications. Search on Bibsonomy CoRR The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
26Loïc Buckwell, Olivier Gilles, Daniel Gracia Pérez, Nikolai Kosmatov Execution at RISC: Stealth JOP Attacks on RISC-V Applications. Search on Bibsonomy ESORICS Workshops (2) The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
26Lukas Gerlach 0001, Daniel Weber 0007, Ruiyi Zhang, Michael Schwarz 0001 A Security RISC: Microarchitectural Attacks on Hardware RISC-V CPUs. Search on Bibsonomy SP The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
26Nick Brown 0002, Maurice Jamieson, Joseph K. L. Lee, Paul Wang Is RISC-V ready for HPC prime-time: Evaluating the 64-core Sophon SG2042 RISC-V CPU. Search on Bibsonomy SC Workshops The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
26Rieul Ducousso Sécurisation des accès aux périphériques et depuis les périphériques dans une architecture multicœur RISC-V utilisée pour la virtualisation. (Securing access to and from devices in a RISC-V multicore architecture used for virtualization). Search on Bibsonomy 2023   RDF
26Farhad Taheri, Siavash Bayat Sarmadi, Shahriar Hadayeghparast RISC-HD: Lightweight RISC-V Processor for Efficient Hyperdimensional Computing Inference. Search on Bibsonomy IEEE Internet Things J. The full citation details ... 2022 DBLP  DOI  BibTeX  RDF
26Olivier Gilles, Franck Viguier, Nikolai Kosmatov, Daniel Gracia Pérez Control-Flow Integrity at RISC: Attacking RISC-V by Jump-Oriented Programming. Search on Bibsonomy CoRR The full citation details ... 2022 DBLP  DOI  BibTeX  RDF
26Nils-Johan Wessman, Fabio Malatesta, Stefano Ribes, Jan Andersson, Antonio García-Vilanova, Miguel Masmano, Vicente Nicolau, Paco Gomez, Jimmy Le Rhun, Sergi Alcaide, Guillem Cabo, Francisco Bas, Pedro Benedicte, Fabio Mazzocchetti, Jaume Abella 0001 De-RISC: A Complete RISC-V Based Space-Grade Platform. Search on Bibsonomy DATE The full citation details ... 2022 DBLP  DOI  BibTeX  RDF
26Christopher Nitta, Aaron Kaloti, Shuotong Wang RISC-V Console: A Containerized RISC-V Based Game Console Emulator for Education. Search on Bibsonomy ITiCSE (1) The full citation details ... 2022 DBLP  DOI  BibTeX  RDF
26Marc Reichenbach, Johannes Knödtel, Sebastian Rachuj, Dietmar Fey RISC-V3: A RISC-V Compatible CPU With a Data Path Based on Redundant Number Systems. Search on Bibsonomy IEEE Access The full citation details ... 2021 DBLP  DOI  BibTeX  RDF
26Taoran Xiang, Lunkai Zhang, Shuqian An, Xiaochun Ye, Mingzhe Zhang, Yanhuan Liu, Mingyu Yan, Da Wang, Hao Zhang 0009, Wenming Li, Ninghui Sun, Dongrui Fan RISC-NN: Use RISC, NOT CISC as Neural Network Hardware Infrastructure. Search on Bibsonomy CoRR The full citation details ... 2021 DBLP  BibTeX  RDF
26Yu Liu, Kejiang Ye, Cheng-Zhong Xu 0001 Performance Evaluation of Various RISC Processor Systems: A Case Study on ARM, MIPS and RISC-V. Search on Bibsonomy CLOUD The full citation details ... 2021 DBLP  DOI  BibTeX  RDF
26Qiang Jiao, Wei Hu 0001, Fang Liu 0031, Yong Dong RISC-VTF: RISC-V Based Extended Instruction Set for Transformer. Search on Bibsonomy SMC The full citation details ... 2021 DBLP  DOI  BibTeX  RDF
26Karyofyllis Patsidis, Chrysostomos Nicopoulos, Georgios Ch. Sirakoulis, Giorgos Dimitrakopoulos RISC-V2: A Scalable RISC-V Vector Processor. Search on Bibsonomy ISCAS The full citation details ... 2020 DBLP  DOI  BibTeX  RDF
26Mark Akoev, Olga Moskaleva, Vladimir Pislyakov Confidence and RISC: How Russian papers indexed in the national citation database Russian Index of Science Citation (RISC) characterize universities and research institutes. Search on Bibsonomy CoRR The full citation details ... 2018 DBLP  BibTeX  RDF
26Christoph Baumhof, Frank Müller, Otto Müller, Manfred Schlett A novel 32 bit RISC architecture unifying RISC and DSP. Search on Bibsonomy ICASSP The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
26Ulrich Golze Der RISC-Prozessor TOOBSIE - Hintergrundband zum Buch "VLSI-Entwurf eines RISC-Prozessors" für den Entwurfsspezialisten. Search on Bibsonomy 1995   RDF
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