Search results for "High-Vt"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
8	Chris H. Kim, Jae-Joon Kim, Saibal Mukhopadhyay, Kaushik Roy 0001	A forward body-biased low-leakage SRAM cache: device and architecture considerations.	ISLPED	2003	DBLP DOI BibTeX RDF	forward body-biasing, super high VT, SRAM, leakage power
6	Meeta Srivastav, S. S. S. P. Rao, Himanshu Bhatnagar	Power Reduction Technique Using Multi-vt Libraries.	IWSOC	2005	DBLP DOI BibTeX RDF	High-Vt, Low-Vt, DFT, ASIC, Leakage power, DSM
5	Vivek De	Leakage-tolerant design techniques for high performance processors.	ISPD	2002	DBLP DOI BibTeX RDF
4	Amit Agarwal 0001, Kunhyuk Kang, Swarup Bhunia, James D. Gallagher, Kaushik Roy 0001	Device-Aware Yield-Centric Dual-Vt Design Under Parameter Variations in Nanoscale Technologies.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
3	Aditya Bansal, Jae-Joon Kim, Keunwoo Kim, Saibal Mukhopadhyay, Ching-Te Chuang, Kaushik Roy 0001	Optimal Dual-VT Design in Sub-100 Nanometer PDSOI and Double-Gate Technologies.	VLSI Design	2008	DBLP DOI BibTeX RDF
3	Ismael Seidel, Bruno George de Moraes, André Beims Bräscher, José Luís Güntzel	On the impacts of pel decimation and High-Vt/Low-Vdd on SAD calculation.	SBCCI	2013	DBLP DOI BibTeX RDF
2	Dongwoo Lee, David T. Blaauw, Dennis Sylvester	Runtime Leakage Minimization Through Probability-Aware Optimization.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
2	Akhilesh Kumar, Mohab Anis	Dual-Vt Design of FPGAs for Subthreshold Leakage Tolerance.	ISQED	2006	DBLP DOI BibTeX RDF
2	Dongwoo Lee, David T. Blaauw, Dennis Sylvester	Runtime leakage minimization through probability-aware dual-Vt or dual-tox assignment.	ASP-DAC	2005	DBLP DOI BibTeX RDF
2	Amit Agarwal 0001, Kunhyuk Kang, Swarup Bhunia, James D. Gallagher, Kaushik Roy 0001	Effectiveness of low power dual-Vt designs in nano-scale technologies under process parameter variations.	ISLPED	2005	DBLP DOI BibTeX RDF	process variation, yield, leakage, dual-Vt, metal gate
2	Jinseob Jeong, Seungwhun Paik, Youngsoo Shin	Statistical mixed Vt allocation of body-biased circuits for reduced leakage variation.	ASP-DAC	2008	DBLP DOI BibTeX RDF
2	Jaehyun Kim, Youngsoo Shin	Minimizing leakage power in sequential circuits by using mixed Vt flip-flops.	ICCAD	2007	DBLP DOI BibTeX RDF
2	Chris H. Kim, Jae-Joon Kim, Saibal Mukhopadhyay, Kaushik Roy 0001	A forward body-biased low-leakage SRAM cache: device, circuit and architecture considerations.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
2	Yu-Shiang Lin, Dennis Sylvester	A New Asymmetric Skewed Buffer Design for Runtime Leakage Power Reduction.	VLSI Design	2005	DBLP DOI BibTeX RDF
2	Fatih Hamzaoglu, Yibin Ye, Ali Keshavarzi, Kevin Zhang 0001, Siva G. Narendra, Shekhar Borkar, Mircea R. Stan, Vivek De	Analysis of dual-VT SRAM cells with full-swing single-ended bit line sensing for on-chip cache.	IEEE Trans. Very Large Scale Integr. Syst.	2002	DBLP DOI BibTeX RDF
2	Hiok-Tiaq Ng, David J. Allstot	CMOS current steering logic for low-voltage mixed-signal integrated circuits.	IEEE Trans. Very Large Scale Integr. Syst.	1997	DBLP DOI BibTeX RDF
1	Rouwaida Kanj, Rajiv V. Joshi, Jente B. Kuang, J. Kim, Mesut Meterelliyoz, William R. Reohr, Sani R. Nassif, Kevin J. Nowka	Statistical yield analysis of silicon-on-insulator embedded DRAM.	ISQED	2009	DBLP DOI BibTeX RDF
1	Sandeep Gupta, Jaya Singh, Abhijit Roy	A Novel Cell-Based Heuristic Method for Leakage Reduction in Multi-Million Gate VLSI Designs.	ISQED	2008	DBLP DOI BibTeX RDF	Dual-Vt Technology, Cell-Based Approach, Cell-swapping, Leakage Power
1	Akhilesh Kumar, Mohab Anis	Dual-Threshold CAD Framework for Subthreshold Leakage Power Aware FPGAs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
1	Mindaugas Drazdziulis, Per Larsson-Edefors, Lars J. Svensson	Overdrive Power-Gating Techniques for Total Power Minimization.	ISVLSI	2007	DBLP DOI BibTeX RDF
1	Jintae Kim, Ritesh Jhaveri, Jason Woo, Chih-Kong Ken Yang	Device-circuit co-optimization for mixed-mode circuit design via geometric programming.	ICCAD	2007	DBLP DOI BibTeX RDF
1	Yibin Ye, Muhammad M. Khellah, Dinesh Somasekhar, Vivek De	Evaluation of differential vs. single-ended sensing and asymmetric cells in 90 nm logic technology for on-chip caches.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Dongwoo Lee, Harmander Deogun, David T. Blaauw, Dennis Sylvester	Simultaneous State, Vt and Tox Assignment for Total Standby Power Minimization.	DATE	2004	DBLP DOI BibTeX RDF
1	Vijay Degalahal, Rajaraman Ramanarayanan, Narayanan Vijaykrishnan, Yuan Xie 0001, Mary Jane Irwin	The Effect of Threshold Voltages on the Soft Error Rate.	ISQED	2004	DBLP DOI BibTeX RDF
1	Dongwoo Lee, David T. Blaauw	Static leakage reduction through simultaneous threshold voltage and state assignment.	DAC	2003	DBLP DOI BibTeX RDF
1	Chris H. Kim, Kaushik Roy 0001	Dynamic Vt SRAM: a leakage tolerant cache memory for low voltage microprocessors.	ISLPED	2002	DBLP DOI BibTeX RDF
1	Debasis Samanta, Ajit Pal	Optimal Dual -VT Assignment for Low-Voltage Energy-Constrained CMOS Circuits.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF
1	Muhammad E. S. Elrabaa, Mohamed I. Elmasry	Split-Gate Logic circuits for multi-threshold technologies.	ISCAS (4)	2001	DBLP DOI BibTeX RDF