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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 22 occurrences of 20 keywords
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Results
Found 35 publication records. Showing 35 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
180 | Michael Cogswell, Don Pearl, James Sage, Alan Troidl |
An Automatic Validation Methodology for Logic BIST in High Performance VLSI Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, ICCD '00, Austin, Texas, USA, September 17-20, 2000, pp. 473-478, 2000, IEEE Computer Society, 0-7695-0801-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
145 | Diogo José Costa Alves, Edna Barros |
A logic built-in self-test architecture that reuses manufacturing compressed scan test patterns. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 22st Annual Symposium on Integrated Circuits and Systems Design: Chip on the Dunes, SBCCI 2009, Natal, Brazil, August 31 - September 3, 2009, 2009, ACM, 978-1-60558-705-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
LBIST, compressed test patterns, test, SoC, self-test |
78 | Paul Chang, Brion L. Keller, Sarala Paliwal |
Design and Implementation of a Parallel Weighted Random Pattern and Logic Built in Self Test Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings of the IEEE International Conference On Computer Design, VLSI in Computers and Processors, ICCD '99, Austin, Texas, USA, October 10-13, 1999, pp. 175-, 1999, IEEE Computer Society, 0-7695-0406-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
LBIST, WRPT, logic built in self test, weighted random pattern test, parallel processing, fault simulation |
59 | Michihiro Shintani, Tomoki Mino, Michiko Inoue |
LBIST-PUF: An LBIST Scheme Towards Efficient Challenge-Response Pairs Collection and Machine-Learning Attack Tolerance Improvement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ATS ![In: 29th IEEE Asian Test Symposium, ATS 2020, Penang, Malaysia, November 23-26, 2020, pp. 1-6, 2020, IEEE, 978-1-7281-7467-9. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
29 | Daniel Tille, Leon Klimasch, Sebastian Huhn 0001 |
A Novel LBIST Signature Computation Method for Automotive Microcontrollers using a Digital Twin. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 41st IEEE VLSI Test Symposium, VTS 2023, San Diego, CA, USA, April 24-26, 2023, pp. 1-6, 2023, IEEE, 979-8-3503-4630-5. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
29 | Bartosz Kaczmarek, Grzegorz Mrugalski, Nilanjan Mukherjee 0001, Artur Pogiel, Janusz Rajski, Lukasz Rybak 0001, Jerzy Tyszer |
LBIST for Automotive ICs With Enhanced Test Generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(7), pp. 2290-2300, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
29 | Umair Saeed Solangi, Muhammad Ibtesam, Sungju Park |
Time multiplexed LBIST for in-field testing of automotive AI accelerators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Electron. Express ![In: IEICE Electron. Express 18(24), pp. 20210451, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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29 | Christos Papameletis, Vivek Chickermane, Brian Foutz, Sarthak Singhal, Krishna Chakravadhanula |
Optimized Physical DFT Synthesis of Unified Compression and LBIST for Automotive Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: IEEE International Test Conference, ITC 2019, Washington, DC, USA, November 9-15, 2019, pp. 1-6, 2019, IEEE, 978-1-7281-4823-6. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
29 | Kashyap R. Adithya, S. Gayathri |
Study on LBIST and comparisons with ATPG. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICACCI ![In: 2018 International Conference on Advances in Computing, Communications and Informatics, ICACCI 2018, Bangalore, India, September 19-22, 2018, pp. 2131-2135, 2018, IEEE, 978-1-5386-5314-2. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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29 | Teresa L. McLaurin |
Periodic Online LBIST Considerations for a Multicore Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC-Asia ![In: IEEE International Test Conference in Asia, ITC-Asia 2018, Harbin, China, August 15-17, 2018, pp. 37-42, 2018, IEEE, 978-1-5386-5180-3. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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29 | Miao Tony He, Gustavo K. Contreras, Dat Tran, LeRoy Winemberg, Mark M. Tehranipoor |
Test-Point Insertion Efficiency Analysis for LBIST in High-Assurance Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 25(9), pp. 2602-2615, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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29 | Sylwester Milewski, Nilanjan Mukherjee 0001, Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer, Justyna Zawada |
Full-scan LBIST with capture-per-cycle hybrid test points. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: IEEE International Test Conference, ITC 2017, Fort Worth, TX, USA, October 31 - Nov. 2, 2017, pp. 1-9, 2017, IEEE, 978-1-5386-3413-4. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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29 | Miao Tony He, Gustavo K. Contreras, Mark M. Tehranipoor, Dat Tran, LeRoy Winemberg |
Test-point insertion efficiency analysis for LBIST applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 34th IEEE VLSI Test Symposium, VTS 2016, Las Vegas, NV, USA, April 25-27, 2016, pp. 1-6, 2016, IEEE Computer Society, 978-1-4673-8454-4. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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29 | Elham K. Moghaddam, Nilanjan Mukherjee 0001, Janusz Rajski, Jerzy Tyszer, Justyna Zawada |
Test point insertion in hybrid test compression/LBIST architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: 2016 IEEE International Test Conference, ITC 2016, Fort Worth, TX, USA, November 15-17, 2016, pp. 1-10, 2016, IEEE, 978-1-4673-8773-6. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
29 | Nan Li 0018, Elena Dubrova, Gunnar Carlsson |
A scan partitioning algorithm for reducing capture power of delay-fault LBIST. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, DATE 2015, Grenoble, France, March 9-13, 2015, pp. 842-847, 2015, ACM, 978-3-9815370-4-8. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP BibTeX RDF |
|
29 | Gustavo K. Contreras, Nisar Ahmed, LeRoy Winemberg, Mark M. Tehranipoor |
Predictive LBIST model and partial ATPG for seed extraction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFTS ![In: 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFTS 2015, Amherst, MA, USA, October 12-14, 2015, pp. 139-146, 2015, IEEE Computer Society, 978-1-4799-8606-4. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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29 | Gustavo K. Contreras, Yang Zhao, Nisar Ahmed, LeRoy Winemberg, Mohammad Tehranipoor |
LBIST pattern reduction by learning ATPG test cube properties. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: Sixteenth International Symposium on Quality Electronic Design, ISQED 2015, Santa Clara, CA, USA, March 2-4, 2015, pp. 147-153, 2015, IEEE, 978-1-4799-7581-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
29 | Nan Li 0018 |
Improvements in High-Coverage and Low-Power LBIST. ![Search on Bibsonomy](Pics/bibsonomy.png) |
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2015 |
RDF |
|
29 | Nan Li 0018, Elena Dubrova |
Area-efficient high-coverage LBIST. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microprocess. Microsystems ![In: Microprocess. Microsystems 38(5), pp. 368-374, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
29 | Elena Dubrova, Mats Näslund, Göran Selander |
Secure and efficient LBIST for feedback shift register-based cryptographic systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ETS ![In: 19th IEEE European Test Symposium, ETS 2014, Paderborn, Germany, May 26-30, 2014, pp. 1-6, 2014, IEEE, 978-1-4799-3415-7. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
29 | Sarvesh Prabhu, Vineeth V. Acharya, Sharad Bagri, Michael S. Hsiao |
Property-checking based LBIST for improved diagnosability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ETS ![In: 19th IEEE European Test Symposium, ETS 2014, Paderborn, Germany, May 26-30, 2014, pp. 1-2, 2014, IEEE, 978-1-4799-3415-7. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
29 | Nan Li 0018, Elena Dubrova, Gunnar Carlsson |
Evaluation of alternative LBIST flows: A case study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NORCHIP ![In: 2014 NORCHIP, Tampere, Finland, October 27-28, 2014, pp. 1-5, 2014, IEEE. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
29 | Sarvesh Prabhu, Vineeth V. Acharya, Sharad Bagri, Michael S. Hsiao |
A diagnosis-friendly LBIST architecture with property checking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: 2014 International Test Conference, ITC 2014, Seattle, WA, USA, October 20-23, 2014, pp. 1-9, 2014, IEEE Computer Society, 978-1-4799-4722-5. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
29 | Dale Meehl, Bassilios Petrakis, Ping Zhang |
LBIST/ATPG Technologies for On-Demand Digital Logic Testing in Automotive Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 21st IEEE Asian Test Symposium, ATS 2012, Niigata, Japan, November 19-22, 2012, pp. 2, 2012, IEEE Computer Society, 978-1-4673-4555-2. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
29 | Fei Zhuang, Junbo Jia, Xiangfeng Li |
System Level LBIST Implementation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ATS ![In: 17th IEEE Asian Test Symposium, ATS 2008, Sapporo, Japan, November 24-27, 2008, pp. 263, 2008, IEEE Computer Society, 978-0-7695-3396-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
29 | Jun Matsushima, Yoichi Maeda, Masahiro Takakura |
CooLBIST: An Effective Approach of Test Power Reduction for LBIST. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ATS ![In: 17th IEEE Asian Test Symposium, ATS 2008, Sapporo, Japan, November 24-27, 2008, pp. 264, 2008, IEEE Computer Society, 978-0-7695-3396-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
29 | Mary P. Kusko, Bryan J. Robbins, Timothy J. Koprowski, William V. Huott |
99% AC test coverage using only LBIST on the 1 GHz IBM S/390 zSeries 900 Microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October - 1 November 2001, pp. 586-592, 2001, IEEE Computer Society, 0-7803-7169-0. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
29 | Debaleena Das, Nur A. Touba |
Reducing test data volume using external/LBIST hybrid test patterns. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 2000, Atlantic City, NJ, USA, October 2000, pp. 115-122, 2000, IEEE Computer Society, 0-7803-6546-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
23 | Adrian E. Seigler, Gary A. Van Huben, Hari Mony |
Formal Verification of Partial Good Self-Test Fencing Structures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FMCAD ![In: Formal Methods in Computer-Aided Design, 7th International Conference, FMCAD 2007, Austin, Texas, USA, November 11-14, 2007, Proceedings, pp. 188-191, 2007, IEEE Computer Society, 0-7695-3023-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
fencing, formal verification, self test |
23 | Jiann-Chyi Rau, Po-Han Wu, Chia-Jung Liu |
A Novel Hardware Architecture for Low Power and Rapid Testing of VLSI Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems 2006, APCCAS 2006, Singapore, 4-7 December 2006, pp. 1883-1886, 2006, IEEE, 1-4244-0387-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
23 | Ethan Long, W. Robert Daasch, Robert Madge, Brady Benware |
Detection of Temperature Sensitive Defects Using ZTC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 22nd IEEE VLSI Test Symposium (VTS 2004), 25-29 April 2004, Napa Valley, CA, USA, pp. 185-192, 2004, IEEE Computer Society, 0-7695-2134-7. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
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23 | Valentin Gherman, Hans-Joachim Wunderlich, Harald P. E. Vranken, Friedrich Hapke, Michael Wittke, Michael Garbers |
Efficient Pattern Mapping for Deterministic Logic BIST. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2004 International Test Conference (ITC 2004), October 26-28, 2004, Charlotte, NC, USA, pp. 48-56, 2004, IEEE Computer Society, 0-7803-8581-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
BDDs, Logic BIST |
23 | Masao Naruse, Irith Pomeranz, Sudhakar M. Reddy, Sandip Kundu |
On-chip Compression of Output Responses with Unknown Values Using LFSR Reseeding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September - 3 October 2003, Charlotte, NC, USA, pp. 1060-1068, 2003, IEEE Computer Society, 0-7803-8106-8. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
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23 | Robert Bailey, A. Metayer, B. Svrcek, Nandu Tendolkar, E. Wolf, Eric Fiene, Mike Alexander, Rick Woltenberg, Rajesh Raina |
Test Methodology for Motorola's High Performance e500 Core Based on PowerPC Instruction Set Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 2002, Baltimore, MD, USA, October 7-10, 2002, pp. 574-583, 2002, IEEE Computer Society, 0-7803-7543-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
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23 | Paul Chang, Brion L. Keller, Sarala Paliwal |
Effective parallel processing techniques for the generation of test data for a logic built-in self test system. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, pp. 374-379, 2000, IEEE Computer Society, 0-7695-0887-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
logic built-in self test, complex processor, simulation time, random stimulus generation, signature computation, Pseudo-Random Pattern Generators, serial compression, response data, serial pattern dependency, parallel processing, parallel processing, logic testing, partitioning, built-in self test, integrated circuit testing, automatic test pattern generation, signatures, parallel simulation, microprocessor chips, logic simulation, logic simulation, post processing, logic partitioning, test data |
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