Search results for "LBIST"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
180	Michael Cogswell, Don Pearl, James Sage, Alan Troidl	An Automatic Validation Methodology for Logic BIST in High Performance VLSI Design.	ICCD	2000	DBLP DOI BibTeX RDF
145	Diogo José Costa Alves, Edna Barros	A logic built-in self-test architecture that reuses manufacturing compressed scan test patterns.	SBCCI	2009	DBLP DOI BibTeX RDF	LBIST, compressed test patterns, test, SoC, self-test
78	Paul Chang, Brion L. Keller, Sarala Paliwal	Design and Implementation of a Parallel Weighted Random Pattern and Logic Built in Self Test Algorithm.	ICCD	1999	DBLP DOI BibTeX RDF	LBIST, WRPT, logic built in self test, weighted random pattern test, parallel processing, fault simulation
59	Michihiro Shintani, Tomoki Mino, Michiko Inoue	LBIST-PUF: An LBIST Scheme Towards Efficient Challenge-Response Pairs Collection and Machine-Learning Attack Tolerance Improvement.	ATS	2020	DBLP DOI BibTeX RDF
29	Daniel Tille, Leon Klimasch, Sebastian Huhn 0001	A Novel LBIST Signature Computation Method for Automotive Microcontrollers using a Digital Twin.	VTS	2023	DBLP DOI BibTeX RDF
29	Bartosz Kaczmarek, Grzegorz Mrugalski, Nilanjan Mukherjee 0001, Artur Pogiel, Janusz Rajski, Lukasz Rybak 0001, Jerzy Tyszer	LBIST for Automotive ICs With Enhanced Test Generation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2022	DBLP DOI BibTeX RDF
29	Umair Saeed Solangi, Muhammad Ibtesam, Sungju Park	Time multiplexed LBIST for in-field testing of automotive AI accelerators.	IEICE Electron. Express	2021	DBLP DOI BibTeX RDF
29	Christos Papameletis, Vivek Chickermane, Brian Foutz, Sarthak Singhal, Krishna Chakravadhanula	Optimized Physical DFT Synthesis of Unified Compression and LBIST for Automotive Applications.	ITC	2019	DBLP DOI BibTeX RDF
29	Kashyap R. Adithya, S. Gayathri	Study on LBIST and comparisons with ATPG.	ICACCI	2018	DBLP DOI BibTeX RDF
29	Teresa L. McLaurin	Periodic Online LBIST Considerations for a Multicore Processor.	ITC-Asia	2018	DBLP DOI BibTeX RDF
29	Miao Tony He, Gustavo K. Contreras, Dat Tran, LeRoy Winemberg, Mark M. Tehranipoor	Test-Point Insertion Efficiency Analysis for LBIST in High-Assurance Applications.	IEEE Trans. Very Large Scale Integr. Syst.	2017	DBLP DOI BibTeX RDF
29	Sylwester Milewski, Nilanjan Mukherjee 0001, Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer, Justyna Zawada	Full-scan LBIST with capture-per-cycle hybrid test points.	ITC	2017	DBLP DOI BibTeX RDF
29	Miao Tony He, Gustavo K. Contreras, Mark M. Tehranipoor, Dat Tran, LeRoy Winemberg	Test-point insertion efficiency analysis for LBIST applications.	VTS	2016	DBLP DOI BibTeX RDF
29	Elham K. Moghaddam, Nilanjan Mukherjee 0001, Janusz Rajski, Jerzy Tyszer, Justyna Zawada	Test point insertion in hybrid test compression/LBIST architectures.	ITC	2016	DBLP DOI BibTeX RDF
29	Nan Li 0018, Elena Dubrova, Gunnar Carlsson	A scan partitioning algorithm for reducing capture power of delay-fault LBIST.	DATE	2015	DBLP BibTeX RDF
29	Gustavo K. Contreras, Nisar Ahmed, LeRoy Winemberg, Mark M. Tehranipoor	Predictive LBIST model and partial ATPG for seed extraction.	DFTS	2015	DBLP DOI BibTeX RDF
29	Gustavo K. Contreras, Yang Zhao, Nisar Ahmed, LeRoy Winemberg, Mohammad Tehranipoor	LBIST pattern reduction by learning ATPG test cube properties.	ISQED	2015	DBLP DOI BibTeX RDF
29	Nan Li 0018	Improvements in High-Coverage and Low-Power LBIST.		2015	RDF
29	Nan Li 0018, Elena Dubrova	Area-efficient high-coverage LBIST.	Microprocess. Microsystems	2014	DBLP DOI BibTeX RDF
29	Elena Dubrova, Mats Näslund, Göran Selander	Secure and efficient LBIST for feedback shift register-based cryptographic systems.	ETS	2014	DBLP DOI BibTeX RDF
29	Sarvesh Prabhu, Vineeth V. Acharya, Sharad Bagri, Michael S. Hsiao	Property-checking based LBIST for improved diagnosability.	ETS	2014	DBLP DOI BibTeX RDF
29	Nan Li 0018, Elena Dubrova, Gunnar Carlsson	Evaluation of alternative LBIST flows: A case study.	NORCHIP	2014	DBLP DOI BibTeX RDF
29	Sarvesh Prabhu, Vineeth V. Acharya, Sharad Bagri, Michael S. Hsiao	A diagnosis-friendly LBIST architecture with property checking.	ITC	2014	DBLP DOI BibTeX RDF
29	Dale Meehl, Bassilios Petrakis, Ping Zhang	LBIST/ATPG Technologies for On-Demand Digital Logic Testing in Automotive Circuits.	Asian Test Symposium	2012	DBLP DOI BibTeX RDF
29	Fei Zhuang, Junbo Jia, Xiangfeng Li	System Level LBIST Implementation.	ATS	2008	DBLP DOI BibTeX RDF
29	Jun Matsushima, Yoichi Maeda, Masahiro Takakura	CooLBIST: An Effective Approach of Test Power Reduction for LBIST.	ATS	2008	DBLP DOI BibTeX RDF
29	Mary P. Kusko, Bryan J. Robbins, Timothy J. Koprowski, William V. Huott	99% AC test coverage using only LBIST on the 1 GHz IBM S/390 zSeries 900 Microprocessor.	ITC	2001	DBLP DOI BibTeX RDF
29	Debaleena Das, Nur A. Touba	Reducing test data volume using external/LBIST hybrid test patterns.	ITC	2000	DBLP DOI BibTeX RDF
23	Adrian E. Seigler, Gary A. Van Huben, Hari Mony	Formal Verification of Partial Good Self-Test Fencing Structures.	FMCAD	2007	DBLP DOI BibTeX RDF	fencing, formal verification, self test
23	Jiann-Chyi Rau, Po-Han Wu, Chia-Jung Liu	A Novel Hardware Architecture for Low Power and Rapid Testing of VLSI Circuits.	APCCAS	2006	DBLP DOI BibTeX RDF
23	Ethan Long, W. Robert Daasch, Robert Madge, Brady Benware	Detection of Temperature Sensitive Defects Using ZTC.	VTS	2004	DBLP DOI BibTeX RDF
23	Valentin Gherman, Hans-Joachim Wunderlich, Harald P. E. Vranken, Friedrich Hapke, Michael Wittke, Michael Garbers	Efficient Pattern Mapping for Deterministic Logic BIST.	ITC	2004	DBLP DOI BibTeX RDF	BDDs, Logic BIST
23	Masao Naruse, Irith Pomeranz, Sudhakar M. Reddy, Sandip Kundu	On-chip Compression of Output Responses with Unknown Values Using LFSR Reseeding.	ITC	2003	DBLP DOI BibTeX RDF
23	Robert Bailey, A. Metayer, B. Svrcek, Nandu Tendolkar, E. Wolf, Eric Fiene, Mike Alexander, Rick Woltenberg, Rajesh Raina	Test Methodology for Motorola's High Performance e500 Core Based on PowerPC Instruction Set Architecture.	ITC	2002	DBLP DOI BibTeX RDF
23	Paul Chang, Brion L. Keller, Sarala Paliwal	Effective parallel processing techniques for the generation of test data for a logic built-in self test system.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	logic built-in self test, complex processor, simulation time, random stimulus generation, signature computation, Pseudo-Random Pattern Generators, serial compression, response data, serial pattern dependency, parallel processing, parallel processing, logic testing, partitioning, built-in self test, integrated circuit testing, automatic test pattern generation, signatures, parallel simulation, microprocessor chips, logic simulation, logic simulation, post processing, logic partitioning, test data