Search results for "Low-Vt"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
15	Mihir R. Choudhury, Masoud Rostami, Kartik Mohanram	Dominant critical gate identification for power and yield optimization in logic circuits.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	low-vt, process variations, yield
8	Vivek De	Leakage-tolerant design techniques for high performance processors.	ISPD	2002	DBLP DOI BibTeX RDF
8	Meeta Srivastav, S. S. S. P. Rao, Himanshu Bhatnagar	Power Reduction Technique Using Multi-vt Libraries.	IWSOC	2005	DBLP DOI BibTeX RDF	High-Vt, Low-Vt, DFT, ASIC, Leakage power, DSM
7	Khawar Sarfraz, Mansun Chan	A 65nm 3.2GHz 44.2mW Low-Vt register file with robust low-capacitance dynamic local bitlines.	ESSCIRC	2015	DBLP DOI BibTeX RDF
7	Seyfi S. Bazarjani, W. Martin Snelgrove	Low Voltage SC Circuit Design with Low-Vt MOSFETs.	ISCAS	1995	DBLP DOI BibTeX RDF
4	Jinseob Jeong, Seungwhun Paik, Youngsoo Shin	Statistical mixed Vt allocation of body-biased circuits for reduced leakage variation.	ASP-DAC	2008	DBLP DOI BibTeX RDF
4	Sherif A. Tawfik, Volkan Kursun	Work-function engineering for reduced power and higher integration density: An alternative to sizing for stability in FinFET memory circuits.	ISCAS	2008	DBLP DOI BibTeX RDF
4	Jaehyun Kim, Youngsoo Shin	Minimizing leakage power in sequential circuits by using mixed Vt flip-flops.	ICCAD	2007	DBLP DOI BibTeX RDF
4	Maryam Ashouei, Abhijit Chatterjee, Adit D. Singh, Vivek De	A Dual-Vt Layout Approach for Statistical Leakage Variability Minimization in Nanometer CMOS.	ICCD	2005	DBLP DOI BibTeX RDF
3	Satoru Akiyama, Riichiro Takemura, Tomonori Sekiguchi, Akira Kotabe, Kiyoo Itoh 0001	A Low-Vt Small-Offset Gated-Preamplifier for Sub-1-V DRAM Mid-Point Sensing.	IEICE Trans. Electron.	2012	DBLP DOI BibTeX RDF
3	Hagen Marien, Michiel Steyaert, Nick A. J. M. van Aerle, Paul Heremans	A mixed-signal organic 1kHz comparator with low VT sensitivity on flexible plastic substrate.	ESSCIRC	2009	DBLP DOI BibTeX RDF
3	Satoru Akiyama, Tomonori Sekiguchi, Riichiro Takemura, Akira Kotabe, Kiyoo Itoh 0001	Low-Vt small-offset gated preamplifier for sub-1V gigabit DRAM arrays.	ISSCC	2009	DBLP DOI BibTeX RDF
3	Thomas Baumann, Doris Schmitt-Landsiedel, Christian Pacha	Architectural assessment of design techniques to improve speed and robustness in embedded microprocessors.	DAC	2009	DBLP DOI BibTeX RDF	variability-aware design, robustness, micro-architecture
3	Amit Agarwal 0001, Kunhyuk Kang, Swarup Bhunia, James D. Gallagher, Kaushik Roy 0001	Device-Aware Yield-Centric Dual-Vt Design Under Parameter Variations in Nanoscale Technologies.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
3	Lin Yuan, Gang Qu 0001	Simultaneous input vector selection and dual threshold voltage assignment for static leakage minimization.	ICCAD	2007	DBLP DOI BibTeX RDF
3	Amit Agarwal 0001, Kunhyuk Kang, Swarup Bhunia, James D. Gallagher, Kaushik Roy 0001	Effectiveness of low power dual-Vt designs in nano-scale technologies under process parameter variations.	ISLPED	2005	DBLP DOI BibTeX RDF	process variation, yield, leakage, dual-Vt, metal gate
3	Arkadiy Morgenshtein, Israel Cidon, Ran Ginosar, Avinoam Kolodny	Low-leakage repeaters for NoC interconnects.	ISCAS (1)	2005	DBLP DOI BibTeX RDF
3	Qi Wang, Sarma B. K. Vrudhula	Algorithms for minimizing standby power in deep submicrometer, dual-Vt CMOS circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
3	Muhammad E. S. Elrabaa, Mohamed I. Elmasry	Split-Gate Logic circuits for multi-threshold technologies.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
3	S. Karthikeyan, A. Tammineedi, C. Boecker, Edward K. F. Lee	A 1 V front-end interface for switched-op amp circuits.	ISCAS (2)	1999	DBLP DOI BibTeX RDF
3	Hendrawan Soeleman, Dinesh Somasekhar, Kaushik Roy 0001	IDD Waveforms Analysis for Testing of Domino and Low Voltage Static CMOS Circuits.	Great Lakes Symposium on VLSI	1998	DBLP DOI BibTeX RDF	IDD Waveforms Analysis, Testing
3	Hiok-Tiaq Ng, David J. Allstot	CMOS current steering logic for low-voltage mixed-signal integrated circuits.	IEEE Trans. Very Large Scale Integr. Syst.	1997	DBLP DOI BibTeX RDF
1	David Bol, Dina Kamel, Denis Flandre, Jean-Didier Legat	Nanometer MOSFET effects on the minimum-energy point of 45nm subthreshold logic.	ISLPED	2009	DBLP DOI BibTeX RDF	short-channel effects, subthreshold logic, variability, cmos digital integrated circuits, ultra-low power, gate leakage
1	Rouwaida Kanj, Rajiv V. Joshi, Jente B. Kuang, J. Kim, Mesut Meterelliyoz, William R. Reohr, Sani R. Nassif, Kevin J. Nowka	Statistical yield analysis of silicon-on-insulator embedded DRAM.	ISQED	2009	DBLP DOI BibTeX RDF
1	Sandeep Gupta, Jaya Singh, Abhijit Roy	A Novel Cell-Based Heuristic Method for Leakage Reduction in Multi-Million Gate VLSI Designs.	ISQED	2008	DBLP DOI BibTeX RDF	Dual-Vt Technology, Cell-Based Approach, Cell-swapping, Leakage Power
1	Mindaugas Drazdziulis, Per Larsson-Edefors, Lars J. Svensson	Overdrive Power-Gating Techniques for Total Power Minimization.	ISVLSI	2007	DBLP DOI BibTeX RDF
1	Jintae Kim, Ritesh Jhaveri, Jason Woo, Chih-Kong Ken Yang	Device-circuit co-optimization for mixed-mode circuit design via geometric programming.	ICCAD	2007	DBLP DOI BibTeX RDF
1	Sorin P. Voinigescu, Sean T. Nicolson, Mehdi Khanpour, Keith K. W. Tang, Kenneth H. K. Yau, N. Seyedfathi, A. Timonov, A. Nachman, George V. Eleftheriades, Peter Schvan, Ming-Ta Yang	CMOS SOCs at 100 GHz: System Architectures, Device Characterization, and IC Design Examples.	ISCAS	2007	DBLP DOI BibTeX RDF
1	Yibin Ye, Muhammad M. Khellah, Dinesh Somasekhar, Vivek De	Evaluation of differential vs. single-ended sensing and asymmetric cells in 90 nm logic technology for on-chip caches.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Saumil Shah, Kanak Agarwal, Dennis Sylvester	A New Threshold Voltage Assignment Scheme for Runtime Leakage Reduction in On-Chip Repeaters.	ICCD	2004	DBLP DOI BibTeX RDF
1	Fatih Hamzaoglu, Yibin Ye, Ali Keshavarzi, Kevin Zhang 0001, Siva G. Narendra, Shekhar Borkar, Mircea R. Stan, Vivek De	Analysis of dual-VT SRAM cells with full-swing single-ended bit line sensing for on-chip cache.	IEEE Trans. Very Large Scale Integr. Syst.	2002	DBLP DOI BibTeX RDF
1	Mahesh Ketkar, Sachin S. Sapatnekar	Standby power optimization via transistor sizing and dual threshold voltage assignment.	ICCAD	2002	DBLP DOI BibTeX RDF
1	Debasis Samanta, Ajit Pal	Optimal Dual -VT Assignment for Low-Voltage Energy-Constrained CMOS Circuits.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF
1	Ali Keshavarzi, Kaushik Roy 0001, Charles F. Hawkins	Intrinsic leakage in deep submicron CMOS ICs-measurement-based test solutions.	IEEE Trans. Very Large Scale Integr. Syst.	2000	DBLP DOI BibTeX RDF