Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
91 | Chunho Lee, Miodrag Potkonjak, William H. Mangione-Smith |
MediaBench: A Tool for Evaluating and Synthesizing Multimedia and Communicatons Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the Thirtieth Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 30, Research Triangle Park, North Carolina, USA, December 1-3, 1997, pp. 330-335, 1997, ACM/IEEE Computer Society, 0-8186-7977-8. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
MediaBench, SPEC benchmark suite, benchmark suite, compilation technology, experimental measurement, general-purpose computing, general-purpose systems, inner-loops, optimization, multimedia systems, instruction-level parallelism, SIMD, VLIW, communications systems, embedded applications, microprocessor architectures |
42 | Jason E. Fritts, Frederick W. Steiling, Joseph A. Tucek, Wayne H. Wolf |
MediaBench II video: Expediting the next generation of video systems research. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microprocess. Microsystems ![In: Microprocess. Microsystems 33(4), pp. 301-318, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
25 | Gokhan Memik, William H. Mangione-Smith |
Evaluating Network Processors using NetBench. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Embed. Comput. Syst. ![In: ACM Trans. Embed. Comput. Syst. 5(2), pp. 453-471, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Embedded systems, benchmarking, network processors |
25 | Ricardo Santos 0002, Rodolfo Azevedo, Guido Araujo |
2D-VLIW: An Architecture Based on the Geometry of Computation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 2006 IEEE International Conference on Application-Specific Systems, Architecture and Processors (ASAP 2006), 11-13 September 2006, Steamboat Springs, Colorado, USA, pp. 87-94, 2006, IEEE Computer Society, 0-7695-2682-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
25 | Jiangjiang Liu 0002, Brian Bell, Tan Truong |
Analysis and Characterization of Intel Itanium Instruction Bundles for Improving VLIW Processor Performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IMSCCS (1) ![In: Interdisciplinary and Multidisciplinary Research in Computer Science, IEEE CS Proceeding of the First International Multi-Symposium of Computer and Computational Sciences (IMSCCS|06), June 20-24, 2006, Zhejiang University, Hangzhou, China, Vol. 1, pp. 389-396, 2006, IEEE Computer Society, 0-7695-2581-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
25 | David M. Brooks, Margaret Martonosi |
Value-based clock gating and operation packing: dynamic strategies for improving processor power and performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Comput. Syst. ![In: ACM Trans. Comput. Syst. 18(2), pp. 89-126, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
25 | David M. Brooks, Margaret Martonosi |
Dynamically Exploiting Narrow Width Operands to Improve Processor Power and Performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: Proceedings of the Fifth International Symposium on High-Performance Computer Architecture, Orlando, FL, USA, January 9-12, 1999, pp. 13-22, 1999, IEEE Computer Society, 0-7695-0004-8. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
12 | Silvian Calman, Jianwen Zhu |
Interprocedural induction variable analysis based on interprocedural SSA form IR. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PASTE ![In: Proceedings of the 9th ACM SIGPLAN-SIGSOFT Workshop on Program Analysis for Software Tools and Engineering, PASTE'10, Toronto, Ontario, Canada, June 5-6, 2010, pp. 37-44, 2010, ACM, 978-1-4503-0082-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
induction variable analysis, interprocedural ssa, ssa |
12 | Mohammad Shihabul Haque, Jorgen Peddersen, Andhi Janapsatya, Sri Parameswaran |
SCUD: a fast single-pass L1 cache simulation approach for embedded processors with round-robin replacement policy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 47th Design Automation Conference, DAC 2010, Anaheim, California, USA, July 13-18, 2010, pp. 356-361, 2010, ACM, 978-1-4503-0002-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
miss rate, simulation, round robin, cache simulation, L1 cache |
12 | Dominique Chanet, Javier Cabezas, Enric Morancho, Nacho Navarro, Koen De Bosschere |
Linux Kernel Compaction through Cold Code Swapping. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Trans. High Perform. Embed. Archit. Compil. ![In: Transactions on High-Performance Embedded Architectures and Compilers II, pp. 173-200, 2009, Springer, 978-3-642-00903-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
12 | Lian Li 0002, Hui Feng, Jingling Xue |
Compiler-directed scratchpad memory management via graph coloring. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Archit. Code Optim. ![In: ACM Trans. Archit. Code Optim. 6(3), pp. 9:1-9:17, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
live range splitting, memory coloring, graph coloring, memory allocation, Scratchpad memory, register coalescing, software-managed cache |
12 | Tyrel Russell, Abid M. Malik, Michael Chase, Peter van Beek |
Learning Heuristics for the Superblock Instruction Scheduling Problem. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Knowl. Data Eng. ![In: IEEE Trans. Knowl. Data Eng. 21(10), pp. 1489-1502, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
12 | Anca Mariana Molnos, Sorin Cotofana, Marc J. M. Heijligers, Jos T. J. van Eijndhoven |
Compositional, Dynamic Cache Management for Embedded Chip Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Signal Process. Syst. ![In: J. Signal Process. Syst. 57(2), pp. 155-172, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Predictability, Multiprocessor, Compositionality, Cache management |
12 | Kevin J. M. Martin, Christophe Wolinski, Krzysztof Kuchcinski, Antoine Floch, François Charot |
Constraint-Driven Identification of Application Specific Instructions in the DURASE System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAMOS ![In: Embedded Computer Systems: Architectures, Modeling, and Simulation, 9th International Workshop, SAMOS 2009, Samos, Greece, July 20-23, 2009. Proceedings, pp. 194-203, 2009, Springer, 978-3-642-03137-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
12 | Samir Ammenouche, Sid Ahmed Ali Touati, William Jalby |
On Instruction-Level Method for Reducing Cache Penalties in Embedded VLIW Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCC ![In: 11th IEEE International Conference on High Performance Computing and Communications, HPCC 2009, 25-27 June 2009, Seoul, Korea, pp. 196-205, 2009, IEEE, 978-0-7695-3738-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
12 | Yanqin Yang, Meng Wang 0005, Zili Shao, Minyi Guo |
Dynamic Scratch-Pad Memory Management with Data Pipelining for Embedded Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CSE (2) ![In: Proceedings of the 12th IEEE International Conference on Computational Science and Engineering, CSE 2009, Vancouver, BC, Canada, August 29-31, 2009, pp. 358-365, 2009, IEEE Computer Society, 978-1-4244-5334-4. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
12 | Silvian Calman, Jianwen Zhu |
Increasing the Scope and Resolution of Interprocedural Static Single Assignment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAS ![In: Static Analysis, 16th International Symposium, SAS 2009, Los Angeles, CA, USA, August 9-11, 2009. Proceedings, pp. 154-170, 2009, Springer, 978-3-642-03236-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
dataflow, constant propagation, SSA, interprocedural |
12 | Kapil Anand, Rajeev Barua |
Instruction cache locking inside a binary rewriter. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2009 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2009, Grenoble, France, October 11-16, 2009, pp. 185-194, 2009, ACM. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
cache locking, embedded systems, caches, binary rewriting |
12 | Jie Tao 0001, Dominic Hillenbrand, Holger Marten |
Instruction Hints for Super Efficient Data Caches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCS (2) ![In: Computational Science - ICCS 2009, 9th International Conference, Baton Rouge, LA, USA, May 25-27, 2009, Proceedings, Part II, pp. 677-685, 2009, Springer, 978-3-642-01972-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
simulation, architecture design, Cache optimization |
12 | Ozcan Ozturk 0001, Mahmut T. Kandemir, Guangyu Chen |
Access pattern-based code compression for memory-constrained systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 13(4), pp. 60:1-60:30, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
CFG, code access pattern, Embedded systems, code compression, memory optimization |
12 | Shu Xiao 0001, Edmund Ming-Kit Lai |
A Rough Programming Approach to Power-Balanced Instruction Scheduling for VLIW Digital Signal Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Signal Process. ![In: IEEE Trans. Signal Process. 56(4), pp. 1698-1709, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
12 | Sanghyun Park, Aviral Shrivastava, Yunheung Paek |
Hiding Cache Miss Penalty Using Priority-based Execution for Embedded Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2008, Munich, Germany, March 10-14, 2008, pp. 1190-1195, 2008, ACM, 978-3-9810801-3-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
12 | Anca Mariana Molnos, Marc J. M. Heijligers, Sorin Dan Cotofana |
Compositional, dynamic cache management for embedded chip multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2008, Munich, Germany, March 10-14, 2008, pp. 991-996, 2008, ACM, 978-3-9810801-3-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
12 | Mattias V. Eriksson, Oskar Skoog, Christoph W. Kessler |
Optimal vs. heuristic integrated code generation for clustered VLIW architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SCOPES ![In: Proceedings of the 11th International Workshop on Software and Compilers for Embedded Systems, Munich, Germany, March 13-14, 2008, pp. 11-20, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
12 | Kenneth Hoste, Lieven Eeckhout |
Characterizing the Unique and Diverse Behaviors in Existing and Emerging General-Purpose and Domain-Specific Benchmark Suites. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPASS ![In: IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS 2008, April 20-22, 2008, Austin, Texas, USA, Proceedings, pp. 157-168, 2008, IEEE Computer Society, 978-1-4244-2232-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
12 | Yanqin Yang, Zili Shao, Linfeng Pan, Minyi Guo |
ISOS: Space Overlapping Based on Iteration Access Patterns for Dynamic Scratch-pad Memory Management in Embedded Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICYCS ![In: Proceedings of the 9th International Conference for Young Computer Scientists, ICYCS 2008, Zhang Jia Jie, Hunan, China, November 18-21, 2008, pp. 1360-1366, 2008, IEEE Computer Society, 978-0-7695-3398-8. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
12 | Talal Bonny, Jörg Henkel |
FBT: filled buffer technique to reduce code size for VLIW processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2008 International Conference on Computer-Aided Design, ICCAD 2008, San Jose, CA, USA, November 10-13, 2008, pp. 549-554, 2008, IEEE Computer Society, 978-1-4244-2820-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
12 | Mohammad Ali Ghodrat, Tony Givargis, Alex Nicolau |
Control flow optimization in loops using interval analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2008 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2008, Atlanta, GA, USA, October 19-24, 2008, pp. 157-166, 2008, ACM. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
algorithmic code transformation, compiler loop optimization, interval analysis |
12 | Arun Rangasamy, Rahul Nagpal, Y. N. Srikant |
Compiler-directed frequency and voltage scaling for a multiple clock domain microarchitecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Conf. Computing Frontiers ![In: Proceedings of the 5th Conference on Computing Frontiers, 2008, Ischia, Italy, May 5-7, 2008, pp. 209-218, 2008, ACM, 978-1-60558-077-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
dvs, dynamic energy, energy, multiple clock domains |
12 | Allen C. Cheng |
Amplifying Embedded System Efficiency via Automatic Instruction Fusion on a Post-Manufacturing Reconfigurable Architecture Platform. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 9th International Symposium on Quality of Electronic Design (ISQED 2008), 17-19 March 2008, San Jose, CA, USA, pp. 744-749, 2008, IEEE Computer Society, 978-0-7695-3117-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
12 | Shlomit S. Pinter, Israel Waldman |
Selective Code Compression Scheme for Embedded Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Trans. High Perform. Embed. Archit. Compil. ![In: Transactions on High-Performance Embedded Architectures and Compilers I, pp. 298-316, 2007, Springer, 978-3-540-71527-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
run-time decompression, Code compression, code size reduction |
12 | Ja Chun Ku, Serkan Ozdemir, Gokhan Memik, Yehea I. Ismail |
Thermal Management of On-Chip Caches Through Power Density Minimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 15(5), pp. 592-604, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
12 | Shao-Yang Wang, Rong-Guey Chang |
Code size reduction by compressing repeated instruction sequences. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Supercomput. ![In: J. Supercomput. 40(3), pp. 319-331, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Repeated instruction sequence, Index table, Instruction table, Register bank, Code compression, Decompression, Instruction prefetching |
12 | Love Singhal, Elaheh Bozorgzadeh, David Eppstein |
Interconnect Criticality-Driven Delay Relaxation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(10), pp. 1803-1817, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
12 | Shu Xiao 0001, Edmund Ming-Kit Lai |
VLIW instruction scheduling for minimal power variation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Archit. Code Optim. ![In: ACM Trans. Archit. Code Optim. 4(3), pp. 18, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
power variation reduction, Instruction scheduling, VLIW processors |
12 | Peter G. Sassone, D. Scott Wills, Gabriel H. Loh |
Static strands: Safely exposing dependence chains for increasing embedded power efficiency. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Embed. Comput. Syst. ![In: ACM Trans. Embed. Comput. Syst. 6(4), pp. 24, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
dependency collapsing, Architecture, energy, sequentiality |
12 | Guangyu Chen, Feihui Li, Mahmut T. Kandemir |
Reducing Energy Consumption of On-Chip Networks Through a Hybrid Compiler-Runtime Approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PACT ![In: 16th International Conference on Parallel Architectures and Compilation Techniques (PACT 2007), Brasov, Romania, September 15-19, 2007, pp. 163-174, 2007, IEEE Computer Society, 0-7695-2944-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
12 | Zhiguo Ge, Weng-Fai Wong, Hock-Beng Lim |
DRIM: a low power dynamically reconfigurable instruction memory hierarchy for embedded systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2007 Design, Automation and Test in Europe Conference and Exposition, DATE 2007, Nice, France, April 16-20, 2007, pp. 1343-1348, 2007, EDA Consortium, San Jose, CA, USA, 978-3-9810801-2-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
12 | Seok-Won Seong, Prabhat Mishra 0001 |
An efficient code compression technique using application-aware bitmask and dictionary selection methods. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2007 Design, Automation and Test in Europe Conference and Exposition, DATE 2007, Nice, France, April 16-20, 2007, pp. 582-587, 2007, EDA Consortium, San Jose, CA, USA, 978-3-9810801-2-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
12 | Yee Jern Chong, Sri Parameswaran |
Automatic application specific floating-point unit generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2007 Design, Automation and Test in Europe Conference and Exposition, DATE 2007, Nice, France, April 16-20, 2007, pp. 461-466, 2007, EDA Consortium, San Jose, CA, USA, 978-3-9810801-2-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
12 | Andhi Janapsatya, Aleksandar Ignjatovic, Sri Parameswaran, Jörg Henkel |
Instruction trace compression for rapid instruction cache simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2007 Design, Automation and Test in Europe Conference and Exposition, DATE 2007, Nice, France, April 16-20, 2007, pp. 803-808, 2007, EDA Consortium, San Jose, CA, USA, 978-3-9810801-2-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
12 | Josep M. Codina, F. Jesús Sánchez, Antonio González 0001 |
Virtual Cluster Scheduling Through the Scheduling Graph. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CGO ![In: Fifth International Symposium on Code Generation and Optimization (CGO 2007), 11-14 March 2007, San Jose, California, USA, pp. 89-101, 2007, IEEE Computer Society, 978-0-7695-2764-2. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
12 | Mohammad Ali Ghodrat, Tony Givargis, Alex Nicolau |
Short-Circuit Compiler Transformation: Optimizing Conditional Blocks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 12th Conference on Asia South Pacific Design Automation, ASP-DAC 2007, Yokohama, Japan, January 23-26, 2007, pp. 504-510, 2007, IEEE Computer Society, 1-4244-0629-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
12 | Xianhua Liu 0001, Jiyu Zhang, Xu Cheng 0001 |
NISD: A Framework for Automatic Narrow Instruction Set Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICESS ![In: Embedded Software and Systems, [Third] International Conference, ICESS 2007, Daegu, Korea, May 14-16, 2007, Proceedings, pp. 271-282, 2007, Springer, 978-3-540-72684-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
dual-width instruction set, narrow instruction set design, automatic instruction set design |
12 | Seunghoon Kim, Robert P. Dick, Russ Joseph |
Power deregulation: eliminating off-chip voltage regulation circuitry from embedded systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2007, Salzburg, Austria, September 30 - October 3, 2007, pp. 105-110, 2007, ACM, 978-1-59593-824-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
power regulation, multimedia, chip multiprocessor, battery |
12 | Haifeng He, Saumya K. Debray, Gregory R. Andrews |
The revenge of the overlay: automatic compaction of OS kernel code via on-demand code loading. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EMSOFT ![In: Proceedings of the 7th ACM & IEEE International conference on Embedded software, EMSOFT 2007, September 30 - October 3, 2007, Salzburg, Austria, pp. 75-83, 2007, ACM, 978-1-59593-825-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
code clustering, embedded systems, code compaction, binary rewriting |
12 | Je-Hyung Lee, Jinpyo Park, Soo-Mook Moon |
Securing More Registers with Reduced Instruction Encoding Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RTCSA ![In: 13th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2007), 21-24 August 2007, Daegu, Korea, pp. 417-425, 2007, IEEE Computer Society, 0-7695-2975-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
12 | Lian Li 0002, Hui Wu 0001, Hui Feng, Jingling Xue |
Towards Data Tiling for Whole Programs in Scratchpad Memory Allocation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asia-Pacific Computer Systems Architecture Conference ![In: Advances in Computer Systems Architecture, 12th Asia-Pacific Conference, ACSAC 2007, Seoul, Korea, August 23-25, 2007, Proceedings, pp. 63-74, 2007, Springer, 978-3-540-74308-8. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
12 | Philip Brisk, Ajay Kumar Verma, Paolo Ienne |
An optimistic and conservative register assignment heuristic for chordal graphs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2007 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2007, Salzburg, Austria, September 30 - October 3, 2007, pp. 209-217, 2007, ACM. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
static single assignment (ssa) form, chordal graph, register assignment |
12 | André Silva, Guilherme Álvaro R. M. Esmeraldo, Edna Barros, Pablo Viana |
Cache-Analyzer: Design Space Evaluation of Configurable-Caches in a Single-Pass. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE International Workshop on Rapid System Prototyping ![In: 18th IEEE International Workshop on Rapid System Prototyping (RSP 2007), 28-30 May 2007, Porto Alegre, RS, Brazil, pp. 3-9, 2007, IEEE Computer Society, 978-0-7695-2834-2. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
12 | Kimish Patel, Wonbok Lee, Massoud Pedram |
Minimizing power dissipation during write operation to register files. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007, Portland, OR, USA, August 27-29, 2007, pp. 183-188, 2007, ACM, 978-1-59593-709-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
write operation, power, register file |
12 | Christophe Wolinski, Krzysztof Kuchcinski |
Identification of Application Specific Instructions Based on Sub-Graph Isomorphism Constraints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: IEEE International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2007, Montréal, Québec, Canada, July 8-11, 2007, pp. 328-333, 2007, IEEE Computer Society, 978-1-4244-1026-2. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
12 | Eduardo Braulio Wanderley Netto, Romain Vaslin, Guy Gogniat, Jean-Philippe Diguet |
A Code Compression Method to Cope with Security Hardware Overheads. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBAC-PAD ![In: 19th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2007), 24-27 October 2007, Gramado, RS, Brazil, pp. 185-192, 2007, IEEE Computer Society, 0-7695-3014-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
12 | Neeraj Goel, Anshul Kumar, Preeti Ranjan Panda |
Power Reduction in VLIW Processor with Compiler Driven Bypass Network. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 20th International Conference on VLSI Design (VLSI Design 2007), Sixth International Conference on Embedded Systems (ICES 2007), 6-10 January 2007, Bangalore, India, pp. 233-238, 2007, IEEE Computer Society, 0-7695-2762-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
12 | Andrew D. Hilton, Amir Roth |
Ginger: control independence using tag rewriting. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 34th International Symposium on Computer Architecture (ISCA 2007), June 9-13, 2007, San Diego, California, USA, pp. 436-447, 2007, ACM, 978-1-59593-706-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
control independence, out-of-order renaming, selective re-dispatch, branch misprediction |
12 | Soheil Ghiasi, Po-Kuan Huang, Roozbeh Jafari |
Probabilistic delay budget assignment for synthesis of soft real-time applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 14(8), pp. 843-853, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
12 | Partha Biswas, Sudarshan Banerjee, Nikil D. Dutt, Laura Pozzi, Paolo Ienne |
ISEGEN: an iterative improvement-based ISE generation technique for fast customization of processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 14(7), pp. 754-762, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
12 | Praveen Kalla, Xiaobo Sharon Hu, Jörg Henkel |
Distance-based recent use (DRU): an enhancement to instruction cache replacement policies for transition energy reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 14(1), pp. 69-80, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
12 | Ajay Joshi, Aashish Phansalkar, Lieven Eeckhout, Lizy Kurian John |
Measuring Benchmark Similarity Using Inherent Program Characteristics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 55(6), pp. 769-782, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
modeling techniques, performance of systems, Measurement techniques, performance attributes |
12 | Olivier Rochecouste, Gilles Pokam, André Seznec |
A case for a complexity-effective, width-partitioned microarchitecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Archit. Code Optim. ![In: ACM Trans. Archit. Code Optim. 3(3), pp. 295-326, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Power analysis |
12 | Desiree Ottoni, Guilherme Ottoni, Guido Araujo, Rainer Leupers |
Offset assignment using simultaneous variable coalescing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Embed. Comput. Syst. ![In: ACM Trans. Embed. Comput. Syst. 5(4), pp. 864-883, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Stack offset assignment, address registers, autoincrement addressing modes, variable coalescing, DSPs, register allocation |
12 | Kashif Ali, Mokhtar Aboelaze, Suprakash Datta |
Modified Hotspot Cache Architecture: A Low Energy Fast Cache for Embedded Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICSAMOS ![In: Proceedings of 2006 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (IC-SAMOS 2006), Samos, Greece, July 17-20, 2006, pp. 35-42, 2006, IEEE, 1-4244-0155-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
12 | Masayo Haneda, Peter M. W. Knijnenburg, Harry A. G. Wijshoff |
Code Size Reduction by Compiler Tuning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAMOS ![In: Embedded Computer Systems: Architectures, Modeling, and Simulation, 6th International Workshop, SAMOS 2006, Samos, Greece, July 17-20, 2006, Proceedings, pp. 186-195, 2006, Springer, 3-540-36410-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
12 | Andhi Janapsatya, Aleksandar Ignjatovic, Sri Parameswaran |
A novel instruction scratchpad memory optimization method based on concomitance metric. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, Yokohama, Japan, January 24-27, 2006, pp. 612-617, 2006, IEEE, 0-7803-9451-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
12 | Andhi Janapsatya, Aleksandar Ignjatovic, Sri Parameswaran |
Finding optimal L1 cache configuration for embedded systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, Yokohama, Japan, January 24-27, 2006, pp. 796-801, 2006, IEEE, 0-7803-9451-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
12 | Yen-Jen Chang |
Lazy BTB: reduce BTB energy consumption using dynamic profiling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, Yokohama, Japan, January 24-27, 2006, pp. 917-922, 2006, IEEE, 0-7803-9451-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
12 | Tom Vander Aa, Murali Jayapala, Henk Corporaal, Francky Catthoor, Geert Deconinck |
Instruction Transfer And Storage Exploration for Low Energy VLIWs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SiPS ![In: Proceedings of the IEEE Workshop on Signal Processing Systems, SiPS 2006, Proceedings, October 2-4, 2006, Banff, Alberta, Canada, pp. 292-297, 2006, IEEE, 1-4244-0382-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
12 | Lian Li 0002, Jingling Xue |
Trace-Based Data Cache Leakage Reduction at Link Time. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asia-Pacific Computer Systems Architecture Conference ![In: Advances in Computer Systems Architecture, 11th Asia-Pacific Conference, ACSAC 2006, Shanghai, China, September 6-8, 2006, Proceedings, pp. 175-188, 2006, Springer, 3-540-40056-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
12 | John Gilbert, David M. Abrahamson |
Adaptive object code compression. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2006 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2006, Seoul, Korea, October 22-25, 2006, pp. 282-292, 2006, ACM, 1-59593-543-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
code compression, code size reduction, code compaction |
12 | Basant Kumar Dwivedi, Arun Kejariwal, M. Balakrishnan, Anshul Kumar |
Rapid Resource-Constrained Hardware Performance Estimation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE International Workshop on Rapid System Prototyping ![In: 17th IEEE International Workshop on Rapid System Prototyping (RSP 2006), 14-16 June 2006, Chania, Crete, Greece, pp. 40-46, 2006, IEEE Computer Society, 0-7695-2580-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
12 | Wonbok Lee, Kimish Patel, Massoud Pedram |
Dynamic thermal management for MPEG-2 decoding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006, Tegernsee, Bavaria, Germany, October 4-6, 2006, pp. 316-321, 2006, ACM, 1-59593-462-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
MPEG-2 decoding, thermal model, temperature-aware design |
12 | Israel Waldman, Shlomit S. Pinter |
Profile-driven compression scheme for embedded systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Conf. Computing Frontiers ![In: Proceedings of the Third Conference on Computing Frontiers, 2006, Ischia, Italy, May 3-5, 2006, pp. 95-104, 2006, ACM, 1-59593-302-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
run-time decompression, code compression, code size reduction |
12 | Constantino G. Ribeiro, Marcelo Cintra |
Quantifying Uncertainty in Points-To Relations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCPC ![In: Languages and Compilers for Parallel Computing, 19th International Workshop, LCPC 2006, New Orleans, LA, USA, November 2-4, 2006. Revised Papers, pp. 190-204, 2006, Springer, 978-3-540-72520-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
12 | Ajay Joshi, Lieven Eeckhout, Robert H. Bell Jr., Lizy Kurian John |
Performance Cloning: A Technique for Disseminating Proprietary Applications as Benchmarks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IISWC ![In: Proceedings of the 2006 IEEE International Symposium on Workload Characterization, IISWC 2006, October 25-27, 2006, San Jose, California, USA, pp. 105-115, 2006, IEEE Computer Society, 1-4244-0508-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
12 | Ja Chun Ku, Serkan Ozdemir, Gokhan Memik, Yehea I. Ismail |
Power density minimization for highly-associative caches in embedded processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30 - May 1, 2006, pp. 100-104, 2006, ACM, 1-59593-347-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
cache, embedded processor, leakage power, temperature |
12 | Ying Chen, Karthik Ranganathan, Vasudev V. Pai, David J. Lilja, Kia Bazargan |
A Novel Memory Structure for Embedded Systems: Flexible Sequential and Random Access Memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Comput. Sci. Technol. ![In: J. Comput. Sci. Technol. 20(5), pp. 596-606, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
sequential access buffer, media benchmark, flexible sequential and random access memory, on-chip memory |
12 | Enric Gibert, F. Jesús Sánchez, Antonio González 0001 |
Distributed Data Cache Designs for Clustered VLIW Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 54(10), pp. 1227-1241, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
design styles, Single data stream architectures |
12 | Nahri Moreano, Edson Borin, Cid C. de Souza, Guido Araujo |
Efficient datapath merging for partially reconfigurable architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(7), pp. 969-980, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
12 | Ankur Srivastava 0001, Seda Ogrenci Memik, Bo-Kyung Choi, Majid Sarrafzadeh |
On effective slack management in postscheduling phase. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(4), pp. 645-653, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
12 | Chuanjun Zhang, Frank Vahid, Jun Yang 0002, Walid A. Najjar |
A way-halting cache for low-energy high-performance systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Archit. Code Optim. ![In: ACM Trans. Archit. Code Optim. 2(1), pp. 34-54, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
embedded systems, low power, Cache, dynamic optimization, low energy |
12 | Chuanjun Zhang, Frank Vahid, Walid A. Najjar |
A highly configurable cache for low energy embedded systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Embed. Comput. Syst. ![In: ACM Trans. Embed. Comput. Syst. 4(2), pp. 363-387, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
embedded systems, low power, Cache, microprocessor, configurable, memory hierarchy, low energy, architecture tuning |
12 | Philip Brisk, Jamie Macbeth 0001, Ani Nahapetian, Majid Sarrafzadeh |
A dictionary construction technique for code compression systems with echo instructions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES ![In: Proceedings of the 2005 ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'05), Chicago, Illinois, USA, June 15-17, 2005, pp. 105-114, 2005, ACM, 1-59593-018-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
(dictionary) compression, echo instructions, scheduling |
12 | Peter G. Sassone, D. Scott Wills, Gabriel H. Loh |
Static strands: safely collapsing dependence chains for increasing embedded power efficiency. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES ![In: Proceedings of the 2005 ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'05), Chicago, Illinois, USA, June 15-17, 2005, pp. 127-136, 2005, ACM, 1-59593-018-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
dependency collapsing, architecture, embedded, energy, sequentiality |
12 | Enric Gibert, Jaume Abella 0001, F. Jesús Sánchez, Xavier Vera, Antonio González 0001 |
Variable-Based Multi-module Data Caches for Clustered VLIW Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE PACT ![In: 14th International Conference on Parallel Architectures and Compilation Techniques (PACT 2005), 17-21 September 2005, St. Louis, MO, USA, pp. 207-217, 2005, IEEE Computer Society, 0-7695-2429-X. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
12 | Alex K. Jones, Raymond Hoare, Dara Kusic, Joshua Fazekas, John Foster 0001 |
An FPGA-based VLIW processor with custom hardware execution. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, FPGA 2005, Monterey, California, USA, February 20-22, 2005, pp. 107-117, 2005, ACM, 1-59593-029-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
NIOS, parallelism, compiler, synthesis, kernels, VLIW |
12 | Partha Biswas, Sudarshan Banerjee, Nikil D. Dutt, Laura Pozzi, Paolo Ienne |
ISEGEN: Generation of High-Quality Instruction Set Extensions by Iterative Improvement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2005 Design, Automation and Test in Europe Conference and Exposition (DATE 2005), 7-11 March 2005, Munich, Germany, pp. 1246-1251, 2005, IEEE Computer Society, 0-7695-2288-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
12 | Tingting Sha, Milo M. K. Martin, Amir Roth |
Scalable Store-Load Forwarding via Store Queue Index Prediction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: 38th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-38 2005), 12-16 November 2005, Barcelona, Spain, pp. 159-170, 2005, IEEE Computer Society, 0-7695-2440-0. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
12 | Qiang Wu, Philo Juang, Margaret Martonosi, Douglas W. Clark |
Voltage and Frequency Control With Adaptive Reaction Time in Multiple-Clock-Domain Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: 11th International Conference on High-Performance Computer Architecture (HPCA-11 2005), 12-16 February 2005, San Francisco, CA, USA, pp. 178-189, 2005, IEEE Computer Society, 0-7695-2275-0. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
12 | Azadeh Davoodi, Ankur Srivastava 0001 |
Simultaneous floorplanning and resource binding: a probabilistic approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005, pp. 517-522, 2005, ACM Press, 0-7803-8737-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
12 | Kiruthika Selvamani, Tarek M. Taha |
Estimating critical region parallelism to guide platform retargeting. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Southeast Regional Conference (1) ![In: Proceedings of the 43nd Annual Southeast Regional Conference, 2005, Kennesaw, Georgia, USA, March 18-20, 2005, Volume 1, pp. 168-173, 2005, ACM, 1-59593-059-0. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
analytical model, performance prediction |
12 | Juan Chen 0001, Yong Dong, Huizhan Yi, Xuejun Yang |
Power Consumption Analysis of Embedded Multimedia Application. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICESS ![In: Embedded Software and Systems, Second International Conference, ICESS 2005, Xi'an, China, December 16-18, 2005, Proceedings, pp. 596-607, 2005, Springer, 3-540-30881-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
12 | Eduardo Afonso Billo, Rodolfo Azevedo, Guido Araujo, Paulo Centoducatte, Eduardo Braulio Wanderley Netto |
Design of a decompressor engine on a SPARC processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 18th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2005, Florianolpolis, Brazil, September 4-7, 2005, pp. 110-114, 2005, ACM. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
performance, code compression |
12 | Hongkyu Kim, D. Scott Wills, Linda M. Wills |
Technology-based Architectural Analysis of Operand Bypass Networks for Efficient Operand Transport. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), CD-ROM / Abstracts Proceedings, 4-8 April 2005, Denver, CO, USA, 2005, IEEE Computer Society, 0-7695-2312-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
12 | Chuanjun Zhang |
An efficient direct mapped instruction cache for application-specific embedded systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2005, Jersey City, NJ, USA, September 19-21, 2005, pp. 45-50, 2005, ACM, 1-59593-161-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
efficient cache design, instruction cache, low power cache |
12 | Trevor N. Mudge |
Performance and power analysis of computer systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2005, Jersey City, NJ, USA, September 19-21, 2005, pp. 2, 2005, ACM, 1-59593-161-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
12 | Kugan Vivekanandarajah, Thambipillai Srikanthan |
Custom Instruction Filter Cache Synthesis for Low-Power Embedded Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE International Workshop on Rapid System Prototyping ![In: 16th IEEE International Workshop on Rapid System Prototyping (RSP 2005), 8-10 June 2005, Montreal, Canada, pp. 151-157, 2005, IEEE Computer Society, 0-7695-2361-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
12 | Gokhan Memik, Mahmut T. Kandemir, Arindam Mallik |
Load elimination for low-power embedded processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, Chicago, Illinois, USA, April 17-19, 2005, pp. 282-285, 2005, ACM, 1-59593-057-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
load elimination technique, low power design |
12 | Brian Fahs, Todd M. Rafacz, Sanjay J. Patel, Steven S. Lumetta |
Continuous Optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 32st International Symposium on Computer Architecture (ISCA 2005), 4-8 June 2005, Madison, Wisconsin, USA, pp. 86-97, 2005, IEEE Computer Society, 978-0-7695-2270-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
12 | Vlad Petric, Tingting Sha, Amir Roth |
RENO - A Rename-Based Instruction Optimizer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 32st International Symposium on Computer Architecture (ISCA 2005), 4-8 June 2005, Madison, Wisconsin, USA, pp. 98-109, 2005, IEEE Computer Society, 978-0-7695-2270-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
12 | Jennifer L. Wong, Farinaz Koushanfar, Miodrag Potkonjak |
Flexible ASIC: shared masking for multiple media processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005, pp. 909-914, 2005, ACM, 1-59593-058-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
optimization, interconnect, ASIC |