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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 70 occurrences of 46 keywords
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Results
Found 42 publication records. Showing 42 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
92 | Mike J. G. Lewis, L. E. M. Brackenbury |
An Instruction Buffer for a Low-Power DSP. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000), 2-6 April 2000, Eilat, Israel, pp. 176-, 2000, IEEE Computer Society, 0-7695-0586-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
92 | O. A. Petlin, Stephen B. Furber |
Built-In Self-Testing of Micropipelines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 3rd International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '97), 7-10 April 1997, Eindhoven, The Netherlands, pp. 22-29, 1997, IEEE Computer Society, 0-8186-7922-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
Built-in self-test, Design for test, Asynchronous design, Micropipelines |
86 | Oliver Chiu-sing Choy, Tin-Chak Johnson Pang, Juraj Povazanec, Cheong-Fat Chan |
A Useful Micropipeline Architecture to Implement DSP Algorithms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROMICRO ![In: 24th EUROMICRO '98 Conference, Engineering Systems and Software for the Next Decade, 25-27 August 1998, Vesteras, Sweden, pp. 10212-, 1998, IEEE Computer Society, 0-8186-8646-4. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
67 | Paul Day, John V. Woods |
Investigation into micropipeline latch design styles. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 3(2), pp. 264-272, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
65 | Oliver Chiu-sing Choy, Jan Butas, Juraj Povazanec, Cheong-Fat Chan |
A New Control Circuit for Asynchronous Micropipelines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 50(9), pp. 992-997, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
zero-overhead, dual-rail coding, Asynchronous design, micropipeline |
55 | Shih-Lien Lu |
Implementation of micropipelines in enable/disable CMOS differential logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 3(2), pp. 338-341, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
49 | Rajat Subhra Chakraborty, Swarup Bhunia |
Micropipeline-Based Asynchronous Design Methodology for Robust System Design Using Nanoscale Crossbar. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 9th International Symposium on Quality of Electronic Design (ISQED 2008), 17-19 March 2008, San Jose, CA, USA, pp. 697-701, 2008, IEEE Computer Society, 978-0-7695-3117-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Diode-resistor logic, CMOSNano, Asynchronous design |
49 | Abdel Ejnioui |
FPGA Prototyping of a Two-Phase Self-Oscillating Micropipeline. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), May 9-11, 2007, Porto Alegre, Brazil, pp. 437-438, 2007, IEEE Computer Society, 0-7695-2896-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
49 | Scott Fairbanks, Simon W. Moore |
Analog Micropipeline Rings for High Precision Timing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 10th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2004), 19-23 April 2004, Crete, Greece, pp. 41-50, 2004, IEEE Computer Society, 0-7695-2133-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
49 | Stephen B. Furber, Paul Day |
Four-phase micropipeline latch control circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 4(2), pp. 247-253, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
49 | Alessandro De Gloria, Mauro Olivieri |
Efficient semicustom micropipeline design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 3(3), pp. 464-469, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
49 | Ganesh Gopalakrishnan |
Developing Micropipeline Wavefront Arbiters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 11(4), pp. 55-64, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
47 | Bret Stott, Dave Johnson 0003, Venkatesh Akella |
Asynchronous 2-D discrete cosine transform core processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1995 International Conference on Computer Design (ICCD '95), VLSI in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings, pp. 380-385, 1995, IEEE Computer Society, 0-8186-7165-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
asynchronous 2-D discrete cosine transform core processor, self-timed design, CCITT compatible asynchronous DCT/IDCT processor, two-phase transition signaling, bounded delay approach, Sutherland's micropipeline, custom techniques, 2 /spl mu/ SCMOS technology, delays, discrete cosine transforms, digital signal processing chips, CMOS digital integrated circuits, standard cell, 2 micron |
47 | O. A. Petlin, Stephen B. Furber |
Scan testing of asynchronous sequential circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 5th Great Lakes Symposium on VLSI (GLS-VLSI '95), March 16-18, 1995, The State University of New York at Buffalo, USA, pp. 224-229, 1995, IEEE Computer Society, 0-8186-7035-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
micropipeline design style, combinational block, state holding elements, standard test generation techniques, VLSI, logic testing, delays, integrated circuit testing, logic design, sequential circuits, asynchronous circuits, integrated logic circuits, delay faults, boundary scan testing, scan testing, single stuck-at faults, asynchronous sequential logic, asynchronous sequential circuits |
37 | Tin Wai Kwan, Maitham Shams |
Design of Multi-GHz Asynchronous Pipelined Circuits in MOS Current-Mode Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 18th International Conference on VLSI Design (VLSI Design 2005), with the 4th International Conference on Embedded Systems Design, 3-7 January 2005, Kolkata, India, pp. 301-306, 2005, IEEE Computer Society, 0-7695-2264-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
37 | Matthew L. King, Kewal K. Saluja |
Testing Micropipelined Asynchronous Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2004 International Test Conference (ITC 2004), October 26-28, 2004, Charlotte, NC, USA, pp. 329-338, 2004, IEEE Computer Society, 0-7803-8581-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
37 | O. A. Petlin, Stephen B. Furber |
Scan testing of micropipelines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 13th IEEE VLSI Test Symposium (VTS'95), April 30 - May 3, 1995, Princeton, New Jersey, USA, pp. 296-303, 1995, IEEE Computer Society, 0-8186-7000-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
asynchronous VLSI circuit design, AMULET1 microprocessor, scan test technique, data processing blocks, combinational processing logic, state holding elements, test generation techniques, VLSI, logic testing, delays, integrated circuit testing, design for testability, logic design, asynchronous circuits, fault location, integrated circuit design, microprocessor chips, delay faults, boundary scan testing, computer testing, test patterns, single stuck-at faults, micropipelines |
30 | Cristiano Merio, Xavier Lesage, Ali Naimi, Sylvain Engels, Katell Morin-Allory, Laurent Fesquet |
Method for Data-Driven Pruning in Micropipeline Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 31st IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2023, Dubai, United Arab Emirates, October 16-18, 2023, pp. 1-6, 2023, IEEE, 979-8-3503-2599-7. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
30 | Sophie Germain, Sylvain Engels, Laurent Fesquet |
A Design Flow for Shaping Electromagnetic Emissions in Micropipeline Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 24th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2018, Vienna, Austria, May 13-16, 2018, pp. 28-29, 2018, IEEE Computer Society, 978-1-5386-5883-3. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
30 | Abdel Ejnioui |
Prototyping of a Two-Phase Micropipeline on FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ERSA ![In: Proceedings of the 2007 International Conference on Engineering of Reconfigurable Systems & Algorithms, ERSA 2007, Las Vegas, Nevada, USA, June 25-28, 2007, pp. 138-146, 2007, CSREA Press, 1-60132-026-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP BibTeX RDF |
|
30 | Yousaf Zafar, Muhammad Mansoor Ahmed |
A novel FPGA compliant micropipeline. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 52-II(9), pp. 611-615, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
30 | Howard Barringer, Donal Fellows, Graham Gough, Alan R. Williams |
Rainbow: Development, Simulation and Analysis Tools for Asynchronous Micropipeline Hardware Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Comput. J. ![In: Comput. J. 45(1), pp. 2-11, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
30 | Sanu hlathew, Ramalingam Sridhar |
A data-driven micropipeline structure using DSDCVSL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CICC ![In: Proceedings of the IEEE 1999 Custom Integrated Circuits Conference, CICC 1999, San Diego, CA, USA, May 16-19, 1999, pp. 295-298, 1999, IEEE, 0-7803-5443-5. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
30 | Yasunori Nagata, D. Michael Miller, Masao Mukaidono |
B-ternary Logic Based Asynchronous Micropipeline. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 29th IEEE International Symposium on Multiple-Valued Logic, ISMVL 1999, Freiburg im Breisgau, Germany, May 20-22, 1999, Proceedings, pp. 214-219, 1999, IEEE Computer Society, 0-7695-0161-3. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
30 | George S. Taylor, Gerard M. Blair |
Reduced complexity two-phase micropipeline latch controller. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 33(10), pp. 1590-1593, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
30 | Shlomo Weiss, A. Goldstein |
Floating point micropipeline performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Syst. Archit. ![In: J. Syst. Archit. 45(1), pp. 15-29, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
30 | Saeid Nooshabadi, Juan A. Montiel-Nelson, G. S. Visweswaran, D. Nagchoudhuri |
Micropipeline Architecture for Multiplier-less FIR Filters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 10th International Conference on VLSI Design (VLSI Design 1997), 4-7 January 1997, Hyderabad, India, pp. 451-456, 1997, IEEE Computer Society, 0-8186-7755-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
30 | Bengt Oelmann, Hannu Tenhunen |
A system level performance model for asynchronous micropipeline circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: Proceedings of Third International Conference on Electronics, Circuits, and Systems, ICECS 1996, Rodos, Greece, October 13-16, 1996, pp. 952-955, 1996, IEEE, 0-7803-3650-X. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
30 | Gernot Armin Liebchen, Ganesh Gopalakrishnan |
Dynamic Reordering of Hgh Latency Transactions Using a Modified a Micropipeline. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computer & Processors, ICCD '92, Cambridge, MA, USA, October 11-14, 1992, pp. 336-340, 1992, IEEE Computer Society, 0-8186-3110-4. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
28 | Charles E. Molnar, Ian W. Jones |
Simple Circuits that Work for Complicated Reasons. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000), 2-6 April 2000, Eilat, Israel, pp. 138-149, 2000, IEEE Computer Society, 0-7695-0586-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
MUTEX, Delay measurement technique, Latch control circuit, Charlie Box, Asynchronous, FIFO, Arbiter, Micropipeline |
28 | Jo C. Ebergen, Robert Berks |
Response Time Properties of Some Asynchronous Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 3rd International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '97), 7-10 April 1997, Eindhoven, The Netherlands, pp. 76-, 1997, IEEE Computer Society, 0-8186-7922-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
variable-delay model, performance analysis, Asynchronous circuits, response time, micropipeline |
18 | Raghid Shreih, Maitham Shams |
Implementation of asynchronous pipeline circuits in multi-threshold CMOS technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, Orlando, Florida, USA, May 4-6, 2008, pp. 189-194, 2008, ACM, 978-1-59593-999-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
c-element, gasp, low power, pipeline, asynchronous, multi-threshold |
18 | Paul Wielage, Erik Jan Marinissen, Michel Altheimer, Clemens Wouters |
Design and DfT of a high-speed area-efficient embedded asynchronous FIFO. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2007 Design, Automation and Test in Europe Conference and Exposition, DATE 2007, Nice, France, April 16-20, 2007, pp. 853-858, 2007, EDA Consortium, San Jose, CA, USA, 978-3-9810801-2-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
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18 | Tiberiu Chelcea, Girish Venkataramani, Seth Copen Goldstein |
Self-Resetting Latches for Asynchronous Micro-Pipelines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 44th Design Automation Conference, DAC 2007, San Diego, CA, USA, June 4-8, 2007, pp. 986-989, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
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18 | Konrad J. Kulikowski, Alexander B. Smirnov, Alexander Taubin |
Automated Design of Cryptographic Devices Resistant to Multiple Side-Channel Attacks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHES ![In: Cryptographic Hardware and Embedded Systems - CHES 2006, 8th International Workshop, Yokohama, Japan, October 10-13, 2006, Proceedings, pp. 399-413, 2006, Springer, 3-540-46559-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
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18 | Robert B. Reese, Mitchell A. Thornton, Cherrice Traver |
A Coarse-Grain Phased Logic CPU. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 54(7), pp. 788-799, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
asynchronous, pipelined processor, Automatic synthesis, self-timed, micropipelines |
18 | Tin Wai Kwan, Maitham Shams |
Design of High-Performance Power-Aware Asynchronous Pipelined Circuits in MOS Current Mode Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 11th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2005), 14-16 March 2005, New York, NY, USA, pp. 23-32, 2005, IEEE Computer Society, 0-7695-2305-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
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18 | Mike J. G. Lewis, Jim D. Garside, L. E. M. Brackenbury |
Reconfigurable Latch Controllers for Low Power Asynchronous Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '99), 19-22 April 1999, Barcelona, Spain, pp. 27-35, 1999, IEEE Computer Society, 0-7695-0031-5. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
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18 | Sun-Yen Tan, Stephen B. Furber, Wen-Fang Yen |
The Design of an Asynchronous VHDL Synthesizer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1998 Design, Automation and Test in Europe (DATE '98), February 23-26, 1998, Le Palais des Congrès de Paris, Paris, France, pp. 44-51, 1998, IEEE Computer Society, 0-8186-8359-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
Synthesis, VHDL, Asynchronous |
18 | W. J. Bainbridge, Stephen B. Furber |
Asynchronous Macrocell Interconnect using MARBLE. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '98), 30 March - 2 April 1998, San Diego, CA, USA, pp. 122-132, 1998, IEEE Computer Society, 0-8186-8392-9. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
Macrocell Bus, VLSI, Interconnect, Asynchronous |
18 | Antonio Cerone, David A. Kearney, George J. Milne |
Integrating the Verification of Timing, Performance and Correctness Properties of Concurrent Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACSD ![In: 1st International Conference on Application of Concurrency to System Design (ACSD '98), 23-26 March 1998, Fukushima, Japan, pp. 109-119, 1998, IEEE Computer Society, 0-8186-8350-3. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
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18 | Jelio Todorov Yantchev, C. G. Huang, Mark B. Josephs, Ivailo M. Nedelchev |
Low-latency asynchronous FIFO buffers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: Second Working Conference on Asynchronous Design Methodologies, May 30-31, 1995, London, England, UK, pp. 24-31, 1995, IEEE Computer Society, 0-8186-7098-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
buffer circuits, low-latency asynchronous FIFO buffers, parallel asynchronous implementation, interface circuitry, inter-chip communication wires, acknowledge signal, high-throughput multiple-burst signalling scheme, packet switching, asynchronous circuits, pipeline processing, propagation delay |
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