Search results for "Micropipeline"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
92	Mike J. G. Lewis, L. E. M. Brackenbury	An Instruction Buffer for a Low-Power DSP.	ASYNC	2000	DBLP DOI BibTeX RDF
92	O. A. Petlin, Stephen B. Furber	Built-In Self-Testing of Micropipelines.	ASYNC	1997	DBLP DOI BibTeX RDF	Built-in self-test, Design for test, Asynchronous design, Micropipelines
86	Oliver Chiu-sing Choy, Tin-Chak Johnson Pang, Juraj Povazanec, Cheong-Fat Chan	A Useful Micropipeline Architecture to Implement DSP Algorithms.	EUROMICRO	1998	DBLP DOI BibTeX RDF
67	Paul Day, John V. Woods	Investigation into micropipeline latch design styles.	IEEE Trans. Very Large Scale Integr. Syst.	1995	DBLP DOI BibTeX RDF
65	Oliver Chiu-sing Choy, Jan Butas, Juraj Povazanec, Cheong-Fat Chan	A New Control Circuit for Asynchronous Micropipelines.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	zero-overhead, dual-rail coding, Asynchronous design, micropipeline
55	Shih-Lien Lu	Implementation of micropipelines in enable/disable CMOS differential logic.	IEEE Trans. Very Large Scale Integr. Syst.	1995	DBLP DOI BibTeX RDF
49	Rajat Subhra Chakraborty, Swarup Bhunia	Micropipeline-Based Asynchronous Design Methodology for Robust System Design Using Nanoscale Crossbar.	ISQED	2008	DBLP DOI BibTeX RDF	Diode-resistor logic, CMOSNano, Asynchronous design
49	Abdel Ejnioui	FPGA Prototyping of a Two-Phase Self-Oscillating Micropipeline.	ISVLSI	2007	DBLP DOI BibTeX RDF
49	Scott Fairbanks, Simon W. Moore	Analog Micropipeline Rings for High Precision Timing.	ASYNC	2004	DBLP DOI BibTeX RDF
49	Stephen B. Furber, Paul Day	Four-phase micropipeline latch control circuits.	IEEE Trans. Very Large Scale Integr. Syst.	1996	DBLP DOI BibTeX RDF
49	Alessandro De Gloria, Mauro Olivieri	Efficient semicustom micropipeline design.	IEEE Trans. Very Large Scale Integr. Syst.	1995	DBLP DOI BibTeX RDF
49	Ganesh Gopalakrishnan	Developing Micropipeline Wavefront Arbiters.	IEEE Des. Test Comput.	1994	DBLP DOI BibTeX RDF
47	Bret Stott, Dave Johnson 0003, Venkatesh Akella	Asynchronous 2-D discrete cosine transform core processor.	ICCD	1995	DBLP DOI BibTeX RDF	asynchronous 2-D discrete cosine transform core processor, self-timed design, CCITT compatible asynchronous DCT/IDCT processor, two-phase transition signaling, bounded delay approach, Sutherland's micropipeline, custom techniques, 2 /spl mu/ SCMOS technology, delays, discrete cosine transforms, digital signal processing chips, CMOS digital integrated circuits, standard cell, 2 micron
47	O. A. Petlin, Stephen B. Furber	Scan testing of asynchronous sequential circuits.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	micropipeline design style, combinational block, state holding elements, standard test generation techniques, VLSI, logic testing, delays, integrated circuit testing, logic design, sequential circuits, asynchronous circuits, integrated logic circuits, delay faults, boundary scan testing, scan testing, single stuck-at faults, asynchronous sequential logic, asynchronous sequential circuits
37	Tin Wai Kwan, Maitham Shams	Design of Multi-GHz Asynchronous Pipelined Circuits in MOS Current-Mode Logic.	VLSI Design	2005	DBLP DOI BibTeX RDF
37	Matthew L. King, Kewal K. Saluja	Testing Micropipelined Asynchronous Circuits.	ITC	2004	DBLP DOI BibTeX RDF
37	O. A. Petlin, Stephen B. Furber	Scan testing of micropipelines.	VTS	1995	DBLP DOI BibTeX RDF	asynchronous VLSI circuit design, AMULET1 microprocessor, scan test technique, data processing blocks, combinational processing logic, state holding elements, test generation techniques, VLSI, logic testing, delays, integrated circuit testing, design for testability, logic design, asynchronous circuits, fault location, integrated circuit design, microprocessor chips, delay faults, boundary scan testing, computer testing, test patterns, single stuck-at faults, micropipelines
30	Cristiano Merio, Xavier Lesage, Ali Naimi, Sylvain Engels, Katell Morin-Allory, Laurent Fesquet	Method for Data-Driven Pruning in Micropipeline Circuits.	VLSI-SoC	2023	DBLP DOI BibTeX RDF
30	Sophie Germain, Sylvain Engels, Laurent Fesquet	A Design Flow for Shaping Electromagnetic Emissions in Micropipeline Circuits.	ASYNC	2018	DBLP DOI BibTeX RDF
30	Abdel Ejnioui	Prototyping of a Two-Phase Micropipeline on FPGAs.	ERSA	2007	DBLP BibTeX RDF
30	Yousaf Zafar, Muhammad Mansoor Ahmed	A novel FPGA compliant micropipeline.	IEEE Trans. Circuits Syst. II Express Briefs	2005	DBLP DOI BibTeX RDF
30	Howard Barringer, Donal Fellows, Graham Gough, Alan R. Williams	Rainbow: Development, Simulation and Analysis Tools for Asynchronous Micropipeline Hardware Design.	Comput. J.	2002	DBLP DOI BibTeX RDF
30	Sanu hlathew, Ramalingam Sridhar	A data-driven micropipeline structure using DSDCVSL.	CICC	1999	DBLP DOI BibTeX RDF
30	Yasunori Nagata, D. Michael Miller, Masao Mukaidono	B-ternary Logic Based Asynchronous Micropipeline.	ISMVL	1999	DBLP DOI BibTeX RDF
30	George S. Taylor, Gerard M. Blair	Reduced complexity two-phase micropipeline latch controller.	IEEE J. Solid State Circuits	1998	DBLP DOI BibTeX RDF
30	Shlomo Weiss, A. Goldstein	Floating point micropipeline performance.	J. Syst. Archit.	1998	DBLP DOI BibTeX RDF
30	Saeid Nooshabadi, Juan A. Montiel-Nelson, G. S. Visweswaran, D. Nagchoudhuri	Micropipeline Architecture for Multiplier-less FIR Filters.	VLSI Design	1997	DBLP DOI BibTeX RDF
30	Bengt Oelmann, Hannu Tenhunen	A system level performance model for asynchronous micropipeline circuits.	ICECS	1996	DBLP DOI BibTeX RDF
30	Gernot Armin Liebchen, Ganesh Gopalakrishnan	Dynamic Reordering of Hgh Latency Transactions Using a Modified a Micropipeline.	ICCD	1992	DBLP DOI BibTeX RDF
28	Charles E. Molnar, Ian W. Jones	Simple Circuits that Work for Complicated Reasons.	ASYNC	2000	DBLP DOI BibTeX RDF	MUTEX, Delay measurement technique, Latch control circuit, Charlie Box, Asynchronous, FIFO, Arbiter, Micropipeline
28	Jo C. Ebergen, Robert Berks	Response Time Properties of Some Asynchronous Circuits.	ASYNC	1997	DBLP DOI BibTeX RDF	variable-delay model, performance analysis, Asynchronous circuits, response time, micropipeline
18	Raghid Shreih, Maitham Shams	Implementation of asynchronous pipeline circuits in multi-threshold CMOS technologies.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	c-element, gasp, low power, pipeline, asynchronous, multi-threshold
18	Paul Wielage, Erik Jan Marinissen, Michel Altheimer, Clemens Wouters	Design and DfT of a high-speed area-efficient embedded asynchronous FIFO.	DATE	2007	DBLP DOI BibTeX RDF
18	Tiberiu Chelcea, Girish Venkataramani, Seth Copen Goldstein	Self-Resetting Latches for Asynchronous Micro-Pipelines.	DAC	2007	DBLP DOI BibTeX RDF
18	Konrad J. Kulikowski, Alexander B. Smirnov, Alexander Taubin	Automated Design of Cryptographic Devices Resistant to Multiple Side-Channel Attacks.	CHES	2006	DBLP DOI BibTeX RDF
18	Robert B. Reese, Mitchell A. Thornton, Cherrice Traver	A Coarse-Grain Phased Logic CPU.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	asynchronous, pipelined processor, Automatic synthesis, self-timed, micropipelines
18	Tin Wai Kwan, Maitham Shams	Design of High-Performance Power-Aware Asynchronous Pipelined Circuits in MOS Current Mode Logic.	ASYNC	2005	DBLP DOI BibTeX RDF
18	Mike J. G. Lewis, Jim D. Garside, L. E. M. Brackenbury	Reconfigurable Latch Controllers for Low Power Asynchronous Circuits.	ASYNC	1999	DBLP DOI BibTeX RDF
18	Sun-Yen Tan, Stephen B. Furber, Wen-Fang Yen	The Design of an Asynchronous VHDL Synthesizer.	DATE	1998	DBLP DOI BibTeX RDF	Synthesis, VHDL, Asynchronous
18	W. J. Bainbridge, Stephen B. Furber	Asynchronous Macrocell Interconnect using MARBLE.	ASYNC	1998	DBLP DOI BibTeX RDF	Macrocell Bus, VLSI, Interconnect, Asynchronous
18	Antonio Cerone, David A. Kearney, George J. Milne	Integrating the Verification of Timing, Performance and Correctness Properties of Concurrent Systems.	ACSD	1998	DBLP DOI BibTeX RDF
18	Jelio Todorov Yantchev, C. G. Huang, Mark B. Josephs, Ivailo M. Nedelchev	Low-latency asynchronous FIFO buffers.	ASYNC	1995	DBLP DOI BibTeX RDF	buffer circuits, low-latency asynchronous FIFO buffers, parallel asynchronous implementation, interface circuitry, inter-chip communication wires, acknowledge signal, high-throughput multiple-burst signalling scheme, packet switching, asynchronous circuits, pipeline processing, propagation delay