Search results for "Multipliers"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
97	K'Andrea C. Bickerstaff, Michael J. Schulte, Earl E. Swartzlander Jr.	Parallel reduced area multipliers.	J. VLSI Signal Process.	1995	DBLP DOI BibTeX RDF
74	Shreesha Srinath, Katherine Compton	Automatic generation of high-performance multipliers for FPGAs with asymmetric multiplier blocks.	FPGA	2010	DBLP DOI BibTeX RDF	asymmetric multipliers, composable multipliers, multiplier design
74	Oscal T.-C. Chen, Sandy Wang, Yi-Wen Wu	Minimization of switching activities of partial products for designing low-power multipliers.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
67	Janardhan H. Satyanarayana, Keshab K. Parhi, Leilei Song, Yun-Nan Chang	Systematic analysis of bounds on power consumption in pipelined and non-pipelined multipliers.	ICCD	1996	DBLP DOI BibTeX RDF	pipelined multipliers, nonpipelined multipliers, Baugh-Wooley multiplier, binary tree multiplier, Wallace tree multiplier, STDs, sub circuits, energy values, cubic dependence, word length, quadratic dependence, digital CMOS circuits, CMOS adder, low power arithmetic units, power consumption, power consumption, switching activity, state transition diagrams
67	Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian	An effective BIST scheme for carry-save and carry-propagate array multipliers.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	BIST scheme, carry-propagate array multipliers, carry-save array multipliers, complex VLSI devices, maximum length LFSR, count-based scheme, multiplier cells, VLSI, logic testing, controllability, built-in self test, integrated circuit testing, automatic testing, observability, fault coverage, test pattern generator, multiplying circuits, carry logic
62	Masayuki Yoshino, Katsuyuki Okeya, Camille Vuillaume	A Black Hen Lays White Eggs.	CARDIS	2008	DBLP DOI BibTeX RDF	double-size technique, RSA, smartcard, Montgomery multiplication, efficient implementation
59	Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian	Effective Built-In Self-Test for Booth Multipliers.	IEEE Des. Test Comput.	1998	DBLP DOI BibTeX RDF	Booth multipliers, Built-In Self Test, design for testability, data paths
59	Alok A. Katkar, James E. Stine	Modified booth truncated multipliers.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	VLSI, arithmetic
54	Suthikshn Kumar, Kevin E. Forward, Marimuthu Palaniswami	A fast-multiplier generator for FPGAs.	VLSI Design	1995	DBLP DOI BibTeX RDF	fast-multiplier generator, variable word length multipliers, Booth encoded optimized Wallace tree architecture, field programmable gate arrays, FPGAs, parallel architectures, artificial neural networks, multiplying circuits, FPGA architecture, neural chips
51	Francisco Rodríguez-Henríquez, Çetin Kaya Koç	Parallel Multipliers Based on Special Irreducible Pentanomials.	IEEE Trans. Computers	2003	DBLP DOI BibTeX RDF	pentanomials, multipliers for GF(2^m), Finite fields arithmetic, parallel multipliers
51	Kiamal Z. Pekmastzi	Multiplexer-Based Array Multipliers.	IEEE Trans. Computers	1999	DBLP DOI BibTeX RDF	multiplication algorithm, two's complement multiplication, pipeline multipliers, Array multipliers
51	Issam Alzaher-Noufal, Michael Nicolaidis	A CAD Framework for Generating Self-Checking 1 Multipliers Based on Residue Codes.	DATE	1999	DBLP DOI BibTeX RDF	Fault Secure Circuits, Residue Arithmetic Codes, Multipliers, Self-Checking Circuits
51	Ravi Kumar Satzoda, Ramya Muralidharan, Chip-Hong Chang	Programmable LSB-first and MSB-first modular multipliers for ECC in GF(2m).	ISCAS	2008	DBLP DOI BibTeX RDF
51	Haining Fan, M. Anwar Hasan	A New Approach to Subquadratic Space Complexity Parallel Multipliers for Extended Binary Fields.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	subquadratic space complexity multiplier, shifted polynomial basis, Finite field, coordinate transformation, Toeplitz matrix
51	Michal Bidlo	Evolutionary Design of Generic Combinational Multipliers Using Development.	ICES	2007	DBLP DOI BibTeX RDF
51	Arash Reyhani-Masoleh, M. Anwar Hasan	Low Complexity Word-Level Sequential Normal Basis Multipliers.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	Finite field, optimal normal basis, Massey-Omura multiplier
51	Arash Reyhani-Masoleh, M. Anwarul Hasan	Low Complexity Sequential Normal Basis Multipliers over GF(2m).	IEEE Symposium on Computer Arithmetic	2003	DBLP DOI BibTeX RDF	Finite field, optimal normal basis, Massey-Omura multiplier
51	Nan-Ying Shen, Oscal T.-C. Chen	Low-power multipliers by minimizing switching activities of partial products.	ISCAS (4)	2002	DBLP DOI BibTeX RDF
51	K'Andrea C. Bickerstaff, Earl E. Swartzlander Jr., Michael J. Schulte	Analysis of Column Compression Multipliers.	IEEE Symposium on Computer Arithmetic	2001	DBLP DOI BibTeX RDF
51	Avinash K. Gautam, V. Visvanathan, S. K. Nandy 0001	Automatic Generation of Tree Multipliers Using Placement-Driven Netlists.	ICCD	1999	DBLP DOI BibTeX RDF
46	Luciano A. de Lacerda, Edson P. Santana, Cleber Vinícius A. de Almeida, Ana Isabela Araújo Cunha	Distortion analysis of analog multiplier circuits using two-dimensional integral nonlinear function.	SBCCI	2009	DBLP DOI BibTeX RDF	CMOS multipliers, distortion, analog multipliers
46	Gopalakrishnan Lakshminarayanan, B. Venkataramani	Optimization Techniques for FPGA-Based Wave-Pipelined DSP Blocks.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
43	Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian	An Effective Built-In Self-Test Scheme for Parallel Multipliers.	IEEE Trans. Computers	1999	DBLP DOI BibTeX RDF	tree multipliers, Built-in self-test, array multipliers, cell fault model
43	Costas Efstathiou, Haridimos T. Vergos, Giorgos Dimitrakopoulos, Dimitris Nikolos	Efficient Diminished-1 Modulo 2^n+1 Multipliers.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	Modulo 2^n+1 multipliers, Fermat number transform, computer arithmetic, VLSI design, residue number system
43	Costas Efstathiou, Haridimos T. Vergos, Dimitris Nikolos	Modified Booth Modulo 2n-1 Multipliers.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF	Mersenne arithmetic, one's complement arithmetic, Booth multipliers, VLSI design, Residue Number System
43	T. Sansaloni, Javier Valls, Keshab K. Parhi	Digit-Serial Complex-Number Multipliers on FPGAs.	J. VLSI Signal Process.	2003	DBLP DOI BibTeX RDF	complex-number multipliers, digit-serial arithmetic, FPGA, Booth recoding
43	Roman A. Polyak	Log-Sigmoid Multipliers Method in Constrained Optimization.	Ann. Oper. Res.	2001	DBLP DOI BibTeX RDF	log-sigmoid, multipliers method, smoothing technique, duality
43	Milos D. Ercegovac, Tomás Lang, Jean-Michel Muller, Arnaud Tisserand	Reciprocation, Square Root, Inverse Square Root, and Some Elementary Functions Using Small Multipliers.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	inverse square root, single-/double-precision operations, small multipliers, exponential, square root, Reciprocal, logarithm, Taylor series
43	Dimitris Bakalis, Dimitris Nikolos, George Alexiou, Emmanouil Kalligeros, Haridimos T. Vergos	Low Power BIST for Wallace Tree-Based Fast Multipliers.	ISQED	2000	DBLP DOI BibTeX RDF	Testing, Low Power, BIST, Multipliers, Wallace Trees
43	Sebastian T. J. Fenn, Michael Gössel, Mohammed Benaissa, David Taylor	On-Line Error Detection for Bit-Serial Multipliers in GF(2m).	J. Electron. Test.	1998	DBLP DOI BibTeX RDF	finite fields, multipliers, parity checking, on-line error detection
43	Michael Nicolaidis, Ricardo de Oliveira Duarte	Design of Fault-Secure Parity-Prediction Booth Multipliers.	DATE	1998	DBLP DOI BibTeX RDF	Booth multipliers, Self-checking circuits
43	Dimitris Gizopoulos, Dimitris Nikolos, Antonis M. Paschalis, Constantin Halatsis	C-Testable modified-Booth multipliers.	J. Electron. Test.	1996	DBLP DOI BibTeX RDF	Booth multipliers, design for testability, C-testability, iterative logic arrays, carry lookahead adders, cell fault model
43	Chetana Nagendra, Robert Michael Owens, Mary Jane Irwin	Design tradeoffs in high speed multipliers and FIR filters.	VLSI Design	1996	DBLP DOI BibTeX RDF	high speed multipliers, high speed FIR filters, modified Booth recoding, pipeline granularity, transistor count, activity factor reduction, guarded evaluation, gate-level pipelining, half-bit level pipelining, bit-level pipelining, delay, clocking, digital filters, FIR filters, multiplying circuits, power dissipation, design tradeoffs, pipeline arithmetic, operation speed
43	Hakim Bederr, Michael Nicolaidis, Alain Guyot	Analytic approach for error masking elimination in on-line multipliers.	IEEE Symposium on Computer Arithmetic	1995	DBLP DOI BibTeX RDF	error masking elimination, online multipliers, high precision numbers, scan design approach, internal state observability, DFT approach, sequential circuits, digital arithmetic, fault coverage, multiplying circuits, area overhead
43	Sandeep S. Kumar, Thomas J. Wollinger, Christof Paar	Optimum Digit Serial GF(2^m) Multipliers for Curve-Based Cryptography.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	least significant digit multiplier, elliptic/hyperelliptic curve cryptography, public key cryptography, digit serial multiplier, Bit serial multiplier
43	Chiou-Yng Lee, Jenn-Shyong Horng, I-Chang Jou, Erl-Huei Lu	Low-Complexity Bit-Parallel Systolic Montgomery Multipliers for Special Classes of GF(2m).	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	irreducible AOP, finite field, montgomery multiplication, irreducible trinomial, Bit-parallel systolic multiplier
43	Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis	Built-in sequential fault self-testing of array multipliers.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
43	Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang	Low-voltage micropower multipliers with reduced spurious switching.	ISCAS (4)	2005	DBLP DOI BibTeX RDF
43	Kenny Johansson, Oscar Gustafsson, Lars Wanhammar	Low-complexity bit-serial constant-coefficient multipliers.	ISCAS (3)	2004	DBLP DOI BibTeX RDF
43	Jean-Luc Beuchat	Some Modular Adders and Multipliers for Field Programmable Gate Arrays.	IPDPS	2003	DBLP DOI BibTeX RDF	modulo m addition, modulo m multiplication, FPGA, Computer arithmetic
43	Tong Zhang 0002, Keshab K. Parhi	Systematic Design of Original and Modified Mastrovito Multipliers for General Irreducible Polynomials.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	Finite (or Galois) field, standard basis, complexity, multiplication, VLSI architecture, irreducible polynomials, Toeplitz matrix
43	Mihalis Psarakis, Antonis M. Paschalis, Nektarios Kranitis, Dimitris Gizopoulos, Yervant Zorian	Robust and Low-Cost BIST Architectures for Sequential Fault Testing in Datapath Multipliers.	VTS	2001	DBLP DOI BibTeX RDF
43	Tim Courtney, Richard H. Turner, Roger F. Woods	An Investigation of Reconfigurable Multipliers for Use in Adaptive Signal Processing.	FCCM	2000	DBLP DOI BibTeX RDF
43	Javier Valls, Trini Sansaloni, Marcos Martínez-Peiró, Eduardo I. Boemo	Fast FPGA-based pipelined digit-serial/parallel multipliers.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
43	Richard C. North, Walter H. Ku	beta-bit serial/parallel multipliers.	J. VLSI Signal Process.	1991	DBLP DOI BibTeX RDF
39	Oliver A. Pfänder, Reinhard Nopper, Hans-Jörg Pfleiderer, Shun Zhou, Amine Bermak	Configurable Blocks for Multi-precision Multiplication.	DELTA	2008	DBLP DOI BibTeX RDF	reconfigurable multipliers, embedded blocks, multi-precision, FPGA, multiplication
38	Mark S. K. Lau, Keck Voon Ling, Yun-Chung Chu	Energy-aware probabilistic multiplier: design and analysis.	CASES	2009	DBLP DOI BibTeX RDF	optimization, multiplier, voltage scaling, probabilistic computation
38	R. Mahesh 0001, A. Prasad Vinod 0001	A New Common Subexpression Elimination Algorithm for Realizing Low-Complexity Higher Order Digital Filters.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
38	Hong-An Huang, Yen-Chin Liao, Hsie-Chia Chang	A self-compensation fixed-width booth multiplier and its 128-point FFT applications.	ISCAS	2006	DBLP DOI BibTeX RDF
38	Zhijun Huang, Milos D. Ercegovac	High-Performance Low-Power Left-to-Right Array Multiplier Design.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	Left-to-right array multiplier, tree multiplier, layout regularity, low-power design, high-performance design
38	Yirng-An Chen, Randal E. Bryant	An efficient graph representation for arithmetic circuitverification.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
38	J. Living, M. Moniri, S. B. Tennakoon	Efficient Recursive Digital Filters using Combined Look-Ahead Denominator Distribution and Numerator Decomposition.	J. VLSI Signal Process.	2001	DBLP DOI BibTeX RDF	IIR digital filters, iteration bound, look ahead pipelining, resource minimisation
38	Sandro Wefel, Paul Molitor	Prove that a faulty multiplier is faulty!?	ACM Great Lakes Symposium on VLSI	2000	DBLP DOI BibTeX RDF
38	Gerardo Orlando, Christof Paar	A Super-Serial Galois Fields Multiplier for FPGAs and its Application to Public-Key Algorithms.	FCCM	1999	DBLP DOI BibTeX RDF	Galois Fields multiplier, field programmable gate array application, cryptography, elliptic curve cryptography
38	Yirng-An Chen, Randal E. Bryant	PHDD: an efficient graph representation for floating point circuit verification.	ICCAD	1997	DBLP DOI BibTeX RDF	KFDD, BMD, HDD, KBMD, Verification, Formal Verifications, BDD, Floating Point, FDD, BMD
36	Patrizia Daniele	Lagrange multipliers and infinite-dimensional equilibrium problems.	J. Glob. Optim.	2008	DBLP DOI BibTeX RDF	Separation theory, Quasi relative interior, Lagrange multipliers, Equilibrium problems
36	Robert T. Grisamore, Earl E. Swartzlander Jr.	Negative Save Sign Extension for Multi-term Adders and Multipliers.	J. Signal Process. Syst.	2008	DBLP DOI BibTeX RDF	adder trees, multi-term adders, two’s complement arithmetic, sign extension, multipliers
36	Pasquale Malacaria, Han Chen	Lagrange multipliers and maximum information leakage in different observational models.	PLAS	2008	DBLP DOI BibTeX RDF	security, information theory, lagrange multipliers
36	Hafizur Rahaman 0001, Jimson Mathew, Biplab K. Sikdar, Dhiraj K. Pradhan	Transition Fault Testability in Bit Parallel Multipliers over GF(2^{m}).	VTS	2007	DBLP DOI BibTeX RDF	cryptography, polynomials, Multipliers, Galois field, error control code, Transition fault, C-testable
36	Gang Quan, James P. Davis, Siddhaveerasharan Devarkal, Duncan A. Buell	High-level synthesis for large bit-width multipliers on FPGAs: a case study.	CODES+ISSS	2005	DBLP DOI BibTeX RDF	FPGA devices, large-scale integer multipliers, high level synthesis, reconfigurable computing, design exploration
36	Lisa A. Korf	Stochastic programming duality: 8 multipliers for unbounded constraints with an application to mathematical finance.	Math. Program.	2004	DBLP DOI BibTeX RDF	arbitrage, fundamental theorem of asset pricing, duality, stochastic programming, Lagrange multipliers
36	Kiamal Z. Pekmestzi, Paraskevas Kalivas	Constant Number Serial Pipeline Multipliers.	J. VLSI Signal Process.	2000	DBLP DOI BibTeX RDF	constant number multiplication, serial multipliers, systolic circuits, canonic signed digit representation
36	Xrysovalantis Kavousianos, Dimitris Bakalis, Haridimos T. Vergos, Dimitris Nikolos, George Alexiou	Low Power Dissipation in BIST Schemes for Modified Booth Multipliers.	DFT	1999	DBLP DOI BibTeX RDF	Modified Booth Multipliers, Low Power, Built In Self Test, VLSI Testing
36	Luca Breveglieri, Luigi Dadda, Vincenzo Piuri	Column Compression Pipelined Multipliers.	ASAP	1995	DBLP DOI BibTeX RDF	pipelining, computer arithmetic, multipliers
35	Alexey F. Izmailov, Mikhail V. Solodov	On attraction of Newton-type iterates to multipliers violating second-order sufficiency conditions.	Math. Program.	2009	DBLP DOI BibTeX RDF	Mathematics Subject Classification (2000) 90C30
35	Saeeid Tahmasbi Oskuii, Per Gunnar Kjeldsberg, Lars Lundheim, Asghar Havashki	Power Optimization of Parallel Multipliers in Systems with Variable Word-Length.	PATMOS	2008	DBLP DOI BibTeX RDF
35	Álvaro Vázquez, Elisardo Antelo, Paolo Montuschi	A New Family of High.Performance Parallel Decimal Multipliers.	IEEE Symposium on Computer Arithmetic	2007	DBLP DOI BibTeX RDF
35	Michal Bidlo	Evolutionary Development of Generic Multipliers: Initial Results.	AHS	2007	DBLP DOI BibTeX RDF
35	Saeeid Tahmasbi Oskuii, Per Gunnar Kjeldsberg, Oscar Gustafsson	Transition-activity aware design of reduction-stages for parallel multipliers.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	power consumption, parallel multiplier, partial product reduction, transition activity
35	José Luis Imaña, Juan Manuel Sánchez, Francisco Tirado	Bit-Parallel Finite Field Multipliers for Irreducible Trinomials.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	Finite (or Galois) fields, canonical basis, triangular basis, complexity, permutation, multiplication, cycles, matrix decomposition, transpositions, irreducible trinomials
35	Magnus Karlsson, Mark Vesterbacka	Digit-serial/parallel multipliers with improved throughput and latency.	ISCAS	2006	DBLP DOI BibTeX RDF
35	Nima Honarmand, Ali Afzali-Kusha	Low Power Combinational Multipliers using Data-driven Signal Gating.	APCCAS	2006	DBLP DOI BibTeX RDF
35	Cornelia Grabbe, Marcus Bednara, Jürgen Teich, Joachim von zur Gathen, Jamshid Shokrollahi	FPGA designs of parallel high performance GF(2233) multipliers.	ISCAS (2)	2003	DBLP DOI BibTeX RDF
35	Jiunn-Chern Chen, Yirng-An Chen	Equivalence checking of integer multipliers.	ASP-DAC	2001	DBLP DOI BibTeX RDF
35	Ron Balczewski, Ramesh Harjani	Capacitive voltage multipliers: a high efficiency method to generate multiple on-chip supply voltages.	ISCAS (1)	2001	DBLP DOI BibTeX RDF
35	Pierre L'Ecuyer, Richard J. Simard	Beware of linear congruential generators with multipliers of the form a = ±2q ±2r.	ACM Trans. Math. Softw.	1999	DBLP DOI BibTeX RDF	correlation test, random number generation, linear congruential generators
35	Leilei Song, Keshab K. Parhi	Low-complexity modified Mastrovito multipliers over finite fields GF(2M).	ISCAS (1)	1999	DBLP DOI BibTeX RDF
35	Thomas K. Callaway, Earl E. Swartzlander Jr.	Power-Delay Characteristics of CMOS Multipliers.	IEEE Symposium on Computer Arithmetic	1997	DBLP DOI BibTeX RDF
35	Michael Gössel, Sebastian T. J. Fenn, David Taylor	On-line error detection for finite field multipliers.	DFT	1997	DBLP DOI BibTeX RDF	on-line error detection circuit, parity prediction, simulation, fault coverage, multiplying circuits, hardware overhead, finite field multiplier
35	Martin Keim, Michael Martin 0002, Bernd Becker 0001, Rolf Drechsler, Paul Molitor	Polynomial Formal Verification of Multipliers.	VTS	1997	DBLP DOI BibTeX RDF	Binary Moment Diagram (BMD), Verification, Multiplier
31	Michael J. Schulte, Pablo I. Balzola, Ahmet Akkas, Robert W. Brocato	Integer Multiplication with Overflow Detection or Saturation.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	unsigned, tree multipliers, computer arithmetic, array multipliers, Overflow, saturation, integer, two's complement
31	Ajay Kumar Verma, Paolo Ienne	Improving XOR-Dominated Circuits by Exploiting Dependencies between Operands.	ASP-DAC	2007	DBLP DOI BibTeX RDF	multiplier-like circuits, XOR-dominated circuits, datapath design, netlist optimization, carry-save form, column compressors, XOR operations, logic synthesizers, algebraic factoring, computer arithmetic, logic synthesis, digital design, parallel multipliers
31	Cheng-Yu Pai, Asim J. Al-Khalili, William E. Lynch	Low-Power Constant-Coefficient Multiplier Generator.	J. VLSI Signal Process.	2003	DBLP DOI BibTeX RDF	constant multipliers, low power, VHDL, DSP, design automation, integer multiplication
31	Masayuki Yoshino, Katsuyuki Okeya, Camille Vuillaume	Unbridle the Bit-Length of a Crypto-coprocessor with Montgomery Multiplication.	Selected Areas in Cryptography	2006	DBLP DOI BibTeX RDF	RSA, smartcard, Montgomery multiplication, crypto-coprocessor
31	Osama Daifallah Al-Khaleel, Christos A. Papachristou, Francis G. Wolff, Kiamal Z. Pekmestzi	A Large Scale Adaptable Multiplier for Cryptographic Applications.	AHS	2006	DBLP DOI BibTeX RDF
31	Casper Lageweg, Sorin Cotofana, Stamatis Vassiliadis	Binary Multiplication based on Single Electron Tunneling.	ASAP	2004	DBLP DOI BibTeX RDF
31	Zhijun Huang, Milos D. Ercegovac	High-Performance Left-to-Right Array Multiplier Design.	IEEE Symposium on Computer Arithmetic	2003	DBLP DOI BibTeX RDF
31	Kiyoharu Hamaguchi, Akihito Morita, Shuzo Yajima	Efficient construction of binary moment diagrams for verifying arithmetic circuits.	ICCAD	1995	DBLP DOI BibTeX RDF	word-level verification, binary moment diagram, arithmetic circuit, design verification
28	Valeria Garofalo, Nicola Petra, Ettore Napoli	Analytical Calculation of the Maximum Error for a Family of Truncated Multipliers Providing Minimum Mean Square Error.	IEEE Trans. Computers	2011	DBLP DOI BibTeX RDF	truncated multipliers, maximum error, digital arithmetic, error analysis, Multiplication, error compensation
28	Igor V. Evstigneev, Sjur Didrik Flåm	Stochastic Programming: Nonanticipativity and Lagrange Multipliers.	Encyclopedia of Optimization	2009	DBLP DOI BibTeX RDF	Nonanticipativity, Fritz John conditions, Yosida-Hewitt decomposition, Stochastic programming, Lagrange multipliers
28	Marc Teboulle	Lagrangian Multipliers Methods for Convex Programming.	Encyclopedia of Optimization	2009	DBLP DOI BibTeX RDF	Proximal algorithms, Convex optimization, Augmented Lagrangians, Primal-dual methods, Lagrangian multipliers
28	Pachara V. Rao, Cyril Prasanna Raj, S. Ravi 0001	VLSI Design and Analysis of Multipliers for Low Power.	IIH-MSP	2009	DBLP DOI BibTeX RDF	Low Power, Delay, CMOS, Multipliers, Area, ASIC Implementation
28	Lucia Parussini	Fictitious Domain Approach Via Lagrange Multipliers with Least Squares Spectral Element Method.	J. Sci. Comput.	2008	DBLP DOI BibTeX RDF	Fictitious Domain, Least Squares Spectral Element Method, Lagrange multipliers
28	Katsushi Ohmori, Norikazu Saito	Flux-free Finite Element Method with Lagrange Multipliers for Two-fluid Flows.	J. Sci. Comput.	2007	DBLP DOI BibTeX RDF	Two-fluid flows, flux-free constraint, mass preserving, finite element method, Lagrange multipliers
28	Hesham A. Al-Twaijry, Michael J. Flynn	Technology Scaling Effects on Multipliers.	IEEE Trans. Computers	1998	DBLP DOI BibTeX RDF	Feature size, topology, multipliers, Booth encoding
28	Weng-Fai Wong, Eiichi Goto	Fast Hardware-Based Algorithms for Elementary Function Computations Using Rectangular Multipliers.	IEEE Trans. Computers	1994	DBLP DOI BibTeX RDF	hardware-based algorithms, elementary function computations, rectangular multipliers, common elementary functions, reciprocal square root, arc tangent, microscopic parallelism, floating point multiplication, scientific computations, digital arithmetic, error analysis, sine, cosine
28	Jien-Chung Lo, Suchai Thanawastien, T. R. N. Rao	Berger Check Prediction for Array Multipliers and Array Dividers.	IEEE Trans. Computers	1993	DBLP DOI BibTeX RDF	Berger check prediction, array dividers, closed-form check-predicting equations, digital arithmetic, multiplying circuits, array multipliers, dividing circuits
28	Alexander Skavantzos, Poornachandra B. Rao	New Multipliers Modulo 2^N - 1.	IEEE Trans. Computers	1992	DBLP DOI BibTeX RDF	modulo 2/sup N/-1, ROM bits, digital arithmetic, multiplication, multipliers, multiplying circuits, additions, squaring, look-up tables, cyclic convolution
28	Nobuaki Yoshida, Eiichi Goto, Shuichi Ichikawa	Pseudorandom Rounding for Truncated Multipliers.	IEEE Trans. Computers	1991	DBLP DOI BibTeX RDF	truncated multipliers, pseudorandom rounding, digital arithmetic, multiplications, rounding, floating-point numbers, multiple-precision
28	Stamatis Vassiliadis, Eric M. Schwarz, Baik Moon Sung	Hard-Wired Multipliers with Encoded Partial Products.	IEEE Trans. Computers	1991	DBLP DOI BibTeX RDF	hardwired multipliers, encoded partial products, multibit overlapped scanning multiplication algorithm, sign-magnitude, encoding, digital arithmetic, multiplying circuits, two's complement