The FacetedDBLP logo    Search for: in:

Disable automatic phrases ?     Syntactic query expansion: ?

Searching for Multipliers with no syntactic query expansion in all metadata.

Publication years (Num. hits)
1956-1975 (15) 1976-1980 (18) 1981-1984 (20) 1985-1988 (24) 1989-1990 (20) 1991 (16) 1992-1993 (32) 1994 (18) 1995 (39) 1996 (28) 1997 (27) 1998 (40) 1999 (58) 2000 (47) 2001 (76) 2002 (74) 2003 (105) 2004 (101) 2005 (139) 2006 (151) 2007 (117) 2008 (166) 2009 (91) 2010 (55) 2011 (56) 2012 (66) 2013 (73) 2014 (79) 2015 (91) 2016 (79) 2017 (94) 2018 (133) 2019 (110) 2020 (108) 2021 (119) 2022 (125) 2023 (137) 2024 (31)
Publication types (Num. hits)
article(1370) book(1) data(2) incollection(14) inproceedings(1381) phdthesis(10)
GrowBag graphs for keyword ? (Num. hits/coverage)

Group by:
The graphs summarize 1366 occurrences of 709 keywords

Results
Found 2778 publication records. Showing 2778 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
97K'Andrea C. Bickerstaff, Michael J. Schulte, Earl E. Swartzlander Jr. Parallel reduced area multipliers. Search on Bibsonomy J. VLSI Signal Process. The full citation details ... 1995 DBLP  DOI  BibTeX  RDF
74Shreesha Srinath, Katherine Compton Automatic generation of high-performance multipliers for FPGAs with asymmetric multiplier blocks. Search on Bibsonomy FPGA The full citation details ... 2010 DBLP  DOI  BibTeX  RDF asymmetric multipliers, composable multipliers, multiplier design
74Oscal T.-C. Chen, Sandy Wang, Yi-Wen Wu Minimization of switching activities of partial products for designing low-power multipliers. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
67Janardhan H. Satyanarayana, Keshab K. Parhi, Leilei Song, Yun-Nan Chang Systematic analysis of bounds on power consumption in pipelined and non-pipelined multipliers. Search on Bibsonomy ICCD The full citation details ... 1996 DBLP  DOI  BibTeX  RDF pipelined multipliers, nonpipelined multipliers, Baugh-Wooley multiplier, binary tree multiplier, Wallace tree multiplier, STDs, sub circuits, energy values, cubic dependence, word length, quadratic dependence, digital CMOS circuits, CMOS adder, low power arithmetic units, power consumption, power consumption, switching activity, state transition diagrams
67Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian An effective BIST scheme for carry-save and carry-propagate array multipliers. Search on Bibsonomy Asian Test Symposium The full citation details ... 1995 DBLP  DOI  BibTeX  RDF BIST scheme, carry-propagate array multipliers, carry-save array multipliers, complex VLSI devices, maximum length LFSR, count-based scheme, multiplier cells, VLSI, logic testing, controllability, built-in self test, integrated circuit testing, automatic testing, observability, fault coverage, test pattern generator, multiplying circuits, carry logic
62Masayuki Yoshino, Katsuyuki Okeya, Camille Vuillaume A Black Hen Lays White Eggs. Search on Bibsonomy CARDIS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF double-size technique, RSA, smartcard, Montgomery multiplication, efficient implementation
59Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian Effective Built-In Self-Test for Booth Multipliers. Search on Bibsonomy IEEE Des. Test Comput. The full citation details ... 1998 DBLP  DOI  BibTeX  RDF Booth multipliers, Built-In Self Test, design for testability, data paths
59Alok A. Katkar, James E. Stine Modified booth truncated multipliers. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2004 DBLP  DOI  BibTeX  RDF VLSI, arithmetic
54Suthikshn Kumar, Kevin E. Forward, Marimuthu Palaniswami A fast-multiplier generator for FPGAs. Search on Bibsonomy VLSI Design The full citation details ... 1995 DBLP  DOI  BibTeX  RDF fast-multiplier generator, variable word length multipliers, Booth encoded optimized Wallace tree architecture, field programmable gate arrays, FPGAs, parallel architectures, artificial neural networks, multiplying circuits, FPGA architecture, neural chips
51Francisco Rodríguez-Henríquez, Çetin Kaya Koç Parallel Multipliers Based on Special Irreducible Pentanomials. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2003 DBLP  DOI  BibTeX  RDF pentanomials, multipliers for GF(2^m), Finite fields arithmetic, parallel multipliers
51Kiamal Z. Pekmastzi Multiplexer-Based Array Multipliers. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1999 DBLP  DOI  BibTeX  RDF multiplication algorithm, two's complement multiplication, pipeline multipliers, Array multipliers
51Issam Alzaher-Noufal, Michael Nicolaidis A CAD Framework for Generating Self-Checking 1 Multipliers Based on Residue Codes. Search on Bibsonomy DATE The full citation details ... 1999 DBLP  DOI  BibTeX  RDF Fault Secure Circuits, Residue Arithmetic Codes, Multipliers, Self-Checking Circuits
51Ravi Kumar Satzoda, Ramya Muralidharan, Chip-Hong Chang Programmable LSB-first and MSB-first modular multipliers for ECC in GF(2m). Search on Bibsonomy ISCAS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
51Haining Fan, M. Anwar Hasan A New Approach to Subquadratic Space Complexity Parallel Multipliers for Extended Binary Fields. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2007 DBLP  DOI  BibTeX  RDF subquadratic space complexity multiplier, shifted polynomial basis, Finite field, coordinate transformation, Toeplitz matrix
51Michal Bidlo Evolutionary Design of Generic Combinational Multipliers Using Development. Search on Bibsonomy ICES The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
51Arash Reyhani-Masoleh, M. Anwar Hasan Low Complexity Word-Level Sequential Normal Basis Multipliers. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2005 DBLP  DOI  BibTeX  RDF Finite field, optimal normal basis, Massey-Omura multiplier
51Arash Reyhani-Masoleh, M. Anwarul Hasan Low Complexity Sequential Normal Basis Multipliers over GF(2m). Search on Bibsonomy IEEE Symposium on Computer Arithmetic The full citation details ... 2003 DBLP  DOI  BibTeX  RDF Finite field, optimal normal basis, Massey-Omura multiplier
51Nan-Ying Shen, Oscal T.-C. Chen Low-power multipliers by minimizing switching activities of partial products. Search on Bibsonomy ISCAS (4) The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
51K'Andrea C. Bickerstaff, Earl E. Swartzlander Jr., Michael J. Schulte Analysis of Column Compression Multipliers. Search on Bibsonomy IEEE Symposium on Computer Arithmetic The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
51Avinash K. Gautam, V. Visvanathan, S. K. Nandy 0001 Automatic Generation of Tree Multipliers Using Placement-Driven Netlists. Search on Bibsonomy ICCD The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
46Luciano A. de Lacerda, Edson P. Santana, Cleber Vinícius A. de Almeida, Ana Isabela Araújo Cunha Distortion analysis of analog multiplier circuits using two-dimensional integral nonlinear function. Search on Bibsonomy SBCCI The full citation details ... 2009 DBLP  DOI  BibTeX  RDF CMOS multipliers, distortion, analog multipliers
46Gopalakrishnan Lakshminarayanan, B. Venkataramani Optimization Techniques for FPGA-Based Wave-Pipelined DSP Blocks. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
43Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian An Effective Built-In Self-Test Scheme for Parallel Multipliers. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1999 DBLP  DOI  BibTeX  RDF tree multipliers, Built-in self-test, array multipliers, cell fault model
43Costas Efstathiou, Haridimos T. Vergos, Giorgos Dimitrakopoulos, Dimitris Nikolos Efficient Diminished-1 Modulo 2^n+1 Multipliers. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2005 DBLP  DOI  BibTeX  RDF Modulo 2^n+1 multipliers, Fermat number transform, computer arithmetic, VLSI design, residue number system
43Costas Efstathiou, Haridimos T. Vergos, Dimitris Nikolos Modified Booth Modulo 2n-1 Multipliers. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2004 DBLP  DOI  BibTeX  RDF Mersenne arithmetic, one's complement arithmetic, Booth multipliers, VLSI design, Residue Number System
43T. Sansaloni, Javier Valls, Keshab K. Parhi Digit-Serial Complex-Number Multipliers on FPGAs. Search on Bibsonomy J. VLSI Signal Process. The full citation details ... 2003 DBLP  DOI  BibTeX  RDF complex-number multipliers, digit-serial arithmetic, FPGA, Booth recoding
43Roman A. Polyak Log-Sigmoid Multipliers Method in Constrained Optimization. Search on Bibsonomy Ann. Oper. Res. The full citation details ... 2001 DBLP  DOI  BibTeX  RDF log-sigmoid, multipliers method, smoothing technique, duality
43Milos D. Ercegovac, Tomás Lang, Jean-Michel Muller, Arnaud Tisserand Reciprocation, Square Root, Inverse Square Root, and Some Elementary Functions Using Small Multipliers. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2000 DBLP  DOI  BibTeX  RDF inverse square root, single-/double-precision operations, small multipliers, exponential, square root, Reciprocal, logarithm, Taylor series
43Dimitris Bakalis, Dimitris Nikolos, George Alexiou, Emmanouil Kalligeros, Haridimos T. Vergos Low Power BIST for Wallace Tree-Based Fast Multipliers. Search on Bibsonomy ISQED The full citation details ... 2000 DBLP  DOI  BibTeX  RDF Testing, Low Power, BIST, Multipliers, Wallace Trees
43Sebastian T. J. Fenn, Michael Gössel, Mohammed Benaissa, David Taylor On-Line Error Detection for Bit-Serial Multipliers in GF(2m). Search on Bibsonomy J. Electron. Test. The full citation details ... 1998 DBLP  DOI  BibTeX  RDF finite fields, multipliers, parity checking, on-line error detection
43Michael Nicolaidis, Ricardo de Oliveira Duarte Design of Fault-Secure Parity-Prediction Booth Multipliers. Search on Bibsonomy DATE The full citation details ... 1998 DBLP  DOI  BibTeX  RDF Booth multipliers, Self-checking circuits
43Dimitris Gizopoulos, Dimitris Nikolos, Antonis M. Paschalis, Constantin Halatsis C-Testable modified-Booth multipliers. Search on Bibsonomy J. Electron. Test. The full citation details ... 1996 DBLP  DOI  BibTeX  RDF Booth multipliers, design for testability, C-testability, iterative logic arrays, carry lookahead adders, cell fault model
43Chetana Nagendra, Robert Michael Owens, Mary Jane Irwin Design tradeoffs in high speed multipliers and FIR filters. Search on Bibsonomy VLSI Design The full citation details ... 1996 DBLP  DOI  BibTeX  RDF high speed multipliers, high speed FIR filters, modified Booth recoding, pipeline granularity, transistor count, activity factor reduction, guarded evaluation, gate-level pipelining, half-bit level pipelining, bit-level pipelining, delay, clocking, digital filters, FIR filters, multiplying circuits, power dissipation, design tradeoffs, pipeline arithmetic, operation speed
43Hakim Bederr, Michael Nicolaidis, Alain Guyot Analytic approach for error masking elimination in on-line multipliers. Search on Bibsonomy IEEE Symposium on Computer Arithmetic The full citation details ... 1995 DBLP  DOI  BibTeX  RDF error masking elimination, online multipliers, high precision numbers, scan design approach, internal state observability, DFT approach, sequential circuits, digital arithmetic, fault coverage, multiplying circuits, area overhead
43Sandeep S. Kumar, Thomas J. Wollinger, Christof Paar Optimum Digit Serial GF(2^m) Multipliers for Curve-Based Cryptography. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2006 DBLP  DOI  BibTeX  RDF least significant digit multiplier, elliptic/hyperelliptic curve cryptography, public key cryptography, digit serial multiplier, Bit serial multiplier
43Chiou-Yng Lee, Jenn-Shyong Horng, I-Chang Jou, Erl-Huei Lu Low-Complexity Bit-Parallel Systolic Montgomery Multipliers for Special Classes of GF(2m). Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2005 DBLP  DOI  BibTeX  RDF irreducible AOP, finite field, montgomery multiplication, irreducible trinomial, Bit-parallel systolic multiplier
43Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis Built-in sequential fault self-testing of array multipliers. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
43Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang Low-voltage micropower multipliers with reduced spurious switching. Search on Bibsonomy ISCAS (4) The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
43Kenny Johansson, Oscar Gustafsson, Lars Wanhammar Low-complexity bit-serial constant-coefficient multipliers. Search on Bibsonomy ISCAS (3) The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
43Jean-Luc Beuchat Some Modular Adders and Multipliers for Field Programmable Gate Arrays. Search on Bibsonomy IPDPS The full citation details ... 2003 DBLP  DOI  BibTeX  RDF modulo m addition, modulo m multiplication, FPGA, Computer arithmetic
43Tong Zhang 0002, Keshab K. Parhi Systematic Design of Original and Modified Mastrovito Multipliers for General Irreducible Polynomials. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2001 DBLP  DOI  BibTeX  RDF Finite (or Galois) field, standard basis, complexity, multiplication, VLSI architecture, irreducible polynomials, Toeplitz matrix
43Mihalis Psarakis, Antonis M. Paschalis, Nektarios Kranitis, Dimitris Gizopoulos, Yervant Zorian Robust and Low-Cost BIST Architectures for Sequential Fault Testing in Datapath Multipliers. Search on Bibsonomy VTS The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
43Tim Courtney, Richard H. Turner, Roger F. Woods An Investigation of Reconfigurable Multipliers for Use in Adaptive Signal Processing. Search on Bibsonomy FCCM The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
43Javier Valls, Trini Sansaloni, Marcos Martínez-Peiró, Eduardo I. Boemo Fast FPGA-based pipelined digit-serial/parallel multipliers. Search on Bibsonomy ISCAS (1) The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
43Richard C. North, Walter H. Ku beta-bit serial/parallel multipliers. Search on Bibsonomy J. VLSI Signal Process. The full citation details ... 1991 DBLP  DOI  BibTeX  RDF
39Oliver A. Pfänder, Reinhard Nopper, Hans-Jörg Pfleiderer, Shun Zhou, Amine Bermak Configurable Blocks for Multi-precision Multiplication. Search on Bibsonomy DELTA The full citation details ... 2008 DBLP  DOI  BibTeX  RDF reconfigurable multipliers, embedded blocks, multi-precision, FPGA, multiplication
38Mark S. K. Lau, Keck Voon Ling, Yun-Chung Chu Energy-aware probabilistic multiplier: design and analysis. Search on Bibsonomy CASES The full citation details ... 2009 DBLP  DOI  BibTeX  RDF optimization, multiplier, voltage scaling, probabilistic computation
38R. Mahesh 0001, A. Prasad Vinod 0001 A New Common Subexpression Elimination Algorithm for Realizing Low-Complexity Higher Order Digital Filters. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
38Hong-An Huang, Yen-Chin Liao, Hsie-Chia Chang A self-compensation fixed-width booth multiplier and its 128-point FFT applications. Search on Bibsonomy ISCAS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
38Zhijun Huang, Milos D. Ercegovac High-Performance Low-Power Left-to-Right Array Multiplier Design. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2005 DBLP  DOI  BibTeX  RDF Left-to-right array multiplier, tree multiplier, layout regularity, low-power design, high-performance design
38Yirng-An Chen, Randal E. Bryant An efficient graph representation for arithmetic circuitverification. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
38J. Living, M. Moniri, S. B. Tennakoon Efficient Recursive Digital Filters using Combined Look-Ahead Denominator Distribution and Numerator Decomposition. Search on Bibsonomy J. VLSI Signal Process. The full citation details ... 2001 DBLP  DOI  BibTeX  RDF IIR digital filters, iteration bound, look ahead pipelining, resource minimisation
38Sandro Wefel, Paul Molitor Prove that a faulty multiplier is faulty!? Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
38Gerardo Orlando, Christof Paar A Super-Serial Galois Fields Multiplier for FPGAs and its Application to Public-Key Algorithms. Search on Bibsonomy FCCM The full citation details ... 1999 DBLP  DOI  BibTeX  RDF Galois Fields multiplier, field programmable gate array application, cryptography, elliptic curve cryptography
38Yirng-An Chen, Randal E. Bryant PHDD: an efficient graph representation for floating point circuit verification. Search on Bibsonomy ICCAD The full citation details ... 1997 DBLP  DOI  BibTeX  RDF KFDD, *BMD, HDD, K*BMD, Verification, Formal Verifications, BDD, Floating Point, FDD, BMD
36Patrizia Daniele Lagrange multipliers and infinite-dimensional equilibrium problems. Search on Bibsonomy J. Glob. Optim. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF Separation theory, Quasi relative interior, Lagrange multipliers, Equilibrium problems
36Robert T. Grisamore, Earl E. Swartzlander Jr. Negative Save Sign Extension for Multi-term Adders and Multipliers. Search on Bibsonomy J. Signal Process. Syst. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF adder trees, multi-term adders, two’s complement arithmetic, sign extension, multipliers
36Pasquale Malacaria, Han Chen Lagrange multipliers and maximum information leakage in different observational models. Search on Bibsonomy PLAS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF security, information theory, lagrange multipliers
36Hafizur Rahaman 0001, Jimson Mathew, Biplab K. Sikdar, Dhiraj K. Pradhan Transition Fault Testability in Bit Parallel Multipliers over GF(2^{m}). Search on Bibsonomy VTS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF cryptography, polynomials, Multipliers, Galois field, error control code, Transition fault, C-testable
36Gang Quan, James P. Davis, Siddhaveerasharan Devarkal, Duncan A. Buell High-level synthesis for large bit-width multipliers on FPGAs: a case study. Search on Bibsonomy CODES+ISSS The full citation details ... 2005 DBLP  DOI  BibTeX  RDF FPGA devices, large-scale integer multipliers, high level synthesis, reconfigurable computing, design exploration
36Lisa A. Korf Stochastic programming duality: 8 multipliers for unbounded constraints with an application to mathematical finance. Search on Bibsonomy Math. Program. The full citation details ... 2004 DBLP  DOI  BibTeX  RDF arbitrage, fundamental theorem of asset pricing, duality, stochastic programming, Lagrange multipliers
36Kiamal Z. Pekmestzi, Paraskevas Kalivas Constant Number Serial Pipeline Multipliers. Search on Bibsonomy J. VLSI Signal Process. The full citation details ... 2000 DBLP  DOI  BibTeX  RDF constant number multiplication, serial multipliers, systolic circuits, canonic signed digit representation
36Xrysovalantis Kavousianos, Dimitris Bakalis, Haridimos T. Vergos, Dimitris Nikolos, George Alexiou Low Power Dissipation in BIST Schemes for Modified Booth Multipliers. Search on Bibsonomy DFT The full citation details ... 1999 DBLP  DOI  BibTeX  RDF Modified Booth Multipliers, Low Power, Built In Self Test, VLSI Testing
36Luca Breveglieri, Luigi Dadda, Vincenzo Piuri Column Compression Pipelined Multipliers. Search on Bibsonomy ASAP The full citation details ... 1995 DBLP  DOI  BibTeX  RDF pipelining, computer arithmetic, multipliers
35Alexey F. Izmailov, Mikhail V. Solodov On attraction of Newton-type iterates to multipliers violating second-order sufficiency conditions. Search on Bibsonomy Math. Program. The full citation details ... 2009 DBLP  DOI  BibTeX  RDF Mathematics Subject Classification (2000) 90C30
35Saeeid Tahmasbi Oskuii, Per Gunnar Kjeldsberg, Lars Lundheim, Asghar Havashki Power Optimization of Parallel Multipliers in Systems with Variable Word-Length. Search on Bibsonomy PATMOS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
35Álvaro Vázquez, Elisardo Antelo, Paolo Montuschi A New Family of High.Performance Parallel Decimal Multipliers. Search on Bibsonomy IEEE Symposium on Computer Arithmetic The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
35Michal Bidlo Evolutionary Development of Generic Multipliers: Initial Results. Search on Bibsonomy AHS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
35Saeeid Tahmasbi Oskuii, Per Gunnar Kjeldsberg, Oscar Gustafsson Transition-activity aware design of reduction-stages for parallel multipliers. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2007 DBLP  DOI  BibTeX  RDF power consumption, parallel multiplier, partial product reduction, transition activity
35José Luis Imaña, Juan Manuel Sánchez, Francisco Tirado Bit-Parallel Finite Field Multipliers for Irreducible Trinomials. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2006 DBLP  DOI  BibTeX  RDF Finite (or Galois) fields, canonical basis, triangular basis, complexity, permutation, multiplication, cycles, matrix decomposition, transpositions, irreducible trinomials
35Magnus Karlsson, Mark Vesterbacka Digit-serial/parallel multipliers with improved throughput and latency. Search on Bibsonomy ISCAS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
35Nima Honarmand, Ali Afzali-Kusha Low Power Combinational Multipliers using Data-driven Signal Gating. Search on Bibsonomy APCCAS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
35Cornelia Grabbe, Marcus Bednara, Jürgen Teich, Joachim von zur Gathen, Jamshid Shokrollahi FPGA designs of parallel high performance GF(2233) multipliers. Search on Bibsonomy ISCAS (2) The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
35Jiunn-Chern Chen, Yirng-An Chen Equivalence checking of integer multipliers. Search on Bibsonomy ASP-DAC The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
35Ron Balczewski, Ramesh Harjani Capacitive voltage multipliers: a high efficiency method to generate multiple on-chip supply voltages. Search on Bibsonomy ISCAS (1) The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
35Pierre L'Ecuyer, Richard J. Simard Beware of linear congruential generators with multipliers of the form a = ±2q ±2r. Search on Bibsonomy ACM Trans. Math. Softw. The full citation details ... 1999 DBLP  DOI  BibTeX  RDF correlation test, random number generation, linear congruential generators
35Leilei Song, Keshab K. Parhi Low-complexity modified Mastrovito multipliers over finite fields GF(2M). Search on Bibsonomy ISCAS (1) The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
35Thomas K. Callaway, Earl E. Swartzlander Jr. Power-Delay Characteristics of CMOS Multipliers. Search on Bibsonomy IEEE Symposium on Computer Arithmetic The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
35Michael Gössel, Sebastian T. J. Fenn, David Taylor On-line error detection for finite field multipliers. Search on Bibsonomy DFT The full citation details ... 1997 DBLP  DOI  BibTeX  RDF on-line error detection circuit, parity prediction, simulation, fault coverage, multiplying circuits, hardware overhead, finite field multiplier
35Martin Keim, Michael Martin 0002, Bernd Becker 0001, Rolf Drechsler, Paul Molitor Polynomial Formal Verification of Multipliers. Search on Bibsonomy VTS The full citation details ... 1997 DBLP  DOI  BibTeX  RDF Binary Moment Diagram (BMD), Verification, Multiplier
31Michael J. Schulte, Pablo I. Balzola, Ahmet Akkas, Robert W. Brocato Integer Multiplication with Overflow Detection or Saturation. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2000 DBLP  DOI  BibTeX  RDF unsigned, tree multipliers, computer arithmetic, array multipliers, Overflow, saturation, integer, two's complement
31Ajay Kumar Verma, Paolo Ienne Improving XOR-Dominated Circuits by Exploiting Dependencies between Operands. Search on Bibsonomy ASP-DAC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF multiplier-like circuits, XOR-dominated circuits, datapath design, netlist optimization, carry-save form, column compressors, XOR operations, logic synthesizers, algebraic factoring, computer arithmetic, logic synthesis, digital design, parallel multipliers
31Cheng-Yu Pai, Asim J. Al-Khalili, William E. Lynch Low-Power Constant-Coefficient Multiplier Generator. Search on Bibsonomy J. VLSI Signal Process. The full citation details ... 2003 DBLP  DOI  BibTeX  RDF constant multipliers, low power, VHDL, DSP, design automation, integer multiplication
31Masayuki Yoshino, Katsuyuki Okeya, Camille Vuillaume Unbridle the Bit-Length of a Crypto-coprocessor with Montgomery Multiplication. Search on Bibsonomy Selected Areas in Cryptography The full citation details ... 2006 DBLP  DOI  BibTeX  RDF RSA, smartcard, Montgomery multiplication, crypto-coprocessor
31Osama Daifallah Al-Khaleel, Christos A. Papachristou, Francis G. Wolff, Kiamal Z. Pekmestzi A Large Scale Adaptable Multiplier for Cryptographic Applications. Search on Bibsonomy AHS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
31Casper Lageweg, Sorin Cotofana, Stamatis Vassiliadis Binary Multiplication based on Single Electron Tunneling. Search on Bibsonomy ASAP The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
31Zhijun Huang, Milos D. Ercegovac High-Performance Left-to-Right Array Multiplier Design. Search on Bibsonomy IEEE Symposium on Computer Arithmetic The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
31Kiyoharu Hamaguchi, Akihito Morita, Shuzo Yajima Efficient construction of binary moment diagrams for verifying arithmetic circuits. Search on Bibsonomy ICCAD The full citation details ... 1995 DBLP  DOI  BibTeX  RDF word-level verification, binary moment diagram, arithmetic circuit, design verification
28Valeria Garofalo, Nicola Petra, Ettore Napoli Analytical Calculation of the Maximum Error for a Family of Truncated Multipliers Providing Minimum Mean Square Error. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2011 DBLP  DOI  BibTeX  RDF truncated multipliers, maximum error, digital arithmetic, error analysis, Multiplication, error compensation
28Igor V. Evstigneev, Sjur Didrik Flåm Stochastic Programming: Nonanticipativity and Lagrange Multipliers. Search on Bibsonomy Encyclopedia of Optimization The full citation details ... 2009 DBLP  DOI  BibTeX  RDF Nonanticipativity, Fritz John conditions, Yosida-Hewitt decomposition, Stochastic programming, Lagrange multipliers
28Marc Teboulle Lagrangian Multipliers Methods for Convex Programming. Search on Bibsonomy Encyclopedia of Optimization The full citation details ... 2009 DBLP  DOI  BibTeX  RDF Proximal algorithms, Convex optimization, Augmented Lagrangians, Primal-dual methods, Lagrangian multipliers
28Pachara V. Rao, Cyril Prasanna Raj, S. Ravi 0001 VLSI Design and Analysis of Multipliers for Low Power. Search on Bibsonomy IIH-MSP The full citation details ... 2009 DBLP  DOI  BibTeX  RDF Low Power, Delay, CMOS, Multipliers, Area, ASIC Implementation
28Lucia Parussini Fictitious Domain Approach Via Lagrange Multipliers with Least Squares Spectral Element Method. Search on Bibsonomy J. Sci. Comput. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF Fictitious Domain, Least Squares Spectral Element Method, Lagrange multipliers
28Katsushi Ohmori, Norikazu Saito Flux-free Finite Element Method with Lagrange Multipliers for Two-fluid Flows. Search on Bibsonomy J. Sci. Comput. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF Two-fluid flows, flux-free constraint, mass preserving, finite element method, Lagrange multipliers
28Hesham A. Al-Twaijry, Michael J. Flynn Technology Scaling Effects on Multipliers. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1998 DBLP  DOI  BibTeX  RDF Feature size, topology, multipliers, Booth encoding
28Weng-Fai Wong, Eiichi Goto Fast Hardware-Based Algorithms for Elementary Function Computations Using Rectangular Multipliers. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1994 DBLP  DOI  BibTeX  RDF hardware-based algorithms, elementary function computations, rectangular multipliers, common elementary functions, reciprocal square root, arc tangent, microscopic parallelism, floating point multiplication, scientific computations, digital arithmetic, error analysis, sine, cosine
28Jien-Chung Lo, Suchai Thanawastien, T. R. N. Rao Berger Check Prediction for Array Multipliers and Array Dividers. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1993 DBLP  DOI  BibTeX  RDF Berger check prediction, array dividers, closed-form check-predicting equations, digital arithmetic, multiplying circuits, array multipliers, dividing circuits
28Alexander Skavantzos, Poornachandra B. Rao New Multipliers Modulo 2^N - 1. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1992 DBLP  DOI  BibTeX  RDF modulo 2/sup N/-1, ROM bits, digital arithmetic, multiplication, multipliers, multiplying circuits, additions, squaring, look-up tables, cyclic convolution
28Nobuaki Yoshida, Eiichi Goto, Shuichi Ichikawa Pseudorandom Rounding for Truncated Multipliers. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1991 DBLP  DOI  BibTeX  RDF truncated multipliers, pseudorandom rounding, digital arithmetic, multiplications, rounding, floating-point numbers, multiple-precision
28Stamatis Vassiliadis, Eric M. Schwarz, Baik Moon Sung Hard-Wired Multipliers with Encoded Partial Products. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1991 DBLP  DOI  BibTeX  RDF hardwired multipliers, encoded partial products, multibit overlapped scanning multiplication algorithm, sign-magnitude, encoding, digital arithmetic, multiplying circuits, two's complement
Displaying result #1 - #100 of 2778 (100 per page; Change: )
Pages: [1][2][3][4][5][6][7][8][9][10][>>]
Valid XHTML 1.1! Valid CSS! [Valid RSS]
Maintained by L3S.
Previously maintained by Jörg Diederich.
Based upon DBLP by Michael Ley.
open data data released under the ODC-BY 1.0 license