Search results for "NDR"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
135	Alejandro F. González, Mayukh Bhattacharya, Shriram Kulkarni, Pinaki Mazumder	Standard CMOS Implementation of a Multiple-Valued Logic Signed-Digit Adder Based on Negative Differential-Resistance Devices.	ISMVL	2000	DBLP DOI BibTeX RDF	signed-digit adder, negative differential-resistance devices, NDR devices, multiple-valued logic, resonant-tunneling diodes, redundant number systems, RTDs
118	Dong-Shong Liang, Kwang-Jow Gan, Chung-Chih Hsiao, Cher-Shiung Tsai, Yaw-Hwang Chen, Shih-Yu Wang, Shun-Huo Kuo, Feng-Chang Chiang, Long-Xian Su	Novel Voltage-Controlled Oscillator Design by MOS-NDR Devices and Circuits.	IWSOC	2005	DBLP DOI BibTeX RDF
100	Kwang-Jow Gan, Dong-Shong Liang, Cher-Shiung Tsai, Yaw-Hwang Chen, Chun-Ming Wen	Five-State Logic Using MOS-HBT-NDR Circuit by Standard SiGe BiCMOS Process.	APCCAS	2006	DBLP DOI BibTeX RDF
82	Dong-Shong Liang, Cheng-Chi Tai, Kwang-Jow Gan, Cher-Shiung Tsai, Yaw-Hwang Chen	Design of AND and NAND Logic Gate Using NDR-BASED Circuit Suitable for CMOS Process.	APCCAS	2006	DBLP DOI BibTeX RDF
82	Dong-Shong Liang, Kwang-Jow Gan, Long-Xian Su, Chi-Pin Chen, Chung-Chih Hsiao, Cher-Shiung Tsai, Yaw-Hwang Chen, Shih-Yu Wang, Shun-Huo Kuo, Feng-Chang Chiang	Four-Valued Memory Circuit Designed by Multiple-Peak MOS-NDR Devices and Circuits.	IWSOC	2005	DBLP DOI BibTeX RDF
81	Dong-Shong Liang, Kwang-Jow Gan	New D-Type Flip-Flop Design Using Negative Differential Resistance Circuits.	DELTA	2008	DBLP DOI BibTeX RDF	negative differential resistance(NDR), monostable-bistable transition logic elements(MOBILE)
64	Dong-Shong Liang, Yaw-Hwang Chen, Chun-Min Wen, Chun-Da Tu, Kwang-Jow Gan, Cher-Shiung Tsai	The Design of MOS-NDR-Based Cellular Neural Network.	IJCNN	2006	DBLP DOI BibTeX RDF
64	Kwang-Jow Gan, Dong-Shong Liang, Chung-Chih Hsiao, Shih-Yu Wang, Feng-Chang Chiang, Cher-Shiung Tsai, Yaw-Hwang Chen, Shun-Huo Kuo, Chi-Pin Chen	Logic Circuit Design Based on MOS-NDR Devices and Circuits Fabricated by CMOS Process.	IWSOC	2005	DBLP DOI BibTeX RDF
63	Marek A. Bawiec	Resonant Tunnelling Diode-Based Circuits: Simulation and Synthesis.	EUROCAST	2009	DBLP DOI BibTeX RDF	Nanoelectronic Devices, NDR Modelling, Boolean Logic Synthesis, SPICE Simulation
54	Sundarar Mohan, Jian Ping Sun, Pinaki Mazumder, George I. Haddad	Device and circuit simulation of quantum electronic devices.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
46	Marek A. Bawiec, Maciej Nikodem	Boolean logic function synthesis for generalised threshold gate circuits.	DAC	2009	DBLP DOI BibTeX RDF	GTG, NDR, nanoscale devices, logic synthesis
36	Bharat B. Sukhwani, Uday Padmanabhan, Janet Meiling Wang	Nano-Sim: A Step Wise Equivalent Conductance based Statistical Simulator for Nanotechnology Circuit Design.	DATE	2005	DBLP DOI BibTeX RDF
36	Yuexian Hou, Liyue Yao, Pilian He	Robust Nonlinear Dimension Reduction: A Self-organizing Approach.	FSKD (2)	2005	DBLP DOI BibTeX RDF
36	Wenjing Rao, Alex Orailoglu, Ramesh Karri	Fault Tolerant Arithmetic with Applications in Nanotechnology based Systems.	ITC	2004	DBLP DOI BibTeX RDF
36	Jacques Farré, José Fortes Gálvez	Bounded-Graph Construction for Noncanonical Discriminating-Reverse Parsers.	CIAA	2001	DBLP DOI BibTeX RDF
28	Adrian Kneip, David Bol	A 7T-NDR Dual-Supply 28-nm FD-SOI Ultra-Low Power SRAM With 0.23-nW/kB Sleep Retention and 0.8 pJ/32b Access at 64 MHz With Forward Back Bias.	IEEE Trans. Circuits Syst. I Regul. Pap.	2023	DBLP DOI BibTeX RDF
28	Ravi Kothapally, Vadthiya Narendar, Satish Maheshwaram	NDR free negative capacitance CGAAFET at 2nm technology node for low power and high-speed applications.	Microelectron. J.	2023	DBLP DOI BibTeX RDF
28	Paris Koloveas, Serafeim Chatzopoulos, Christos Tryfonopoulos, Thanasis Vergoulis	BIP! NDR (NoDoiRefs): A Dataset of Citations From Papers Without DOIs in Computer Science Conferences and Workshops.	CoRR	2023	DBLP DOI BibTeX RDF
28	Paris Koloveas, Serafeim Chatzopoulos, Christos Tryfonopoulos, Thanasis Vergoulis	BIP! NDR (NoDoiRefs): A Dataset of Citations from Papers Without DOIs in Computer Science Conferences and Workshops.	TPDL	2023	DBLP DOI BibTeX RDF
28	Rajeewa Kumar Jaisawal, Sunil Rathore, P. N. Kondekar, Navjeet Bagga	Impact of Temperature on NDR Characteristics of a Negative Capacitance FinFET: Role of Landau Parameter (α).	VDAT	2022	DBLP DOI BibTeX RDF
28	M. Sankush Krishna, Sangeeta Singh	Disconnected N-doped zigzag ZnO nanoribbon for potential Negative Differential Resistance (NDR) applications.	Microelectron. J.	2021	DBLP DOI BibTeX RDF
28	Md Sakib Hasan, Aysha S. Shanta, Partha Sarathi Paul 0002, Maisha Sadia, Md. Badruddoja Majumder, Garrett S. Rose	Design of an Enhanced Reconfigurable Chaotic Oscillator using G4FET-NDR Based Discrete Map.	CoRR	2021	DBLP BibTeX RDF
28	Fan Zhao, Cong Jia, Weilian Guo, Sheng Xie, Yan Chen, Clarence Augustine Th Tee, Dongquan Huo, Yanyan Chang, Huaiyan Jiang	Silicon neuron transistor based on CMOS negative differential resistance (NDR).	IEICE Electron. Express	2020	DBLP DOI BibTeX RDF
28	Hao Yu, Chengxu Wang, Xiangshui Miao, Xingsheng Wang	A TCAD-based Study of NDR Effect in NC-FinFET.	ICTA	2020	DBLP DOI BibTeX RDF
28	Mi Lin, Qiao Wu, Weifeng Lyu, Lanye Wang, Luping Li	Design of Multiple-Valued Logic Unit by Using R-HBT-NDR-Based Memristor.	FSDM	2019	DBLP DOI BibTeX RDF
28	Abdallah Sobehy, Eric Renault, Paul Mühlethaler	NDR: Noise and Dimensionality Reduction of CSI for Indoor Positioning Using Deep Learning.	GLOBECOM	2019	DBLP DOI BibTeX RDF
28	Yuezhang Zou, Darshil K. Gala, James A. Bain	Impact Ionization Model for S-NDR based Threshold Switching Devices.	DRC	2019	DBLP DOI BibTeX RDF
28	Navneet Gupta, Adam Makosiej, Andrei Vladimirescu, Amara Amara, Sorin Cotofana, Costin Anghel	TFET NDR skewed inverter based sensing method.	NANOARCH	2016	DBLP DOI BibTeX RDF
28	Alex Lins de Araújo, Luiz Marcio Cysneiros, Vera Werneck	NDR-Tool: Uma Ferramenta de Apoio ao Reuso de Conhecimento em Requisitos Não Funcionais.	CIbSE	2014	DBLP BibTeX RDF
28	Alex Lins de Araújo, Luiz Marcio Cysneiros, Vera Maria Benjamim Werneck	NDR-Tool: Uma Ferramenta de Apoio ao Reuso de Conhecimento em Requisitos Não Funcionais.	WER	2014	DBLP BibTeX RDF
28	Hao Wu, Fabrizio Lombardi, Jie Han 0001	A PCM-based TCAM cell using NDR.	NANOARCH	2013	DBLP DOI BibTeX RDF
28	Juan Núñez 0002, Maria J. Avedillo, José M. Quintana	Bifurcation diagrams in MOS-NDR frequency divider circuits.	ICECS	2012	DBLP DOI BibTeX RDF
28	Juan Núñez 0002, Maria J. Avedillo, José M. Quintana	Compact and Power Efficient MOS-NDR Muller C-Elements.	DoCEIS	2012	DBLP DOI BibTeX RDF
28	Luis Corrons	The rise and rise of NDR.	Netw. Secur.	2010	DBLP DOI BibTeX RDF
28	Juan Núñez 0002, Maria J. Avedillo, José M. Quintana	Single phase MOS-NDR mobile networks.	ISCAS	2010	DBLP DOI BibTeX RDF
28	Juan Núñez 0002, José M. Quintana, Maria J. Avedillo	Fast and Area Efficient Multi-input Muller C-Element based on MOS-NDR.	ISCAS	2009	DBLP DOI BibTeX RDF
28	Claudia López, Luiz Marcio Cysneiros, Hernán Astudillo	NDR Ontology: Sharing and Reusing NFR and Design Rationale Knowledge.	MARK@RE	2008	DBLP DOI BibTeX RDF
28	David Bol, Ilham Hassoune, David Levacq, Denis Flandre, Jean-Didier Legat	Efficient Multiple-Valued Signed-Digit Full Adder Based on NDR MOS Structures and its Application to an N-bit Current-Mode Constant-Time Adder.	J. Multiple Valued Log. Soft Comput.	2007	DBLP BibTeX RDF
28	Sándor Vágvölgyi, Zoltán Fülöp 0001	An infinite hierarchy of tree transformations in the class NDR.	Acta Cybern.	1987	DBLP BibTeX RDF
28	Honggui Li, Xingguo Li	Improved LLE Algorithm for Motion Analysis.	APPT	2007	DBLP DOI BibTeX RDF	NDR, Motion analysis, LLE
28	Tetsuya Uemura, Toshio Baba	Demonstration of a Novel Multiple-Valued T-Gate Using Multiple-Junction Surface Tunnel Transistors and Its Application to Three-Valued Data Flip-Flop.	ISMVL	2000	DBLP DOI BibTeX RDF	tunnel transistor, multiple-valued T-gate, D-FF, NDR
18	Zhengfei Wang, Huaixiu Zheng, Qinwei Shi, Jie Chen 0002	Emerging nanodevice paradigm: Graphene-based electronics for nanoscale computing.	ACM J. Emerg. Technol. Comput. Syst.	2009	DBLP DOI BibTeX RDF	Graphene device, negative differential resistance, tight-binding model, memory structure
18	Marzena Kryszkiewicz	Non-Derivable Item Set and Non-Derivable Literal Set Representations of Patterns Admitting Negation.	DaWaK	2009	DBLP DOI BibTeX RDF
18	Harika Manem, Garrett S. Rose	The effects of logic partitioning in a majority logic based CMOS-NANO FPGA.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	cmos-nano, fpga
18	Yexin Zheng, Chao Huang	Reconfigurable RTD-based circuit elements of complete logic functionality.	ASP-DAC	2008	DBLP DOI BibTeX RDF
18	Harika Manem, Peter C. Paliwoda, Garrett S. Rose	A hybrid cmos/nano fpga architecture built fromprogrammable majority logic arrays.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	PMLA, FPGA, hybrid
18	Krzysztof S. Berezowski, Sarma B. K. Vrudhula	Multiple-Valued Logic Circuits Design Using Negative Differential Resistance Devices.	ISMVL	2007	DBLP DOI BibTeX RDF
18	Carol Minton Morris, Helene Hembrooke, Lynette Rayle	Finding a metaphor for collecting and disseminating distributed NSDL content and communications.	JCDL	2006	DBLP DOI BibTeX RDF
18	Tarik Çakar	A New Neuro-Dominance Rule for Single Machine Tardiness Problem with Unequal Release Dates.	ICANN (2)	2006	DBLP DOI BibTeX RDF	Neuro-dominance rule, weighted tardiness problem, single machine scheduling
18	Bharat B. Sukhwani, Janet Meiling Wang	A stepwise constant conductance approach for simulating resonant tunneling diodes.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
18	Tarik Çakar	A New Neuro-Dominance Rule for Single Machine Tardiness Problem.	ICCSA (4)	2005	DBLP DOI BibTeX RDF
18	Sing-Rong Li, Pinaki Mazumder, Leon O. Chua	On the implementation of RTD based CNNs.	ISCAS (3)	2004	DBLP DOI BibTeX RDF
18	Santanu Mahapatra, Kaustav Banerjee, Florent Pegeon, Adrian M. Ionescu	A CAD Framework for Co-Design and Analysis of CMOS-SET Hybrid Integrated Circuits.	ICCAD	2003	DBLP DOI BibTeX RDF
18	Tetsuya Uemura, Masafumi Yamamoto	Proposal of Four-Valued MRAM based on MTJ/RTD Structure.	ISMVL	2003	DBLP DOI BibTeX RDF
18	Mayukh Bhattacharya, Pinaki Mazumder	Augmentation of SPICE for simulation of circuits containingresonant tunneling diodes.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
18	Mayukh Bhattacharya, Pinaki Mazumder	Convergence Issues in Resonant Tunneling Diode Circuit Simulation.	VLSI Design	2000	DBLP DOI BibTeX RDF	negative differential resistance, convergence, SPICE, circuit simulation, resonant tunneling diode, Newton-Raphson
18	Toshio Baba	Development of Quantum Functional Devices for Multiple-Valued Logic Circuits.	ISMVL	1999	DBLP DOI BibTeX RDF
18	Alejandro F. González, Pinaki Mazumder	Compact Signed-Digit Adder Using Multiple-Valued Logic.	ARVLSI	1997	DBLP DOI BibTeX RDF