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Publication years (Num. hits)
2002-2005 (17) 2006-2007 (21) 2008-2009 (22) 2010-2016 (15) 2019-2021 (3)
Publication types (Num. hits)
article(13) inproceedings(64) phdthesis(1)
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The graphs summarize 67 occurrences of 42 keywords

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Found 78 publication records. Showing 78 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
94Omar A. Al Rayahi, Mohammed A. S. Khalid UWindsor Nios II: A soft-core processor for design space exploration. Search on Bibsonomy EIT The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
94Paul Metzgen A high performance 32-bit ALU for programmable logic. Search on Bibsonomy FPGA The full citation details ... 2004 DBLP  DOI  BibTeX  RDF ALU, Apex 20KE, Nios, FPGA, programmable logic, soft processors
78Willian dos Santos Lima, Renata Spolon Lobato, Aleardo Manacero, Roberta Spolon Ulson Towards a Java bytecodes compiler for Nios II soft-core processor. Search on Bibsonomy ISCC The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
61Eugene Hyun, Mihai Sima, Michael McGuire Reconfigurable Implementation of Wavelet Transform on an Fpga-Augmented NIOS Processor. Search on Bibsonomy CCECE The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
49Franjo Plavec, Blair Fort, Zvonko G. Vranesic, Stephen Dean Brown Experiences with Soft-Core Processor Design. Search on Bibsonomy IPDPS The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
45Abel G. Silva-Filho, Sidney M. L. Lima Energy consumption reduction mechanism by tuning cache configuration usign NIOS II processor. Search on Bibsonomy SoCC The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
45Daniel Etiemble, Samir Bouaziz, Lionel Lacassagne Customizing 16-bit FP Instructions on a NIOS II Processor for FPGA Image and Media Processing. Search on Bibsonomy ESTIMedia The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
45P. Moore, Máire McLoone, Sakir Sezer Reconfigurable Instruction Interface Architecture for Private-Key Cryptography on the Altera Nios-II Processor. Search on Bibsonomy AICT/SAPIR/ELETE The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
45Peter Yiannacouras, J. Gregory Steffan, Jonathan Rose Application-specific customization of soft processor microarchitecture. Search on Bibsonomy FPGA The full citation details ... 2006 DBLP  DOI  BibTeX  RDF Nios, RTL generation, SPREE, FPGA, customization, embedded processor, ASIP, microarchitecture, application specific, soft processor
33Shiuh-Jer Huang, Shian-Shin Wu Vision-Based Robotic Motion Control for Non-autonomous Environment. Search on Bibsonomy J. Intell. Robotic Syst. The full citation details ... 2009 DBLP  DOI  BibTeX  RDF Self-organizing fuzzy control, FPGA chip, Visual servo, Robotic system
33Christian Schäck, Wolfgang Heenes, Rolf Hoffmann A Multiprocessor Architecture with an Omega Network for the Massively Parallel Model GCA. Search on Bibsonomy SAMOS The full citation details ... 2009 DBLP  DOI  BibTeX  RDF Global Cellular Automata, FPGA, multiprocessor architecture, omega network
33Mihai Sima, Michael McGuire Embedded Reconfigurable Solution for OFDM Detection Over Fast Fading Radio Channels. Search on Bibsonomy SiPS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
33Blair Fort, Davor Capalija, Zvonko G. Vranesic, Stephen Dean Brown A Multithreaded Soft Processor for SoPC Area Reduction. Search on Bibsonomy FCCM The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
33Ambrose Chu, Mihai Sima Reconfigurable RSA Cryptography for Embedded Devices. Search on Bibsonomy CCECE The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
33Ian D. L. Anderson, Mohammed A. S. Khalid Design Space Exploration using Parameterized Cores: A Case Study. Search on Bibsonomy CCECE The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
33Ahmed Ben Atitallah, Patrice Kadionik, Fahmi Ghozzi, Patrice Nouel, Nouri Masmoudi, Hervé Levi HW/SW Codesign of the H.263 Video Coder. Search on Bibsonomy CCECE The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
33Siew Kei Lam, Mohammed Shoaib, Thambipillai Srikanthan Modeling Arbitrator Delay-Area Dependencies in Customizable Instruction Set Processors. Search on Bibsonomy DELTA The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
33Maya B. Gokhale, Janette Frigo, Kevin McCabe, James Theiler, Christophe Wolinski, Dominique Lavenier Experience with a Hybrid Processor: K-Means Clustering. Search on Bibsonomy J. Supercomput. The full citation details ... 2003 DBLP  DOI  BibTeX  RDF configurable system on a chip, CSOC, Excalibur, FPGA, image processing, k-means clustering
28Zhong-xun Wang, Kai-yue Sha, Xinglong Gao Digital Image Encryption Test System Based on FPGA and Nios II Soft Core. Search on Bibsonomy Autom. Control. Comput. Sci. The full citation details ... 2021 DBLP  DOI  BibTeX  RDF
28Aleieldin Shamseldin, Hassan Soubra, Reham Elnabawy Performance of DSP operations implemented using a soft microprocessor: a case study based on Nios II. Search on Bibsonomy ICM The full citation details ... 2021 DBLP  DOI  BibTeX  RDF
28Argirios Sideris, Theodora Sanida, Minas Dasygenis Hardware Acceleration of SHA-256 Algorithm Using NIOS-II Processor. Search on Bibsonomy MOCAST The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
28Zouhir Irki, Abdelhai Lati, Samir Sakhi, Abdelkrim Nemra, Mustapha Hamerlain FPGA implementation of the RANSAC based image mosaicing algorithm using the Nios II softcore. Search on Bibsonomy IWSSIP The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
28Naraig Manjikian Retargeting and enhancing a compact multitasking kernel for the Altera Nios II processor. Search on Bibsonomy CCECE The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
28Julio C. Sosa, Iván Dominguez-Lopez, Adrián L. García-García, J. D. Oscar Barceinas-Sánchez, Anuar Jassen Sistema embebido para la detección de luz láser empleando el soft-core Nios II. Search on Bibsonomy Res. Comput. Sci. The full citation details ... 2015 DBLP  BibTeX  RDF
28Chung-Wen Hung, Ke-Cheng Huang, Yan-Ting Yu, Hsuan-Ting Chang A Nios-based colonoscopy navigation system. Search on Bibsonomy Artif. Life Robotics The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
28Diego González 0002, Guillermo Botella, Carlos García 0001, Anke Meyer-Bäse, Uwe Meyer-Bäse, Manuel Prieto-Matías Customized Nios II multi-cycle instructions to accelerate block-matching techniques. Search on Bibsonomy Real-Time Image and Video Processing The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
28Vahid Rashtchi, Mohsen Nourazar A Multiprocessor Nios II Implementation of Duffing oscillator Array for Weak signal Detection. Search on Bibsonomy J. Circuits Syst. Comput. The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
28Trifon Trifonov IP design for DIF, integrated in Nios II systems: averaging filter. Search on Bibsonomy CompSysTech The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
28John M. McNichols, Eric J. Balster, William F. Turri, Kerry L. Hill Design and Implementation of an Embedded NIOS II System for JPEG2000 Tier II Encoding. Search on Bibsonomy Int. J. Reconfigurable Comput. The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
28Diego González 0002, Guillermo Botella, Carlos García 0001, Manuel Prieto 0001, Francisco Tirado Acceleration of block-matching algorithms using a custom instruction-based paradigm on a Nios II microprocessor. Search on Bibsonomy EURASIP J. Adv. Signal Process. The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
28A. D. Voykin, Francis Minhthang Bui, R. J. Bolton FPGA based reconfigurable body area network using Nios II and uClinux. Search on Bibsonomy CCECE The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
28Diego González 0002, Guillermo Botella, Uwe Meyer-Baese, Carlos García 0001, Concepción Sanz, Manuel Prieto-Matías, Francisco Tirado A Low Cost Matching Motion Estimation Sensor Based on the NIOS II Microprocessor. Search on Bibsonomy Sensors The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
28Lucile Senn, Eric Senn, Christian Samoyeau Modelling the Power and Energy Consumption of NIOS II Softcores on FPGA. Search on Bibsonomy CLUSTER Workshops The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
28Tércio A. Santos Filho Desenvolvimento de um nó de rede com diferentes interfaces de acordo com o padrão IEEE 1451 utilizando o processador nios II e o sistema operacional embarcado uclinux. Search on Bibsonomy 2012   RDF
28M. E. Paramasivam, R. S. Sabeenian Handloom Silk Fabric Defect Detection Using First Order Statistical Features on a NIOS II Processor. Search on Bibsonomy ICT The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
28Philipp Digeser, Marco Tubolino, Martin Klemm, Daniel Shapiro, Miodrag Bolic Instruction set extension in the NIOS II: A floating point divider for complex numbers. Search on Bibsonomy CCECE The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
28Hao-Chung Shih, Chian C. Ho Soft DSP Design Methodology of Face Recognition System on Nios II Embedded Platform. Search on Bibsonomy IAS The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
28Haimeng Zhao, Xifeng Zheng, Weiya Liu Intelligent Traffic Control System Based on DSP and Nios II. Search on Bibsonomy CAR The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
28Nivedita N. Joshi, P. K. Dakhole, P. P. Zode Embedded Web Server on Nios II Embedded FPGA Platform. Search on Bibsonomy ICETET The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
28Yang Xu, Min Xiang Design a New Type PWM Peripherals in Nios II. Search on Bibsonomy CSIE (2) The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
28David M. Cambre, Eduardo I. Boemo, Elias Todorovich Arithmetic Operations and Their Energy Consumption in the Nios II Embedded Processor. Search on Bibsonomy ReConFig The full citation details ... 2008 DBLP  DOI  BibTeX  RDF energy evaluation, embedded processor
28Feng Lin, Haili Wang, Jinian Bian HW/SW Interface Synthesis Based on Avalon Bus Specification for Nios-Oriented SoC Design. Search on Bibsonomy FPT The full citation details ... 2005 DBLP  BibTeX  RDF
28Haichen Ren, David Jeff Jackson Morphological Image Processing Using Custom Instructions on Distributed Nios Processors. Search on Bibsonomy CATA The full citation details ... 2004 DBLP  BibTeX  RDF
28Ziting Wang, Cunfang Zheng Research of Image Capturing and Processing System Based on SOPC Technology. Search on Bibsonomy NCM The full citation details ... 2009 DBLP  DOI  BibTeX  RDF System on Programmable Chip, Nios II, Field Programmable Gate Arrays, Image Processing, Image Capturing
28Alex K. Jones, Raymond Hoare, Dara Kusic, Joshua Fazekas, John Foster 0001 An FPGA-based VLIW processor with custom hardware execution. Search on Bibsonomy FPGA The full citation details ... 2005 DBLP  DOI  BibTeX  RDF NIOS, parallelism, compiler, synthesis, kernels, VLIW
28Peter Yiannacouras, Jonathan Rose, J. Gregory Steffan The microarchitecture of FPGA-based soft processors. Search on Bibsonomy CASES The full citation details ... 2005 DBLP  DOI  BibTeX  RDF Nios, RTL generation, SPREE, application specic tradeoff, FPGA, pipeline, exploration, embedded processor, ASIP, microarchitecture, soft processor
16Jason Yu, Christopher Eagleston, Christopher Han-Yu Chou, Maxime Perreault, Guy G. Lemieux Vector Processing as a Soft Processor Accelerator. Search on Bibsonomy ACM Trans. Reconfigurable Technol. Syst. The full citation details ... 2009 DBLP  DOI  BibTeX  RDF parallelism, Computer architecture, embedded processor, vector processor, multimedia processing, soft processor
16G. Seetharaman, B. Venkataramani Automation Schemes for FPGA Implementation of Wave-Pipelined Circuits. Search on Bibsonomy ACM Trans. Reconfigurable Technol. Syst. The full citation details ... 2009 DBLP  DOI  BibTeX  RDF FPGA, pipelining, SOC, CORDIC, wave-pipelining, DAA
16Michael Dyer, Saeid Nooshabadi, David S. Taubman Design and Analysis of System on a Chip Encoder for JPEG2000. Search on Bibsonomy IEEE Trans. Circuits Syst. Video Technol. The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
16Hui-Ya Li, Wen-Jyi Hwang, Chih-Chieh Hsu, Chia-Lung Hung Efficient K-Means VLSI Architecture for Vector Quantization. Search on Bibsonomy SCIA The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
16Chi-Tai Cheng, Yu-Ting Yang, Shih-Heng Miao, Ching-Chang Wong Motion and Emotional Behavior Design for Pet Robot Dog. Search on Bibsonomy FIRA The full citation details ... 2009 DBLP  DOI  BibTeX  RDF Robot Dog, Emotional Behavior
16Yu-Te Su, Chun-Yang Hu, Tzuu-Hseng S. Li FPGA-Based Vocabulary Recognition Module for Humanoid Robot. Search on Bibsonomy FIRA The full citation details ... 2009 DBLP  DOI  BibTeX  RDF FPGA-based, humanoid robot
16Hui-Ya Li, Yao-Jung Yeh, Wen-Jyi Hwang, Cheng-Tsun Yang High Speed k-Winner-Take-ALL Competitive Learning in Reconfigurable Hardware. Search on Bibsonomy IEA/AIE The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
16Pierre-Alain Fouque, Gaëtan Leurent, Denis Réal, Frédéric Valette Practical Electromagnetic Template Attack on HMAC. Search on Bibsonomy CHES The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
16Jason Yu, Guy G. Lemieux, Christopher Eagleston Vector processing as a soft-core CPU accelerator. Search on Bibsonomy FPGA The full citation details ... 2008 DBLP  DOI  BibTeX  RDF C2H, FPGA, configurable, embedded processor, application specific, soft processor, data-level parallelism
16Yvan Eustache, Jean-Philippe Diguet Specification and OS-based implementation of self-adaptive, hardware/software embedded systems. Search on Bibsonomy CODES+ISSS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF self-adaptive embedded systems, HW/SW codesign
16Ce Li, Yang Jiang, Zhenyu Wu, Takahiro Watanabe A Multiprocessor System for a Small Size Soccer Robot Control System. Search on Bibsonomy DELTA The full citation details ... 2008 DBLP  DOI  BibTeX  RDF MP, FPGA, multiprocessor, soccer robot
16Peter Yiannacouras, J. Gregory Steffan, Jonathan Rose Exploration and Customization of FPGA-Based Soft Processors. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
16Michael Dyer, Saeid Nooshabadi, David S. Taubman Analysis of Multiple Parallel Block Coding in JPEG2000. Search on Bibsonomy ICIP (5) The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
16Ari Kulmala, Erno Salminen, Timo D. Hämäläinen Evaluating Large System-on-Chip on Multi-FPGA Platform. Search on Bibsonomy SAMOS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
16Stevan M. Bererber, Chih-Hong Wang, Kevin K. Wei Design of a CDMA System in FPGA Technology. Search on Bibsonomy VTC Spring The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
16Gerald Hempel, Christian Hochberger A resource optimized Processor Core for FPGA based SoCs. Search on Bibsonomy DSD The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
16Jordana L. Seixas, Edson Barbosa, Stelita M. da Silva, Paulo Sérgio B. do Nascimento, Vinícius Kursancew, Remy Eskinazi Sant'Anna, Edna Barros, Manoel Eusébio de Lima Aquarius: a dynamically reconfigurable computing platform. Search on Bibsonomy SBCCI The full citation details ... 2007 DBLP  DOI  BibTeX  RDF ?CLinux, FPGAs, prototyping, dynamic reconfiguration, tasks scheduling, device driver, bitstream
16Zhonghai Lu, Jonas Sicking, Ingo Sander, Axel Jantsch Using Synchronizers for Refining Synchronous Communication onto Hardware/Software Architectures. Search on Bibsonomy IEEE International Workshop on Rapid System Prototyping The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
16V. Amudha, B. Venkataramani, R. Vinoth Kumar, S. Ravishankar SOC Implementation of HMM Based Speaker Independent Isolated Digit Recognition System. Search on Bibsonomy VLSI Design The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
16Erwan Piriou, Christophe Jégo, Patrick Adde, Michel Jézéquel A Flexible Architecture For Block Turbo Decoders Using BCH Or Reed-Solomon Components Codes. Search on Bibsonomy ISVLSI The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
16Tero Arpinen, Petri Kukkala, Erno Salminen, Marko Hännikäinen, Timo D. Hämäläinen Configurable multiprocessor platform with RTOS for distributed execution of UML 2.0 designed applications. Search on Bibsonomy DATE The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
16Erwan Piriou, Christophe Jégo, Patrick Adde, Raphaël Le Bidan, Michel Jézéquel Efficient architecture for Reed Solomon block turbo code. Search on Bibsonomy ISCAS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
16Martin Simka, Milos Drutarovský, Viktor Fischer, J. Fayolle Model of a true random number generator aimed at cryptographic applications. Search on Bibsonomy ISCAS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
16Adriel Cheng, Atanas N. Parashkevov, Cheng-Chew Lim Coverage Measurement for Software Application Testing using Partially Ordered Domains and Symbolic Trajectory Evaluation Techniques. Search on Bibsonomy DELTA The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
16Jing Ma 0006, Xinming Huang 0001 A System-on-Programmable Chip Approach for MIMO Sphere Decoder. Search on Bibsonomy FCCM The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
16H. G. Epassa, François R. Boyer, Yvon Savaria Implementation of a cycle by cycle variable speed processor. Search on Bibsonomy ISCAS (4) The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
16Jason Cong, Yiping Fan, Guoling Han, Zhiru Zhang Application-specific instruction generation for configurable processor architectures. Search on Bibsonomy FPGA The full citation details ... 2004 DBLP  DOI  BibTeX  RDF binate covering, compilation, ASIP, technology mapping, configurable processor
16Jian Liang, Russell Tessier, Dennis Goeckel A Dynamically-Reconfigurable, Power-Efficient Turbo Decoder. Search on Bibsonomy FCCM The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
16Deepak Boppana, Kully Dhanoa, Jesse Kempa FPGA based Embedded Processing Architecture for the QRD-RLS Algorithm. Search on Bibsonomy FCCM The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
16Martin Simka, Viktor Fischer, Milos Drutarovský Hardware-Software Codesign in Embedded Asymmetric Cryptographiy Application - A Case Study. Search on Bibsonomy FPL The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
16Manev Luthra, Sumit Gupta, Nikil D. Dutt, Rajesh K. Gupta 0001, Alexandru Nicolau Interface Synthesis using Memory Mapping for an FPGA Platform. Search on Bibsonomy ICCD The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
16Sylvain Poussier, Hassan Rabah, Serge Weber SOPC-based Embedded Smart Strain Gage Sensor. Search on Bibsonomy FPL The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
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