Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
94 | Omar A. Al Rayahi, Mohammed A. S. Khalid |
UWindsor Nios II: A soft-core processor for design space exploration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EIT ![In: 2009 IEEE International Conference on Electro/Information Technology, EIT 2009, Windsor, Ontario, Canada, June 7-9, 2009, pp. 451-457, 2009, IEEE, 978-1-4244-3355-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
94 | Paul Metzgen |
A high performance 32-bit ALU for programmable logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, FPGA 2004, Monterey, California, USA, February 22-24, 2004, pp. 61-70, 2004, ACM, 1-58113-829-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
ALU, Apex 20KE, Nios, FPGA, programmable logic, soft processors |
78 | Willian dos Santos Lima, Renata Spolon Lobato, Aleardo Manacero, Roberta Spolon Ulson |
Towards a Java bytecodes compiler for Nios II soft-core processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCC ![In: Proceedings of the 14th IEEE Symposium on Computers and Communications (ISCC 2009), July 5-8, Sousse, Tunisia, pp. 104-109, 2009, IEEE Computer Society, 978-1-4244-4672-8. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
61 | Eugene Hyun, Mihai Sima, Michael McGuire |
Reconfigurable Implementation of Wavelet Transform on an Fpga-Augmented NIOS Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCECE ![In: Proceedings of the Canadian Conference on Electrical and Computer Engineering, CCECE 2006, May 7-10, 2006, Ottawa Congress Centre, Ottawa, Canada, pp. 1052-1055, 2006, IEEE, 1-4244-0038-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
49 | Franjo Plavec, Blair Fort, Zvonko G. Vranesic, Stephen Dean Brown |
Experiences with Soft-Core Processor Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), CD-ROM / Abstracts Proceedings, 4-8 April 2005, Denver, CO, USA, 2005, IEEE Computer Society, 0-7695-2312-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
45 | Abel G. Silva-Filho, Sidney M. L. Lima |
Energy consumption reduction mechanism by tuning cache configuration usign NIOS II processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SoCC ![In: 21st Annual IEEE International SoC Conference, SoCC 2008, September 17-20, 2008, Radisson Hotel, Newport Beach, CA, USA, Proceedings, pp. 291-294, 2008, IEEE, 978-1-4244-2596-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
45 | Daniel Etiemble, Samir Bouaziz, Lionel Lacassagne |
Customizing 16-bit FP Instructions on a NIOS II Processor for FPGA Image and Media Processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESTIMedia ![In: Proceedings of the 2005 3rd Workshop on Embedded Systems for Real-Time Multimedia, ESTIMedia 2005, September 22-23, 2005, New York Metropolitan Area, USA, pp. 61-66, 2005, IEEE Computer Society, 0-7803-9347-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
45 | P. Moore, Máire McLoone, Sakir Sezer |
Reconfigurable Instruction Interface Architecture for Private-Key Cryptography on the Altera Nios-II Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AICT/SAPIR/ELETE ![In: Telecommunications 2005: Advanced Industrial Conference on Telecommunications / Service Assurance with Partial and Intermittent Resources Conference / E-Learning on Telecommunications Workshop (AICT / SAPIR / ELETE 2005), 17-22 July 2005, Lisbon, Portugal, pp. 296-299, 2005, IEEE Computer Society, 0-7695-2388-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
45 | Peter Yiannacouras, J. Gregory Steffan, Jonathan Rose |
Application-specific customization of soft processor microarchitecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, FPGA 2006, Monterey, California, USA, February 22-24, 2006, pp. 201-210, 2006, ACM, 1-59593-292-5. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Nios, RTL generation, SPREE, FPGA, customization, embedded processor, ASIP, microarchitecture, application specific, soft processor |
33 | Shiuh-Jer Huang, Shian-Shin Wu |
Vision-Based Robotic Motion Control for Non-autonomous Environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Intell. Robotic Syst. ![In: J. Intell. Robotic Syst. 54(5), pp. 733-754, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Self-organizing fuzzy control, FPGA chip, Visual servo, Robotic system |
33 | Christian Schäck, Wolfgang Heenes, Rolf Hoffmann |
A Multiprocessor Architecture with an Omega Network for the Massively Parallel Model GCA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAMOS ![In: Embedded Computer Systems: Architectures, Modeling, and Simulation, 9th International Workshop, SAMOS 2009, Samos, Greece, July 20-23, 2009. Proceedings, pp. 98-107, 2009, Springer, 978-3-642-03137-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Global Cellular Automata, FPGA, multiprocessor architecture, omega network |
33 | Mihai Sima, Michael McGuire |
Embedded Reconfigurable Solution for OFDM Detection Over Fast Fading Radio Channels. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SiPS ![In: Proceedings of the IEEE Workshop on Signal Processing Systems, SiPS 2007, Proceedings, October 17-19, 2007, Eton Hotel, Shanghai, China, pp. 13-18, 2007, IEEE, 1-4244-1222-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
33 | Blair Fort, Davor Capalija, Zvonko G. Vranesic, Stephen Dean Brown |
A Multithreaded Soft Processor for SoPC Area Reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 14th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2006), 24-26 April 2006, Napa, CA, USA, Proceedings, pp. 131-142, 2006, IEEE Computer Society, 0-7695-2661-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
33 | Ambrose Chu, Mihai Sima |
Reconfigurable RSA Cryptography for Embedded Devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCECE ![In: Proceedings of the Canadian Conference on Electrical and Computer Engineering, CCECE 2006, May 7-10, 2006, Ottawa Congress Centre, Ottawa, Canada, pp. 1312-1315, 2006, IEEE, 1-4244-0038-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
33 | Ian D. L. Anderson, Mohammed A. S. Khalid |
Design Space Exploration using Parameterized Cores: A Case Study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCECE ![In: Proceedings of the Canadian Conference on Electrical and Computer Engineering, CCECE 2006, May 7-10, 2006, Ottawa Congress Centre, Ottawa, Canada, pp. 1893-1896, 2006, IEEE, 1-4244-0038-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
33 | Ahmed Ben Atitallah, Patrice Kadionik, Fahmi Ghozzi, Patrice Nouel, Nouri Masmoudi, Hervé Levi |
HW/SW Codesign of the H.263 Video Coder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCECE ![In: Proceedings of the Canadian Conference on Electrical and Computer Engineering, CCECE 2006, May 7-10, 2006, Ottawa Congress Centre, Ottawa, Canada, pp. 783-787, 2006, IEEE, 1-4244-0038-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
33 | Siew Kei Lam, Mohammed Shoaib, Thambipillai Srikanthan |
Modeling Arbitrator Delay-Area Dependencies in Customizable Instruction Set Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA 2006), 17-19 January 2006, Kuala Lumpur, Malaysia, pp. 237-242, 2006, IEEE Computer Society, 0-7695-2500-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
33 | Maya B. Gokhale, Janette Frigo, Kevin McCabe, James Theiler, Christophe Wolinski, Dominique Lavenier |
Experience with a Hybrid Processor: K-Means Clustering. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Supercomput. ![In: J. Supercomput. 26(2), pp. 131-148, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
configurable system on a chip, CSOC, Excalibur, FPGA, image processing, k-means clustering |
28 | Zhong-xun Wang, Kai-yue Sha, Xinglong Gao |
Digital Image Encryption Test System Based on FPGA and Nios II Soft Core. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Autom. Control. Comput. Sci. ![In: Autom. Control. Comput. Sci. 55(5), pp. 490-499, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
28 | Aleieldin Shamseldin, Hassan Soubra, Reham Elnabawy |
Performance of DSP operations implemented using a soft microprocessor: a case study based on Nios II. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICM ![In: International Conference on Microelectronics, ICM 2021, New Cairo City, Egypt, December 19-22, 2021, pp. 66-69, 2021, IEEE, 978-1-6654-0839-4. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
28 | Argirios Sideris, Theodora Sanida, Minas Dasygenis |
Hardware Acceleration of SHA-256 Algorithm Using NIOS-II Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MOCAST ![In: 8th International Conference on Modern Circuits and Systems Technologies, MOCAST 2019, Thessaloniki, Greece, May 13-15, 2019, pp. 1-4, 2019, IEEE, 978-1-7281-1184-1. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
28 | Zouhir Irki, Abdelhai Lati, Samir Sakhi, Abdelkrim Nemra, Mustapha Hamerlain |
FPGA implementation of the RANSAC based image mosaicing algorithm using the Nios II softcore. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IWSSIP ![In: International Conference on Systems, Signals and Image Processing, IWSSIP 2016, Bratislava, Slovakia, May 23-25, 2016, pp. 1-4, 2016, IEEE, 978-1-4673-9555-7. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
28 | Naraig Manjikian |
Retargeting and enhancing a compact multitasking kernel for the Altera Nios II processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCECE ![In: 2016 IEEE Canadian Conference on Electrical and Computer Engineering, CCECE 2016, Vancouver, BC, Canada, May 15-18, 2016, pp. 1-5, 2016, IEEE, 978-1-4673-8721-7. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
28 | Julio C. Sosa, Iván Dominguez-Lopez, Adrián L. García-García, J. D. Oscar Barceinas-Sánchez, Anuar Jassen |
Sistema embebido para la detección de luz láser empleando el soft-core Nios II. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Res. Comput. Sci. ![In: Res. Comput. Sci. 107, pp. 121-132, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP BibTeX RDF |
|
28 | Chung-Wen Hung, Ke-Cheng Huang, Yan-Ting Yu, Hsuan-Ting Chang |
A Nios-based colonoscopy navigation system. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Artif. Life Robotics ![In: Artif. Life Robotics 20(3), pp. 222-227, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
28 | Diego González 0002, Guillermo Botella, Carlos García 0001, Anke Meyer-Bäse, Uwe Meyer-Bäse, Manuel Prieto-Matías |
Customized Nios II multi-cycle instructions to accelerate block-matching techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Real-Time Image and Video Processing ![In: Real-Time Image and Video Processing 2015, San Francisco, CA, USA, February 10, 2015, pp. 940002, 2015, SPIE, 978-1-6284-1490-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
28 | Vahid Rashtchi, Mohsen Nourazar |
A Multiprocessor Nios II Implementation of Duffing oscillator Array for Weak signal Detection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 23(4), 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
28 | Trifon Trifonov |
IP design for DIF, integrated in Nios II systems: averaging filter. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CompSysTech ![In: Proceedings of the 15th International Conference on Computer Systems and Technologies, CompSysTech '14, Ruse, Bulgaria, June 27-28, 2014, pp. 55-62, 2014, ACM, 978-1-4503-2753-4. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
28 | John M. McNichols, Eric J. Balster, William F. Turri, Kerry L. Hill |
Design and Implementation of an Embedded NIOS II System for JPEG2000 Tier II Encoding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Reconfigurable Comput. ![In: Int. J. Reconfigurable Comput. 2013, pp. 140234:1-140234:9, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
28 | Diego González 0002, Guillermo Botella, Carlos García 0001, Manuel Prieto 0001, Francisco Tirado |
Acceleration of block-matching algorithms using a custom instruction-based paradigm on a Nios II microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EURASIP J. Adv. Signal Process. ![In: EURASIP J. Adv. Signal Process. 2013, pp. 118, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
28 | A. D. Voykin, Francis Minhthang Bui, R. J. Bolton |
FPGA based reconfigurable body area network using Nios II and uClinux. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCECE ![In: 26th IEEE Canadian Conference on Electrical and Computer Engineering CCECE 2013, Regina, SK, Canada, May 5-8, 2013, pp. 1-4, 2013, IEEE, 978-1-4799-0031-2. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
28 | Diego González 0002, Guillermo Botella, Uwe Meyer-Baese, Carlos García 0001, Concepción Sanz, Manuel Prieto-Matías, Francisco Tirado |
A Low Cost Matching Motion Estimation Sensor Based on the NIOS II Microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Sensors ![In: Sensors 12(10), pp. 13126-13149, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
28 | Lucile Senn, Eric Senn, Christian Samoyeau |
Modelling the Power and Energy Consumption of NIOS II Softcores on FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CLUSTER Workshops ![In: 2012 IEEE International Conference on Cluster Computing Workshops, CLUSTER Workshops 2012, Beijing, China, September 24-28, 2012, pp. 179-183, 2012, IEEE Computer Society, 978-1-4673-2893-7. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
28 | Tércio A. Santos Filho |
Desenvolvimento de um nó de rede com diferentes interfaces de acordo com o padrão IEEE 1451 utilizando o processador nios II e o sistema operacional embarcado uclinux. ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2012 |
RDF |
|
28 | M. E. Paramasivam, R. S. Sabeenian |
Handloom Silk Fabric Defect Detection Using First Order Statistical Features on a NIOS II Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICT ![In: Information and Communication Technologies - International Conference, ICT 2010, Kochi, Kerala, India, September 7-9, 2010. Proceedings, pp. 475-477, 2010, Springer, 978-3-642-15765-3. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
28 | Philipp Digeser, Marco Tubolino, Martin Klemm, Daniel Shapiro, Miodrag Bolic |
Instruction set extension in the NIOS II: A floating point divider for complex numbers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCECE ![In: Proceedings of the 23rd Canadian Conference on Electrical and Computer Engineering, CCECE 2010, Calgary, Alberta, Canada, 2-5 May, 2010, pp. 1-5, 2010, IEEE, 978-1-4244-5376-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
28 | Hao-Chung Shih, Chian C. Ho |
Soft DSP Design Methodology of Face Recognition System on Nios II Embedded Platform. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IAS ![In: Proceedings of the Fifth International Conference on Information Assurance and Security, IAS 2009, Xi'An, China, 18-20 August 2009, pp. 753-756, 2009, IEEE Computer Society, 978-0-7695-3744-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
28 | Haimeng Zhao, Xifeng Zheng, Weiya Liu |
Intelligent Traffic Control System Based on DSP and Nios II. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAR ![In: 2009 International Asia Conference on Informatics in Control, Automation and Robotics, CAR 2009, Bangkok, Thailand, 1-2 February 2009, pp. 90-94, 2009, IEEE Computer Society, 978-0-7695-3519-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
28 | Nivedita N. Joshi, P. K. Dakhole, P. P. Zode |
Embedded Web Server on Nios II Embedded FPGA Platform. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICETET ![In: Proceedings of the Second International Conference on Emerging Trends in Engineering & Technology, ICETET 2009, Nagpur, Maharashtra, India, 16-18 December 2009, pp. 372-377, 2009, IEEE Computer Society, 978-0-7695-3884-6. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
28 | Yang Xu, Min Xiang |
Design a New Type PWM Peripherals in Nios II. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CSIE (2) ![In: CSIE 2009, 2009 WRI World Congress on Computer Science and Information Engineering, March 31 - April 2, 2009, Los Angeles, California, USA, 7 Volumes, pp. 442-446, 2009, IEEE Computer Society, 978-0-7695-3507-4. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
28 | David M. Cambre, Eduardo I. Boemo, Elias Todorovich |
Arithmetic Operations and Their Energy Consumption in the Nios II Embedded Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ReConFig ![In: ReConFig'08: 2008 International Conference on Reconfigurable Computing and FPGAs, 3-5 December 2008, Cancun, Mexico, Proceedings, pp. 151-156, 2008, IEEE Computer Society, 978-0-7695-3474-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
energy evaluation, embedded processor |
28 | Feng Lin, Haili Wang, Jinian Bian |
HW/SW Interface Synthesis Based on Avalon Bus Specification for Nios-Oriented SoC Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPT ![In: Proceedings of the 2005 IEEE International Conference on Field-Programmable Technology, FPT 2005, 11-14 December 2005, Singapore, pp. 305-306, 2005, IEEE, 0-7803-9407-0. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP BibTeX RDF |
|
28 | Haichen Ren, David Jeff Jackson |
Morphological Image Processing Using Custom Instructions on Distributed Nios Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CATA ![In: 19th International Conference on Computers and Their Applications, CATA 2004, March 18-20, 2004, Red Lion Hotel on Fifth Avenue, Seattle, Washington, USA, pp. 25-28, 2004, ISCA, 1-880843-50-1. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP BibTeX RDF |
|
28 | Ziting Wang, Cunfang Zheng |
Research of Image Capturing and Processing System Based on SOPC Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NCM ![In: International Conference on Networked Computing and Advanced Information Management, NCM 2009, Fifth International Joint Conference on INC, IMS and IDC: INC 2009: International Conference on Networked Computing, IMS 2009: International Conference on Advanced Information Management and Service, IDC 2009: International Conference on Digital Content, Multimedia Technology and its Applications, Seoul, Korea, August 25-27, 2009, pp. 1733-1736, 2009, IEEE Computer Society, 978-0-7695-3769-6. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
System on Programmable Chip, Nios II, Field Programmable Gate Arrays, Image Processing, Image Capturing |
28 | Alex K. Jones, Raymond Hoare, Dara Kusic, Joshua Fazekas, John Foster 0001 |
An FPGA-based VLIW processor with custom hardware execution. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, FPGA 2005, Monterey, California, USA, February 20-22, 2005, pp. 107-117, 2005, ACM, 1-59593-029-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
NIOS, parallelism, compiler, synthesis, kernels, VLIW |
28 | Peter Yiannacouras, Jonathan Rose, J. Gregory Steffan |
The microarchitecture of FPGA-based soft processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2005 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2005, San Francisco, California, USA, September 24-27, 2005, pp. 202-212, 2005, ACM, 1-59593-149-X. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Nios, RTL generation, SPREE, application specic tradeoff, FPGA, pipeline, exploration, embedded processor, ASIP, microarchitecture, soft processor |
16 | Jason Yu, Christopher Eagleston, Christopher Han-Yu Chou, Maxime Perreault, Guy G. Lemieux |
Vector Processing as a Soft Processor Accelerator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Reconfigurable Technol. Syst. ![In: ACM Trans. Reconfigurable Technol. Syst. 2(2), pp. 12:1-12:34, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
parallelism, Computer architecture, embedded processor, vector processor, multimedia processing, soft processor |
16 | G. Seetharaman, B. Venkataramani |
Automation Schemes for FPGA Implementation of Wave-Pipelined Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Reconfigurable Technol. Syst. ![In: ACM Trans. Reconfigurable Technol. Syst. 2(2), pp. 11:1-11:19, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
FPGA, pipelining, SOC, CORDIC, wave-pipelining, DAA |
16 | Michael Dyer, Saeid Nooshabadi, David S. Taubman |
Design and Analysis of System on a Chip Encoder for JPEG2000. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. Video Technol. ![In: IEEE Trans. Circuits Syst. Video Technol. 19(2), pp. 215-225, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
16 | Hui-Ya Li, Wen-Jyi Hwang, Chih-Chieh Hsu, Chia-Lung Hung |
Efficient K-Means VLSI Architecture for Vector Quantization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SCIA ![In: Image Analysis, 16th Scandinavian Conference, SCIA 2009, Oslo, Norway, June 15-18, 2009. Proceedings, pp. 440-449, 2009, Springer, 978-3-642-02229-6. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
16 | Chi-Tai Cheng, Yu-Ting Yang, Shih-Heng Miao, Ching-Chang Wong |
Motion and Emotional Behavior Design for Pet Robot Dog. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FIRA ![In: Advances in Robotics, FIRA RoboWorld Congress 2009, Incheon, Korea, August 16-20, 2009. Proceedings, pp. 13-22, 2009, Springer, 978-3-642-03982-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Robot Dog, Emotional Behavior |
16 | Yu-Te Su, Chun-Yang Hu, Tzuu-Hseng S. Li |
FPGA-Based Vocabulary Recognition Module for Humanoid Robot. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FIRA ![In: Advances in Robotics, FIRA RoboWorld Congress 2009, Incheon, Korea, August 16-20, 2009. Proceedings, pp. 151-160, 2009, Springer, 978-3-642-03982-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
FPGA-based, humanoid robot |
16 | Hui-Ya Li, Yao-Jung Yeh, Wen-Jyi Hwang, Cheng-Tsun Yang |
High Speed k-Winner-Take-ALL Competitive Learning in Reconfigurable Hardware. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEA/AIE ![In: Next-Generation Applied Intelligence, 22nd International Conference on Industrial, Engineering and Other Applications of Applied Intelligent Systems, IEA/AIE 2009, Tainan, Taiwan, June 24-27, 2009. Proceedings, pp. 594-603, 2009, Springer, 978-3-642-02567-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
16 | Pierre-Alain Fouque, Gaëtan Leurent, Denis Réal, Frédéric Valette |
Practical Electromagnetic Template Attack on HMAC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHES ![In: Cryptographic Hardware and Embedded Systems - CHES 2009, 11th International Workshop, Lausanne, Switzerland, September 6-9, 2009, Proceedings, pp. 66-80, 2009, Springer, 978-3-642-04137-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
16 | Jason Yu, Guy G. Lemieux, Christopher Eagleston |
Vector processing as a soft-core CPU accelerator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 16th International Symposium on Field Programmable Gate Arrays, FPGA 2008, Monterey, California, USA, February 24-26, 2008, pp. 222-232, 2008, ACM, 978-1-59593-934-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
C2H, FPGA, configurable, embedded processor, application specific, soft processor, data-level parallelism |
16 | Yvan Eustache, Jean-Philippe Diguet |
Specification and OS-based implementation of self-adaptive, hardware/software embedded systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 6th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2008, Atlanta, GA, USA, October 19-24, 2008, pp. 67-72, 2008, ACM, 978-1-60558-470-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
self-adaptive embedded systems, HW/SW codesign |
16 | Ce Li, Yang Jiang, Zhenyu Wu, Takahiro Watanabe |
A Multiprocessor System for a Small Size Soccer Robot Control System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008, Hong Kong, January 23-25, 2008, pp. 115-118, 2008, IEEE Computer Society, 978-0-7695-3110-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
MP, FPGA, multiprocessor, soccer robot |
16 | Peter Yiannacouras, J. Gregory Steffan, Jonathan Rose |
Exploration and Customization of FPGA-Based Soft Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(2), pp. 266-277, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
16 | Michael Dyer, Saeid Nooshabadi, David S. Taubman |
Analysis of Multiple Parallel Block Coding in JPEG2000. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICIP (5) ![In: Proceedings of the International Conference on Image Processing, ICIP 2007, September 16-19, 2007, San Antonio, Texas, USA, pp. 173-176, 2007, IEEE, 978-1-4244-1436-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
16 | Ari Kulmala, Erno Salminen, Timo D. Hämäläinen |
Evaluating Large System-on-Chip on Multi-FPGA Platform. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAMOS ![In: Embedded Computer Systems: Architectures, Modeling, and Simulation, 7th International Workshop, SAMOS 2007, Samos, Greece, July 16-19, 2007, Proceedings, pp. 179-189, 2007, Springer, 978-3-540-73622-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
16 | Stevan M. Bererber, Chih-Hong Wang, Kevin K. Wei |
Design of a CDMA System in FPGA Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTC Spring ![In: Proceedings of the 65th IEEE Vehicular Technology Conference, VTC Spring 2007, 22-25 April 2007, Dublin, Ireland, pp. 3061-3065, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
16 | Gerald Hempel, Christian Hochberger |
A resource optimized Processor Core for FPGA based SoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: Tenth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2007), 29-31 August 2007, Lübeck, Germany, pp. 51-58, 2007, IEEE Computer Society, 0-7695-2978-X. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
16 | Jordana L. Seixas, Edson Barbosa, Stelita M. da Silva, Paulo Sérgio B. do Nascimento, Vinícius Kursancew, Remy Eskinazi Sant'Anna, Edna Barros, Manoel Eusébio de Lima |
Aquarius: a dynamically reconfigurable computing platform. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2007, Copacabana, Rio de Janeiro, Brazil, September 3-6, 2007, pp. 171-176, 2007, ACM, 978-1-59593-816-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
?CLinux, FPGAs, prototyping, dynamic reconfiguration, tasks scheduling, device driver, bitstream |
16 | Zhonghai Lu, Jonas Sicking, Ingo Sander, Axel Jantsch |
Using Synchronizers for Refining Synchronous Communication onto Hardware/Software Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE International Workshop on Rapid System Prototyping ![In: 18th IEEE International Workshop on Rapid System Prototyping (RSP 2007), 28-30 May 2007, Porto Alegre, RS, Brazil, pp. 143-149, 2007, IEEE Computer Society, 978-0-7695-2834-2. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
16 | V. Amudha, B. Venkataramani, R. Vinoth Kumar, S. Ravishankar |
SOC Implementation of HMM Based Speaker Independent Isolated Digit Recognition System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 20th International Conference on VLSI Design (VLSI Design 2007), Sixth International Conference on Embedded Systems (ICES 2007), 6-10 January 2007, Bangalore, India, pp. 848-853, 2007, IEEE Computer Society, 0-7695-2762-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
16 | Erwan Piriou, Christophe Jégo, Patrick Adde, Michel Jézéquel |
A Flexible Architecture For Block Turbo Decoders Using BCH Or Reed-Solomon Components Codes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2-3 March 2006, Karlsruhe, Germany, pp. 430-431, 2006, IEEE Computer Society, 0-7695-2533-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
16 | Tero Arpinen, Petri Kukkala, Erno Salminen, Marko Hännikäinen, Timo D. Hämäläinen |
Configurable multiprocessor platform with RTOS for distributed execution of UML 2.0 designed applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006, pp. 1324-1329, 2006, European Design and Automation Association, Leuven, Belgium, 3-9810801-1-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
16 | Erwan Piriou, Christophe Jégo, Patrick Adde, Raphaël Le Bidan, Michel Jézéquel |
Efficient architecture for Reed Solomon block turbo code. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
16 | Martin Simka, Milos Drutarovský, Viktor Fischer, J. Fayolle |
Model of a true random number generator aimed at cryptographic applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
16 | Adriel Cheng, Atanas N. Parashkevov, Cheng-Chew Lim |
Coverage Measurement for Software Application Testing using Partially Ordered Domains and Symbolic Trajectory Evaluation Techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA 2006), 17-19 January 2006, Kuala Lumpur, Malaysia, pp. 481-487, 2006, IEEE Computer Society, 0-7695-2500-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
16 | Jing Ma 0006, Xinming Huang 0001 |
A System-on-Programmable Chip Approach for MIMO Sphere Decoder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 13th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2005), 17-20 April 2005, Napa, CA, USA, Proceedings, pp. 317-318, 2005, IEEE Computer Society, 0-7695-2445-1. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
16 | H. G. Epassa, François R. Boyer, Yvon Savaria |
Implementation of a cycle by cycle variable speed processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 3335-3338, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
16 | Jason Cong, Yiping Fan, Guoling Han, Zhiru Zhang |
Application-specific instruction generation for configurable processor architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, FPGA 2004, Monterey, California, USA, February 22-24, 2004, pp. 183-189, 2004, ACM, 1-58113-829-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
binate covering, compilation, ASIP, technology mapping, configurable processor |
16 | Jian Liang, Russell Tessier, Dennis Goeckel |
A Dynamically-Reconfigurable, Power-Efficient Turbo Decoder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 12th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2004), 20-23 April 2004, Napa, CA, USA, Proceedings, pp. 91-100, 2004, IEEE Computer Society, 0-7695-2230-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
16 | Deepak Boppana, Kully Dhanoa, Jesse Kempa |
FPGA based Embedded Processing Architecture for the QRD-RLS Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 12th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2004), 20-23 April 2004, Napa, CA, USA, Proceedings, pp. 330-331, 2004, IEEE Computer Society, 0-7695-2230-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
16 | Martin Simka, Viktor Fischer, Milos Drutarovský |
Hardware-Software Codesign in Embedded Asymmetric Cryptographiy Application - A Case Study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field Programmable Logic and Application, 13th International Conference, FPL 2003, Lisbon, Portugal, September 1-3, 2003, Proceedings, pp. 1075-1078, 2003, Springer, 3-540-40822-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
16 | Manev Luthra, Sumit Gupta, Nikil D. Dutt, Rajesh K. Gupta 0001, Alexandru Nicolau |
Interface Synthesis using Memory Mapping for an FPGA Platform. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 21st International Conference on Computer Design (ICCD 2003),VLSI in Computers and Processors, 13-15 October 2003, San Jose, CA, USA, Proceedings, pp. 140-145, 2003, IEEE Computer Society, 0-7695-2025-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
16 | Sylvain Poussier, Hassan Rabah, Serge Weber |
SOPC-based Embedded Smart Strain Gage Sensor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, Reconfigurable Computing Is Going Mainstream, 12th International Conference, FPL 2002, Montpellier, France, September 2-4, 2002, Proceedings, pp. 1131-1134, 2002, Springer, 3-540-44108-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|