Search results for "PRPG"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
115	Ahmad A. Al-Yamani, Subhasish Mitra, Edward J. McCluskey	Optimized reseeding by seed ordering and encoding.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
91	Sukanta Das, Hafizur Rahaman 0001, Biplab K. Sikdar	Cost Optimal Design of Nonlinear CA based PRPG for Test Applications.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
91	Sukanta Das, Debdas Dey, Subhayan Sen, Biplab K. Sikdar, Parimal Pal Chaudhuri	An efficient design of non-linear CA based PRPG for VLSI circuit testing.	ASP-DAC	2004	DBLP DOI BibTeX RDF
77	Sukanta Das, Biplab K. Sikdar, Parimal Pal Chaudhuri	Nonlinear CA Based Scalable Design of On-Chip TPG for Multiple Cores.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF
71	Sukanta Das, Anirban Kundu, Subhayan Sen, Biplab K. Sikdar, Parimal Pal Chaudhuri	Non-Linear Celluar Automata Based PRPG Design (Without Prohibited Pattern Set) In Linear Time Complexity.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF
66	Li-Ren Huang, Jing-Yang Jou, Sy-Yen Kuo	An Efficient PRPG Strategy By Utilizing Essential Faults.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF	PRPG, essential fault, multiple polynomial, Gauss elimination, pseudorandom test pattern, multivariable linear equation, deterministic test set, random pattern resistant circuit, don't care value, intelligent heuristic, ISCAS-85 benchmark, ISCAS-89 benchmark, built-in self test, BIST, fault coverage, LFSR, test length, hardware overhead, multiple seed
58	Ahmad A. Al-Yamani, Edward J. McCluskey	BIST-Guided ATPG.	ISQED	2005	DBLP DOI BibTeX RDF
52	Ismet Bayraktaroglu, Alex Orailoglu	Selecting a PRPG: Randomness, Primitiveness, or Sheer Luck?	Asian Test Symposium	2001	DBLP DOI BibTeX RDF
38	Steven A. Myers	Efficient Amplification of the Security of Weak Pseudo-Random Function Generators.	J. Cryptol.	2003	DBLP DOI BibTeX RDF	Security amplification, XOR Lemma, Pseudo-randomness, Function generators
38	Ahmad A. Al-Yamani, Edward J. McCluskey	Seed encoding with LFSRs and cellular automata.	DAC	2003	DBLP DOI BibTeX RDF	built-in self test, VLSI Test, reseeding
38	Niloy Ganguly, Biplab K. Sikdar, Parimal Pal Chaudhuri	Design of an On-Chip Test Pattern Generator without Prohibited Pattern Set (PPS).	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF
38	Steven A. Myers	Efficient Amplification of the Security of Weak Pseudo-random Function Generators.	EUROCRYPT	2001	DBLP DOI BibTeX RDF
38	Paul Chang, Brion L. Keller, Sarala Paliwal	Effective parallel processing techniques for the generation of test data for a logic built-in self test system.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	logic built-in self test, complex processor, simulation time, random stimulus generation, signature computation, Pseudo-Random Pattern Generators, serial compression, response data, serial pattern dependency, parallel processing, parallel processing, logic testing, partitioning, built-in self test, integrated circuit testing, automatic test pattern generation, signatures, parallel simulation, microprocessor chips, logic simulation, logic simulation, post processing, logic partitioning, test data
38	Li-Ren Huang, Jing-Yang Jou, Sy-Yen Kuo	Gauss-elimination-based generation of multiple seed-polynomial pairs for LFSR.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
33	Michal Filipek, Grzegorz Mrugalski, Nilanjan Mukherjee 0001, Benoit Nadeau-Dostie, Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer	Low-Power Programmable PRPG With Test Compression Capabilities.	IEEE Trans. Very Large Scale Integr. Syst.	2015	DBLP DOI BibTeX RDF
33	Jedrzej Solecki, Jerzy Tyszer, Grzegorz Mrugalski, Nilanjan Mukherjee 0001, Janusz Rajski	Low power programmable PRPG with enhanced fault coverage gradient.	ITC	2012	DBLP DOI BibTeX RDF
33	Michal Filipek, Yoshiaki Fukui, Hiroyuki Iwata, Grzegorz Mrugalski, Janusz Rajski, Masahiro Takakura, Jerzy Tyszer	Low Power Decompressor and PRPG with Constant Value Broadcast.	Asian Test Symposium	2011	DBLP DOI BibTeX RDF
33	Peter Wohl, John A. Waicukauski, T. Finklea	Increasing PRPG-based compression by delayed justification.	ITC	2010	DBLP DOI BibTeX RDF
33	Peter Wohl, John A. Waicukauski, Sanjay Patel, Francisco DaSilva, Thomas W. Williams, Rohit Kapur	Efficient compression of deterministic patterns into multiple PRPG seeds.	ITC	2005	DBLP DOI BibTeX RDF
33	Ismet Bayraktaroglu, K. Udawatta, Alex Orailoglu	An Examination of PRPG Selection Approaches for Large, Industrial Designs.	Asian Test Symposium	1998	DBLP DOI BibTeX RDF
33	Li-Ren Huang, Sy-Yen Kuo, Ing-Yi Chen	A Gauss-elimination based PRPG for combinational circuits.	ED&TC	1995	DBLP DOI BibTeX RDF
33	Alodeep Sanyal, Sandip Kundu	A Built-in Test and Characterization Method for Circuit Marginality Related Failures.	ISQED	2008	DBLP DOI BibTeX RDF	Circuit Marginality, Pseudorandom Pattern Generator (PRPG), Multiple Input Signature Register (MISR), Fmax testing based on frequency shmoo, Built-In Self-Test (BIST), Design-for-Testability (DFT), Linear Feedback Shift Register (LFSR)
19	Peter Wohl, John A. Waicukauski, Frederic Neuveux, Emil Gizdarski	Fully X-tolerant, very high scan compression.	DAC	2010	DBLP DOI BibTeX RDF	X-tolerant, compression, LFSR, VLSI test, MISR
19	Diogo José Costa Alves, Edna Barros	A logic built-in self-test architecture that reuses manufacturing compressed scan test patterns.	SBCCI	2009	DBLP DOI BibTeX RDF	LBIST, compressed test patterns, test, SoC, self-test
19	Sandeep Jain, Jais Abraham, Srinivas Kumar Vooka, Sumant Kale, Amit Dutta, Rubin A. Parekhji	Enhancements in Deterministic BIST Implementations for Improving Test of Complex SOCs.	VLSI Design	2007	DBLP DOI BibTeX RDF
19	Biplab K. Sikdar, Samir Roy, Debesh K. Das	A Degree-of-Freedom Based Synthesis Scheme for Sequential Machines with Enhanced BIST Quality and Reduced Area.	J. Electron. Test.	2005	DBLP DOI BibTeX RDF	emitability, FSM state encoding, reachability, degree-of-freedom
19	Sukanta Das, Anirban Kundu, Biplab K. Sikdar, Parimal Pal Chaudhuri	Design of Nonlinear CA Based TPG Without Prohibited Pattern Set In Linear Time.	J. Electron. Test.	2005	DBLP DOI BibTeX RDF	nonlinear CA, prohibited pattern set, TPG
19	Samir Roy, Ujjwal Maulik, Biplab K. Sikdar	Exploiting Ghost-FSMs as a BIST Structure for Sequential Machines.	VLSI Design	2003	DBLP DOI BibTeX RDF
19	Niloy Ganguly, Anindyasundar Nandi, Sukanta Das, Biplab K. Sikdar, Parimal Pal Chaudhuri	An Evolutionary Strategy To Design An On-Chip Test Pattern Generator Without Prohibited Pattern Set (PPS).	Asian Test Symposium	2002	DBLP DOI BibTeX RDF
19	Jacob Savir	Module Level Weighted Random Patterns.	J. Electron. Test.	1997	DBLP DOI BibTeX RDF	weighted random test, self-test, detection probability, signal probability, pseudorandom test
19	Jacob Savir	Module level weighted random patterns.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	module level self-test architecture, pseudorandom pattern generator, universal weighting generator, scan latch, near-optimal weight, signal pins, weight control function, self-test time, logic testing, probability, integrated circuit testing, automatic testing, multivalued logic circuits, boundary scan testing, scan test, weighted random patterns, multiple input signature register
19	Paul H. Bardell	Design considerations for Parallel pseudoRandom Pattern Generators.	J. Electron. Test.	1990	DBLP DOI BibTeX RDF