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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 65 occurrences of 47 keywords
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Results
Found 60 publication records. Showing 60 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
36 | Slo-Li Chu |
An Energy Reduction Scheduling Mechanism for a High-Performance SoC Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUC ![In: Embedded and Ubiquitous Computing - EUC 2005, International Conference EUC 2005, Nagasaki, Japan, December 6-9, 2005, Proceedings, pp. 281-290, 2005, Springer, 3-540-30807-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
EOPRS, SAGE II, SoC, Power Reduction, Processor-in-Memory |
36 | Josep Torrellas, Liuxi Yang, Anthony-Trung Nguyen |
Toward a Cost-Effective DSM Organization That Exploits Processor-Memory Integration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: Proceedings of the Sixth International Symposium on High-Performance Computer Architecture, Toulouse, France, January 8-12, 2000, pp. 15-25, 2000, IEEE Computer Society, 0-7695-0550-3. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
directory controller, multiprocessor, reconfigurable, PIM, DSM, coherence protocol, NUMA, processor-in-memory, COMA |
35 | Slo-Li Chu |
POERS: A Performance-Oriented Energy Reduction Scheduling Technique for a High-Performance MPSoC Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPADS (2) ![In: 11th International Conference on Parallel and Distributed Systems, ICPADS 2005, Fuduoka, Japan, July 20-22, 2005, pp. 699-703, 2005, IEEE Computer Society, 0-7695-2281-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
POERS, SAGE II, MPSoC, Processor-in-Memory, Energy Reduction |
32 | Krishna Kumar Rangan, Philip A. Wilsey, Nilesh Pisolkar, Nael B. Abu-Ghazaleh |
PPIM-SIM: An Efficient Simulator for a Parallel Processor in Memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Annual Simulation Symposium ![In: Proceedings 34th Annual Simulation Symposium (SS 2001), Seattle, WA, USA, 22-26 April 2001, pp. 117-124, 2001, IEEE Computer Society, 0-7695-1092-2. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
32 | Slo-Li Chu |
PSS: A Novel Statement Scheduling Mechanism for a High-Performance SoC Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPADS ![In: 10th International Conference on Parallel and Distributed Systems, ICPADS 2004, Newport Beach, CA, USA, July 7-9, 2004, pp. 690-, 2004, IEEE Computer Society, 0-7695-2152-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Pair-Selection Scheduling, Statement Analysis, SoC, Processor-in-Memory, SAGE |
31 | Marco Lanuzza, Martin Margala, Pasquale Corsonello |
Cost-effective low-power processor-in-memory-based reconfigurable datapath for multimedia applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005, San Diego, California, USA, August 8-10, 2005, pp. 161-166, 2005, ACM, 1-59593-137-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
reconfigurable computing, datapath, processor-in-memory |
30 | Slo-Li Chu |
Critical Block Scheduling: A Thread-Level Parallelizing Mechanism for a Heterogeneous Chip Multiprocessor Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCPC ![In: Languages and Compilers for Parallel Computing, 20th International Workshop, LCPC 2007, Urbana, IL, USA, October 11-13, 2007, Revised Selected Papers, pp. 261-275, 2007, Springer, 978-3-540-85260-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Critical Block Scheduling, Octans, Chip Multiprocessor (CMP), Processor-in-Memory |
27 | Michael C. Huang 0001, Jose Renau, Seung-Moon Yoo, Josep Torrellas |
Energy/Performance Design of Memory Hierarchies for Processor-in-Memory Chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Intelligent Memory Systems ![In: Intelligent Memory Systems, Second International Workshop, IMS 2000, Cambridge, MA, USA, November 12, 2000, Revised Papers, pp. 152-159, 2000, Springer, 3-540-42328-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
26 | Xiaoyong Wen, Faycal Bensaali, Reza Sotudeh |
Dynamic Co-operative Intelligent Memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008, Hong Kong, January 23-25, 2008, pp. 184-189, 2008, IEEE Computer Society, 978-0-7695-3110-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
26 | Thomas L. Sterling |
Towards Memory Oriented Scalable Computer Architecture and High Efficiency Petaflops Computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NPC ![In: Network and Parallel Computing, IFIP International Conference, NPC 2004, Wuhan, China, October 18-20, 2004, Proceedings, pp. 2, 2004, Springer, 3-540-23388-1. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
25 | Shyamkumar Thoziyoor, Jay B. Brockman, Daniel Rinzler |
PIM lite: a multithreaded processor-in-memory prototype. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, Chicago, Illinois, USA, April 17-19, 2005, pp. 64-69, 2005, ACM, 1-59593-057-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
multithreading, VLSI design, processing-in-memory |
25 | Jung-Yup Kang, Sandeep Gupta 0001, Jean-Luc Gaudiot |
Accelerating the Kernels of BLAST with an Efficient PIM (Processor-In-Memory) Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CSB ![In: 3rd International IEEE Computer Society Computational Systems Bioinformatics Conference, CSB 2004, Stanford, CA, USA, August 16-19, 2004, pp. 552-553, 2004, IEEE Computer Society, 0-7695-2194-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Processor-In-Memory (PIM) Architecture, Sequence Alignment, BLAST |
25 | Thomas L. Sterling, Hans P. Zima |
Gilgamesh: a multithreaded processor-in-memory architecture for petaflops computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SC ![In: Proceedings of the 2002 ACM/IEEE conference on Supercomputing, Baltimore, Maryland, USA, November 16-22, 2002, CD-ROM, pp. 38:1-38:23, 2002, IEEE Computer Society, 0-7695-1524-X. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Petaflops computing, data parallel processing, parallel architectures, Processor-In-Memory, irregular applications |
24 | Slo-Li Chu |
Toward to Utilize the Heterogeneous Multiple Processors of the Chip Multiprocessor Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUC ![In: Embedded and Ubiquitous Computing, International Conference, EUC 2007, Taipei, Taiwan, December 17-20, 2007, Proceedings, pp. 234-246, 2007, Springer, 978-3-540-77091-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Swing Scheduling, Octans, Chip Multiprocessor (CMP), Processor-in-Memory |
22 | Changhee Jung, Daeseob Lim, Jaejin Lee, Yan Solihin |
Helper thread prefetching for loosely-coupled multiprocessor systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), Proceedings, 25-29 April 2006, Rhodes Island, Greece, 2006, IEEE. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
21 | Nagarajan Venkateswaran, Aditya Krishnan 0002, S. Niranjan Kumar, Arrvindh Shriraman, Srinivas Sridharan |
Memory in processor: a novel design paradigm for supercomputing architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGARCH Comput. Archit. News ![In: SIGARCH Comput. Archit. News 32(3), pp. 19-26, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
20 | Brandon J. Jasionowski, Michelle K. Lay, Martin Margala |
A Processor-In-Memory Architecture for Multimedia Compression. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 15(4), pp. 478-483, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
20 | Hans P. Zima, Thomas L. Sterling |
Macroservers: An Object-Based Programming and Execution Model for Processor-in-Memory Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISHPC ![In: High Performance Computing, Third International Symposium, ISHPC 2000, Tokyo, Japan, October 16-18, 2000. Proceedings, pp. 7-25, 2000, Springer, 3-540-41128-3. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
20 | Jaejin Lee, Changhee Jung, Daeseob Lim, Yan Solihin |
Prefetching with Helper Threads for Loosely Coupled Multiprocessor Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 20(9), pp. 1309-1324, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
19 | Peter M. Kogge, Toshio Sunaga, Hisatada Miyataka, Koji Kitamura, Eric Retter |
Combined DRAM and logic chip for massively parallel systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARVLSI ![In: 16th Conference on Advanced Research in VLSI (ARVLSI '95), March 27-29, 1995, Chapel Hill, North Carolina, USA, pp. 4-16, 1995, IEEE Computer Society, 0-8186-7047-9. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
EXECUBE, custom circuits, high density memory, PIM chip, Processor-In-Memory computer architecture, logic chip, 0.8 micron, 2.7 W, 25 MHz, 5 V, 50 MIPS, embedded systems, parallel architectures, CMOS logic circuits, microprocessor chips, CMOS technology, CPU, macros, massively parallel processing, DRAM chips, DRAM chip, CMOS memory circuits |
18 | Jih-Ching Chiu, Yu-Liang Chou, Hua-Yi Tzeng |
A multi-streaming SIMD architecture for multimedia applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Conf. Computing Frontiers ![In: Proceedings of the 6th Conference on Computing Frontiers, 2009, Ischia, Italy, May 18-20, 2009, pp. 51-60, 2009, ACM, 978-1-60558-413-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
SIMD, streaming processing, streaming computing, processor-in-memory, mmx, multimedia extensions, pim |
17 | Duncan G. Elliott, Michael Stumm, W. Martin Snelgrove, Christian Cojocaru, Robert McKenzie |
Computational RAM: Implementing Processors in Memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 16(1), pp. 32-41, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
16 | Jae Chul Cha, Sandeep K. Gupta 0001 |
Matrix Inversion on a PIM (Processor-in-Memory). ![Search on Bibsonomy](Pics/bibsonomy.png) |
CSSE (3) ![In: International Conference on Computer Science and Software Engineering, CSSE 2008, Volume 3: Grid Computing / Distributed and Parallel Computing / Information Security, December 12-14, 2008, Wuhan, China, pp. 419-422, 2008, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
16 | Slo-Li Chu, Wen-Chih Ho, Chien-Fang Chen, Kai-Wei Ceng, Ming-Han Liu |
Design a Novel Memory Network for Processor-in-Memory Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SKG ![In: 13th International Conference on Semantics, Knowledge and Grids, SKG 2017, Beijing, China, August 13-14, 2017, pp. 56-61, 2017, IEEE, 978-1-5386-2558-3. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
16 | Danijela Efnusheva, Aristotel Tentov |
Design of Processor in Memory with RISC-modified Memory-Centric Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CSOC (2) ![In: Cybernetics and Mathematics Applications in Intelligent Systems - Proceedings of the 6th Computer Science On-line Conference 2017 (CSOC2017), Vol 2, pp. 70-81, 2017, 978-3-319-57263-5. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
16 | Christopher J. Hughes, Sarita V. Adve |
Memory-side prefetching for linked data structures for processor-in-memory systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Parallel Distributed Comput. ![In: J. Parallel Distributed Comput. 65(4), pp. 448-463, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
16 | Yan Solihin, Jaejin Lee, Josep Torrellas |
Adaptively Mapping Code in an Intelligent Memory Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Intelligent Memory Systems ![In: Intelligent Memory Systems, Second International Workshop, IMS 2000, Cambridge, MA, USA, November 12, 2000, Revised Papers, pp. 71-84, 2000, Springer, 3-540-42328-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
16 | Dennis W. Prather |
Three Dimensional VLSI-Scale Interconnects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS Workshops ![In: Parallel and Distributed Processing, 15 IPDPS 2000 Workshops, Cancun, Mexico, May 1-5, 2000, Proceedings, pp. 1092-1103, 2000, Springer, 3-540-67442-X. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
15 | Ed T. Upchurch, Thomas L. Sterling, Jay B. Brockman |
Analysis and Modeling of Advanced PIM Architecture Design Tradeoffs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SC ![In: Proceedings of the ACM/IEEE SC2004 Conference on High Performance Networking and Computing, 6-12 November 2004, Pittsburgh, PA, USA, CD-Rom, pp. 12, 2004, IEEE Computer Society, 0-7695-2153-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
13 | Jih-Ching Chiu, Kai-Ming Yang, Yu-Liang Chou |
Design of a novel SIMD architecture by fusing operations and registers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICS ![In: Proceedings of the 23rd international conference on Supercomputing, 2009, Yorktown Heights, NY, USA, June 8-12, 2009, pp. 503-504, 2009, ACM, 978-1-60558-498-0. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
processor-in-memory, mmx, simd, multimedia extensions, pim |
13 | Sourav Chatterji, Manikandan Narayanan, Jason Duell, Leonid Oliker |
Performance Evaluation of Two Emerging Media Processors: VIRAM and Imagine. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 22-26 April 2003, Nice, France, CD-ROM/Abstracts Proceedings, pp. 229, 2003, IEEE Computer Society, 0-7695-1926-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
multimedia applications, stream processing, QR decomposition, processor-in-memory, vector architecture |
13 | Brian R. Gaeke, Parry Husbands, Xiaoye S. Li, Leonid Oliker, Katherine A. Yelick, Rupak Biswas |
Memory-Intensive Benchmarks: IRAM vs. Cache-Based Machines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 16th International Parallel and Distributed Processing Symposium (IPDPS 2002), 15-19 April 2002, Fort Lauderdale, FL, USA, CD-ROM/Abstracts Proceedings, 2002, IEEE Computer Society, 0-7695-1573-8. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
memory intensive benchmarks, data parallelism, vector processor, Processor-in-Memory, embedded DRAM |
13 | G. Jack Lipovski, Clement T. Yu |
The Dynamic Associative Access Memory Chip and Its Application to SIMD Processing and Full-Text Database Retrieval. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 7th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT '99), August 9-10, 1999, San Jose, CA, USA, pp. 24-, 1999, IEEE Computer Society, 0-7695-0259-8. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
12 | M. D. Arafat Kabir, Ehsan Kabir, Joshua Hollis, Eli Levy-Mackay, Atiyehsadat Panahi, Jason D. Bakos, Miaoqing Huang, David Andrews 0001 |
FPGA Processor In Memory Architectures (PIMs): Overlay or Overhaul ? ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2308.03914, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
12 | M. D. Arafat Kabir, Ehsan Kabir, Joshua Hollis, Eli Levy-Mackay, Atiyehsadat Panahi, Jason D. Bakos, Miaoqing Huang, David Andrews 0001 |
FPGA Processor In Memory Architectures (PIMs): Overlay or Overhaul ? ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 33rd International Conference on Field-Programmable Logic and Applications, FPL 2023, Gothenburg, Sweden, September 4-8, 2023, pp. 109-115, 2023, IEEE, 979-8-3503-4151-5. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
12 | Sung-June Byun, Dong-Gyun Kim, Kyung-Do Park, Yeun-Jin Choi, Pervesh Kumar, Imran Ali, Dong-Gyu Kim, June-Mo Yoo, Hyung-Ki Huh, Yeon-Jae Jung, Seok-Kee Kim, YoungGun Pu, Kang-Yoon Lee |
A Low-Power Analog Processor-in-Memory-Based Convolutional Neural Network for Biosensor Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Sensors ![In: Sensors 22(12), pp. 4555, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
12 | Kyung Do Park, Dong Gyun Kim, YoungGun Pu, Kang-Yoon Lee |
10.76 TOPS/W CNN Algorithm Circuit using Processor-In-Memory with 8T-SRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
BigComp ![In: IEEE International Conference on Big Data and Smart Computing, BigComp 2021, Jeju Island, South Korea, January 17-20, 2021, pp. 330-333, 2021, IEEE, 978-1-7281-8924-6. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
12 | Purab Ranjan Sutradhar, Mark Connolly, Sathwika Bavikadi, Sai Manoj Pudukotai Dinakarrao, Mark A. Indovina, Amlan Ganguly |
pPIM: A Programmable Processor-in-Memory Architecture With Precision-Scaling for Deep Learning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Comput. Archit. Lett. ![In: IEEE Comput. Archit. Lett. 19(2), pp. 118-121, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
12 | Dominique Lavenier, Remy Cimadomo, Romaric Jodin |
Variant Calling Parallelization on Processor-in-Memory Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
BIBM ![In: IEEE International Conference on Bioinformatics and Biomedicine, BIBM 2020, Virtual Event, South Korea, December 16-19, 2020, pp. 204-207, 2020, IEEE, 978-1-7281-6215-7. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
12 | Richard Muri, Paul J. Fortier |
Embedded Processor-In-Memory Architecture for Accelerating Arithmetic Operations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPEC ![In: 2019 IEEE High Performance Extreme Computing Conference, HPEC 2019, Waltham, MA, USA, September 24-26, 2019, pp. 1-7, 2019, IEEE, 978-1-7281-5020-8. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
12 | Duckhwan Kim 0001 |
Neurocube: Energy-Efficient Programmable Digital Deep Learning Accelerator based on Processor in Memory Platform. ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2019 |
RDF |
|
12 | Dominique Lavenier, Jean-François Roy, David Furodet |
DNA mapping using Processor-in-Memory architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
BIBM ![In: IEEE International Conference on Bioinformatics and Biomedicine, BIBM 2016, Shenzhen, China, December 15-18, 2016, pp. 1429-1435, 2016, IEEE Computer Society, 978-1-5090-1611-2. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
12 | Joshua Schabel, Lee Baker, Sumon Dey, Weifu Li, Paul D. Franzon |
Processor-in-memory support for artificial neural networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICRC ![In: IEEE International Conference on Rebooting Computing, ICRC 2016, San Diego, CA, USA, October 17-19, 2016, pp. 1-8, 2016, IEEE Computer Society, 978-1-5090-1370-8. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
12 | Erik P. DeBenedictis, Jeanine E. Cook, Mark Hoemmen, Tzevetan S. Metodi |
Optimal adiabatic scaling and the processor-in-memory-and-storage architecture (OAS+PIMS). ![Search on Bibsonomy](Pics/bibsonomy.png) |
NANOARCH ![In: Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2015, Boston, MA, USA, July 8-10, 2015, pp. 69-74, 2015, IEEE Computer Society, 978-1-4673-7849-9. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
12 | Jed Kao-Tung Chang, Chen Liu 0001, Jean-Luc Gaudiot |
Enhancement for Potential Target in Cryptography Algorithms by Applying Processor-in-Memory Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS Workshops ![In: 2013 IEEE International Symposium on Parallel & Distributed Processing, Workshops and Phd Forum, Cambridge, MA, USA, May 20-24, 2013, pp. 2035-2044, 2013, IEEE. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
12 | Mohammed Sayed, Wael M. Badawy, Graham A. Jullien |
Video-Active RAM: A processor-in-memory architecture for video coding applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2010), May 30 - June 2, 2010, Paris, France, pp. 2968-2971, 2010, IEEE, 978-1-4244-5308-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
12 | Jung-Yup Kang, Sandeep K. Gupta 0001, Jean-Luc Gaudiot |
An Efficient Data-Distribution Mechanism in a Processor-In-Memory (PIM) Architecture Applied to Motion Estimation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 57(3), pp. 375-388, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Real-time and embedded systems, Special-Purpose and Application-Based Systems |
12 | A. I. Eldosuky, H. A. Ali, M. A. Abbas |
An Energy-Efficient FlexRAM Processor-In-Memory chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Egypt. Comput. Sci. J. ![In: Egypt. Comput. Sci. J. 28(3), pp. 66-74, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP BibTeX RDF |
|
12 | Slo-Li Chu, Tsung-Chuan Huang, Lan-Chi Lee |
Improving workload balance and code optimization on processor-in-memory systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Syst. Softw. ![In: J. Syst. Softw. 71(1-2), pp. 71-82, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
12 | Slo-Li Chu, Tsung-Chuan Huang |
SAGE: an automatic analyzing system for a new high-performance SoC architecture--processor-in-memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Syst. Archit. ![In: J. Syst. Archit. 50(1), pp. 1-15, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
12 | Tsung-Chuan Huang, Slo-Li Chu |
A statement based parallelizing framework for processor-in-memory architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Inf. Process. Lett. ![In: Inf. Process. Lett. 85(3), pp. 159-163, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
12 | Jung-Yup Kang, Sandeep Gupta 0001, Saurabh Shah, Jean-Luc Gaudiot |
An Efficient PIM (Processor-In-Memory) Architecture for Motion Estimation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 14th IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP 2003), 24-26 June 2003, The Hague, The Netherlands, pp. 282-292, 2003, IEEE Computer Society, 0-7695-1992-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
12 | Thomas L. Sterling |
The Gilgamesh MIND Processor-in-Memory Architecture for Petaflops-Scale Computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISHPC ![In: High Performance Computing, 4th International Symposium, ISHPC 2002, Kansai Science City, Japan, May 15-17, 2002, Proceedings, pp. 1-5, 2002, Springer, 3-540-43674-X. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
12 | Slo-Li Chu, Tsung-Chuan Huang, Lan-Chi Lee |
Improving Workload Balance and Code Optimization in Processor-in-Memory Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPADS ![In: Eigth International Conference on Parallel and Distributed Systems, ICPADS 2001, KyongJu City, Korea, June 26-29, 2001, pp. 273-278, 2001, IEEE Computer Society, 0-7695-1153-8. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
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12 | Yi Tian, Edwin Hsing-Mean Sha, Chantana Chantrapornchai, Peter M. Kogge |
Optimizing Data Scheduling on Processor-in-Memory Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPPS/SPDP ![In: 12th International Parallel Processing Symposium / 9th Symposium on Parallel and Distributed Processing (IPPS/SPDP '98), March 30 - April 3, 1998, Orlando, Florida, USA, Proceedings, pp. 57-61, 1998, IEEE Computer Society, 0-8186-8403-8. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
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11 | Arun Rodrigues, Richard C. Murphy, Peter M. Kogge, Keith D. Underwood |
Poster reception - The structural simulation toolkit: exploring novel architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SC ![In: Proceedings of the ACM/IEEE SC2006 Conference on High Performance Networking and Computing, November 11-17, 2006, Tampa, FL, USA, pp. 157, 2006, ACM Press, 0-7695-2700-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
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11 | John C. Koob, Daniel A. Leder, Raymond J. Sung, Tyler L. Brandon, Duncan G. Elliott, Bruce F. Cockburn, Lisa G. McIlrath |
Design of a 3-D fully depleted SOI computational RAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 13(3), pp. 358-369, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
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4 | Jinwoo Suh, Eun-Gyu Kim, Stephen P. Crago, Lakshmi Srinivasan, Matthew C. French |
A Performance Analysis of PIM, Stream Processing, and Tiled Processing on Memory-Intensive Signal Processing Kernels. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 30th International Symposium on Computer Architecture (ISCA 2003), 9-11 June 2003, San Diego, California, USA, pp. 410-419, 2003, IEEE Computer Society, 0-7695-1945-8. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
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4 | Jinwoo Suh, Dong-In Kang, Stephen P. Crago |
Dynamic Power Management of Multiprocessor Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 16th International Parallel and Distributed Processing Symposium (IPDPS 2002), 15-19 April 2002, Fort Lauderdale, FL, USA, CD-ROM/Abstracts Proceedings, 2002, IEEE Computer Society, 0-7695-1573-8. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
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4 | Hans P. Zima, Thomas L. Sterling |
Support for Irregular Computations in Massively Parallel PIM Arrays, Using an Object-Based Execution Model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS Workshops ![In: Parallel and Distributed Processing, 15 IPDPS 2000 Workshops, Cancun, Mexico, May 1-5, 2000, Proceedings, pp. 450-456, 2000, Springer, 3-540-67442-X. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
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