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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 851 occurrences of 523 keywords
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Results
Found 2201 publication records. Showing 2201 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
94 | Ciji Isen, Lizy K. John, Eugene John |
A Tale of Two Processors: Revisiting the RISC-CISC Debate. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SPEC Benchmark Workshop ![In: Computer Performance Evaluation and Benchmarking, SPEC Benchmark Workshop 2009, Austin, TX, USA, January 25, 2009. Proceedings, pp. 57-76, 2009, Springer, 978-3-540-93798-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
76 | Liwen Shih |
Microprogramming heritage of RISC design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 23rd Annual Workshop and Symposium on Microprogramming and Microarchitecture, 1990, Orlando, Florida, USA, November 27-29, 1990, pp. 275-280, 1990, ACM/IEEE, 0-89791-413-9. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP BibTeX RDF |
|
73 | Krishna V. Palem, Barbara B. Simons |
Scheduling Time-Critical Instructions on RISC Machines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Program. Lang. Syst. ![In: ACM Trans. Program. Lang. Syst. 15(4), pp. 632-658, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
RISC machine scheduling, NP-complete, latency, compiler optimization, register allocation, greedy algorithm, instruction scheduling, deadline, RISC, pipeline processor |
69 | Michel J. Daydé, Iain S. Duff |
The RISC BLAS: a blocked implementation of level 3 BLAS for RISC processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Math. Softw. ![In: ACM Trans. Math. Softw. 25(3), pp. 316-340, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
matrix-matrix kernels, blocking, loop-unrolling, level 3 BLAS, RISC processors |
58 | Marco Aurélio Cavalcanti Pacheco, Philip C. Treleaven |
A Risc Architecture to Support Neural Net Simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IWANN ![In: New Trends in Neural Computation, International Workshop on Artificial Neural Networks, IWANN '93, Sitges, Spain, June 9-11, 1993, Proceedings, pp. 482-487, 1993, Springer, 3-540-56798-4. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
56 | Sung-Soo Lim, Young Hyun Bae, Gyu Tae Jang, Byung-Do Rhee, Sang Lyul Min, Chang Yun Park, Heonshik Shin, Kunsoo Park, Soo-Mook Moon, Chong-Sang Kim |
An Accurate Worst Case Timing Analysis for RISC Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Software Eng. ![In: IEEE Trans. Software Eng. 21(7), pp. 593-604, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
pipelined execution, real-time system, Cache memory, worst case execution time, RISC processor |
54 | Farooq Butt |
Porting the mcc PowerPC C/C++ Compiler into an Interactive Development Environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM SIGPLAN Notices ![In: ACM SIGPLAN Notices 31(8), pp. 64-73, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
C++ |
54 | Charles D. Norton |
The International Workshop on Parallel C++ (IWPC++), Kanazawa, Ishikawa Prefecture, Japan. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM SIGPLAN Notices ![In: ACM SIGPLAN Notices 31(8), pp. 28-30, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
C++ |
49 | Sofiène Tahar, Ramayya Kumar |
Implementational Issues for Verifying RISC-Pipeline Conflicts in HOL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
TPHOLs ![In: Higher Order Logic Theorem Proving and Its Applications, 7th International Workshop, Valletta, Malta, September 19-22, 1994, Proceedings, pp. 424-439, 1994, Springer, 3-540-58450-1. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
47 | Ioannis Panagopoulos, Christos Pavlatos, George K. Papakonstantinou |
A hardware extension of the RISC microprocessor for Attribute Grammar evaluation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAC ![In: Proceedings of the 2004 ACM Symposium on Applied Computing (SAC), Nicosia, Cyprus, March 14-17, 2004, pp. 897-904, 2004, ACM, 1-58113-812-1. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
RISC microprocessors, Attribute Grammars, declarative programs |
47 | Krishna V. Palem, Barbara B. Simons |
Scheduling Time-Critical Instructions on RISC Machines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
POPL ![In: Conference Record of the Seventeenth Annual ACM Symposium on Principles of Programming Languages, San Francisco, California, USA, January 1990, pp. 270-280, 1990, ACM Press, 0-89791-343-4. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
RISC |
47 | Margaret L. Simmons, Harvey J. Wasserman |
Performance evaluation of the IBM RISC System/6000: comparison of an optimized scalar processor with two vector processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SC ![In: Proceedings Supercomputing '90, New York, NY, USA, November 12-16, 1990, pp. 132-141, 1990, IEEE Computer Society, 0-89791-412-0. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
RISC |
47 | Christopher F. Clark |
The JADE interpreter: a RISC interpreter for syntax directed editing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PLDI ![In: Proceedings of the Symposium on Interpreters and Interpretive Techniques, 1987, St. Paul, Minnesota, USA, June 24 - 26, 1987, pp. 222-228, 1987, ACM, 0-89791-235-7. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
RISC |
47 | Richard B. Kieburtz |
A RISC Architecture for Symbolic Computation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASPLOS ![In: Proceedings of the Second International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS II), Palo Alto, California, USA, October 5-8, 1987., pp. 146-155, 1987, ACM Press, 0-8186-0805-6. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
RISC |
45 | Nikolaos Kavvadias, Spiridon Nikolaidis 0001 |
Elimination of Overhead Operations in Complex Loop Structures for Embedded Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 57(2), pp. 200-214, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Optimization, Microprocessors, Hardware description languages, Real-time and embedded systems, Pipeline processors, Control design |
43 | Rishiyur S. Nikhil |
Can Dataflow Subsume von Neumann Computing? ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: Proceedings of the 16th Annual International Symposium on Computer Architecture. Jerusalem, Israel, June 1989, pp. 262-272, 1989, ACM, 0-89791-319-1. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
RISC |
42 | Bob Wilkinson, Lawrence S. Mulholland |
An Implementation of the BLAS on the i860: A RISC Approach to Software for RISC Devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CONPAR ![In: Parallel Processing: CONPAR 92 - VAPP V, Second Joint International Conference on Vector and Parallel Processing, Lyon, France, September 1-4, 1992, Proceedings, pp. 283-294, 1992, Springer, 3-540-55895-0. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
Fortran, linear algebra, RISC, BLAS, hierarchical memory |
40 | Xiaoyong Chen, Douglas L. Maskell |
M2E: A Multiple-Input, Multiple-Output Function Extension for RISC-Based Extensible Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARCS ![In: Architecture of Computing Systems - ARCS 2006, 19th International Conference, Frankfurt/Main, Germany, March 13-16, 2006, Proceedings, pp. 191-201, 2006, Springer, 3-540-32765-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
40 | Steffen Köhler, Jens Braunes, Thomas Preußer, Martin Zabel, Rainer G. Spallek |
Increasing ILP of RISC Microprocessors Through Control-Flow Based Reconfiguration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field Programmable Logic and Application, 14th International Conference , FPL 2004, Leuven, Belgium, August 30-September 1, 2004, Proceedings, pp. 781-790, 2004, Springer, 3-540-22989-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
40 | Jiyang Kang, Jongbok Lee, Wonyong Sung |
A Compiler-Friendly RISC-Based Digital Signal Processor Synthesis and Performance Evaluation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 27(3), pp. 297-312, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
code converter, compiler-friendly, performance evaluation, digital signal processor, architecture synthesis |
40 | Chris R. Jesshope, Bing Luo |
Micro-Threading: A New Approach to Future RISC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACAC ![In: 5th Australasian Computer Architecture Conference (ACAC 2000), 31 January - 3 February 2000, Canberra, Australia, pp. 34-41, 2000, IEEE Computer Society, 0-7695-0512-0. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
40 | Edgar Holmann, Toyohiko Yoshida, Akira Yamada 0005, Shin-ichi Uramoto |
Single Chip Dual-Issue RISC Processor for Real-Time MPEG-2 Software Decoding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 18(2), pp. 155-165, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
40 | Olivier Maquelin, Herbert H. J. Hum, Guang R. Gao |
Costs and Benefits of Multithreading with Off-the-Shelf RISC Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Euro-Par ![In: Euro-Par '95 Parallel Processing, First International Euro-Par Conference, Stockholm, Sweden, August 29-31, 1995, Proceedings, pp. 117-128, 1995, Springer, 3-540-60247-X. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
40 | Kai Hwang 0001, Michel Dubois 0001, Dhabaleswar K. Panda 0001, S. Rao, Shisheng Shang, Aydin Üresin, W. Mao, H. Nair, M. Lytwyn, F. Hsieh, J. Liu, Sharad Mehrotra, Chien-Ming Cheng |
OMP: a RISC-based multiprocessor using orthogonal-access memories and multiple spanning buses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICS ![In: Proceedings of the 4th international conference on Supercomputing, ICS 1990, Amsterdam, The Netherlands, June 11-15, 1990, pp. 7-22, 1990, ACM, 0-89791-369-8. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
38 | Erik Buchanan, Ryan Roemer, Hovav Shacham, Stefan Savage |
When good instructions go bad: generalizing return-oriented programming to RISC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCS ![In: Proceedings of the 2008 ACM Conference on Computer and Communications Security, CCS 2008, Alexandria, Virginia, USA, October 27-31, 2008, pp. 27-38, 2008, ACM, 978-1-59593-810-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
return-into-libc, return-oriented programming, RISC, SPARC |
38 | Salah Merniz, Mohamed Benmohammed |
A Scalable Proof Methodology for RISC Processor Designs: A Functional Approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITNG ![In: Fifth International Conference on Information Technology: New Generations (ITNG 2008), 7-8 April 2008, Las Vegas, Nevada, USA, pp. 241-246, 2008, IEEE Computer Society, 978-0-7695-3099-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
State functions, RISC designs, Formal Verification, Functional programming, Micro-architectures |
38 | Yunquan Zhang, Ying Chen, Yuan Tang |
Block size selection of parallel LU and QR on PVP-based and RISC-based supercomputers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
China HPC ![In: CHINA HPC 2007, Proceedings of the Asian Technology Information Program's (ATIP's) Third Workshop on High-Performance Computing in China: `Solution Approaches to Impediments for High Performance Computing`, Supercomputing 2007 (SC07), November 11, 2007, Reno, Nevada, USA, pp. 115-125, 2007, ACM Press, 978-1-59593-903-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
LU, PVP, optimal parallel block size, RISC, ScaLAPACK, QR |
38 | Tsung-Han Tsai 0001, Ren-Jr Wu, Liang-Gee Chen |
A Cost-Effective Design for MPEG-2 Audio Decoder with Embedded RISC Core. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 29(3), pp. 255-265, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
degrouping, synthesis filterbank, RISC, MPEG-2, multichannel |
38 | Marco Antonio Dal Poz, Jose Edinson Aedo Cobo, Wilhelmus A. M. Van Noije, Marcelo Knörich Zuffo |
A Simple RISC Microprocessor Core Designed for Digital Set-Top-Box Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 12th IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP 2000), 10-12 July 2000, Boston, MA, USA, pp. 35-, 2000, IEEE Computer Society, 0-7695-0716-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
FPGA, VHDL, Reconfigurable Computing, Microprocessor, MPEG, RISC, Co-Design, Instruction Set, HDTV, Set-Top-Box, iDCT, cable TV |
38 | Valentina Salapura, Michael Gschwind |
Hardware/Software Co-Design of a Fuzzy RISC Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1998 Design, Automation and Test in Europe (DATE '98), February 23-26, 1998, Le Palais des Congrès de Paris, Paris, France, pp. 875-882, 1998, IEEE Computer Society, 0-8186-8359-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
hardware/software co-evaluation, processor core, MIPS RISC processor, fuzzy processing, fuzzy rule evaluation, instruction set definition, performance evaluation, VHDL, logic synthesis, application specific instruction set processor (ASIP), hardware/software co-design, instruction set architecture, subword parallelism |
38 | Zhen Guo, He Li, Shuling Guo, Dongsheng Wang |
Design and Simulation of a RISC-Based 32-bit Embedded On-Board Computer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, pp. 413-, 1998, IEEE Computer Society, 0-8186-8277-9. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
Hardware/Software, Simulation, Design, Embedded System, EDA, RISC |
38 | Kanad Ghose, Pavel Vasek |
A Fast Capability Extension to a RISC Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROMICRO ![In: 22rd EUROMICRO Conference '96, Beyond 2000: Hardware and Software Design Strategies, September 2-5, 1996, Prague, Czech Republic, pp. 606-, 1996, IEEE Computer Society, 0-8186-7487-3. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
fast capability extension, RISC architecture, capability-based addressing, capability-based machines, simulated executions, security, information sharing, reduced instruction set computing, performance penalty |
38 | Kotaro Shimamura, Shigeya Tanaka, Tetsuya Shimomura, Takashi Hotta, Eiki Kamada, Hideo Sawamoto, Teruhisa Shimizu, Kisaburo Nakazawa |
A superscalar RISC processor with pseudo vector processing feature. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1995 International Conference on Computer Design (ICCD '95), VLSI in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings, pp. 102-109, 1995, IEEE Computer Society, 0-8186-7165-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
superscalar RISC processor, pseudo vector processing, architectural extension, floating-point registers, scoreboard-based dependency check, pipeline stage optimization, 267 MFLOPS, 1.2 Gbyte/s, performance evaluation, performance, computer architecture, memory access, reduced instruction set computing, vector processor systems |
38 | Thomas Scholz, Michael Schäfers 0003 |
An improved dynamic register array concept for high-performance RISC processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HICSS (1) ![In: 28th Annual Hawaii International Conference on System Sciences (HICSS-28), January 3-6, 1995, Kihei, Maui, Hawaii, USA, pp. 181-190, 1995, IEEE Computer Society, 0-8186-6945-4. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
dynamic register array concept, high-performance RISC processors, processor registers, Multi Windows, Threaded Windows, dynamic register array, dynamic register allocation, general purpose registers, fast context switches, short interrupt latency, exception routines, real time systems, data structures, data structures, interrupts, storage allocation, external memory, registers, reduced instruction set computing |
38 | Manuel L. Anido, David J. Allerton, Ed Zaluska |
A Three-Port/Three-Access Register File for Concurrent Processing and I/O Communication in a RISC-Like Graphics Engine. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: Proceedings of the 16th Annual International Symposium on Computer Architecture. Jerusalem, Israel, June 1989, pp. 354-361, 1989, ACM, 0-89791-319-1. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
Computer Image Generation, Computer Architecture, VLSI Design, Interprocessor Communication, RISC, Reduced Instruction Set Computers |
38 | William R. Bush, A. Dain Samples, David M. Ungar, Paul N. Hilfinger |
Compiling Smalltalk-80 to a RISC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASPLOS ![In: Proceedings of the Second International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS II), Palo Alto, California, USA, October 5-8, 1987., pp. 112-116, 1987, ACM Press, 0-8186-0805-6. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
RISC, Smalltalk-80 |
36 | Chien-Kuo V. Tien, Kelvin Lewis, Hans J. Greub, Tom Tsen, John F. McDonald 0001 |
Design of a 32 b monolithic microprocessor based on GaAs HMESFET technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 5(2), pp. 238-243, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
34 | Ioannis Panagopoulos, Christos Pavlatos, George K. Papakonstantinou |
An Embedded Microprocessor for Intelligent Control. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Intell. Robotic Syst. ![In: J. Intell. Robotic Syst. 42(2), pp. 179-211, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
embedded systems, logic programming, microprocessor, intelligent control, RISC, declarative programs |
34 | Gaetano Borriello, Andrew R. Cherenson, Peter B. Danzig, Michael N. Nelson |
RISCs versus CISCs for Prolog: A Case Study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASPLOS ![In: Proceedings of the Second International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS II), Palo Alto, California, USA, October 5-8, 1987., pp. 136-145, 1987, ACM Press, 0-8186-0805-6. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
Prolog, RISC, CISC |
31 | Cheol-Hong Moon, Woo-Chun Jang |
Implementation of LED Array Color Temperature Controlled Lighting System Using RISC IP Core. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICIC (1) ![In: Emerging Intelligent Computing Technology and Applications, 5th International Conference on Intelligent Computing, ICIC 2009, Ulsan, South Korea, September 16-19, 2009. Proceedings, pp. 753-761, 2009, Springer, 978-3-642-04069-6. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
31 | Josef Börcsök, Ali Hayek, Muhammad Umar |
Implementation of a 1oo2-RISC-architecture on FPGA for safety systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AICCSA ![In: The 6th ACS/IEEE International Conference on Computer Systems and Applications, AICCSA 2008, Doha, Qatar, March 31 - April 4, 2008, pp. 1046-1051, 2008, IEEE Computer Society, 978-1-4244-1967-8. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
31 | Xuehai Qian, He Huang, Hao Zhang 0009, Guoping Long, Junchao Zhang, Dongrui Fan |
Design and Implementation of Floating Point Stack on General RISC Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PDP ![In: 15th Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP 2007), 7-9 February 2007, Naples, Italy, pp. 238-245, 2007, IEEE Computer Society, 0-7695-2784-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
31 | Rainer Ohlendorf, Thomas Wild, Michael Meitinger, Holm Rauchfuss, Andreas Herkersdorf |
Performance Evaluation of RISC-based SoC Platforms in Network Processing Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICSAMOS ![In: Proceedings of 2006 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (IC-SAMOS 2006), Samos, Greece, July 17-20, 2006, pp. 152-159, 2006, IEEE, 1-4244-0155-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
31 | Kiyofumi Tanaka |
Casablanca II: Implementation of a Real-Time RISC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 16th IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP 2005), 23-25 July 2005, Samos, Greece, pp. 36-42, 2005, IEEE Computer Society, 0-7695-2407-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
31 | Tay-Jyi Lin, Chie-Min Chao, Chia-Hsien Liu, Pi-Chen Hsiao, Shin-Kai Chen, Li-Chun Lin, Chih-Wei Liu, Chein-Wei Jen |
A unified processor architecture for RISC & VLIW DSP. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, Chicago, Illinois, USA, April 17-19, 2005, pp. 50-55, 2005, ACM, 1-59593-057-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
dual-core processor, register organization, variable-length instruction encoding, digital signal processor |
31 | Sascha Wennekers, Christian Siemers |
Reconfigurable RISC - A New Approach for Space-Efficient Superscalar Microprocessor Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARCS ![In: Trends in Network and Pervasive Computing - ARCS 2002, International Conference on Architecture of Computing Systems, Karlsruhe, Germany, April 8-12, 2002, Proceedings, pp. 165-178, 2002, Springer, 3-540-43409-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
31 | Johann Großschädl |
Instruction Set Extension for Long Integer Modulo Arithmetic on RISC-Based Smart Cards. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBAC-PAD ![In: 14th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2002), 28-30 October 2002, Vitoria, Espirito Santo, Brazil, pp. 13-19, 2002, IEEE Computer Society, 0-7695-1772-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
31 | Marc Campbell |
Evaluating ASIC, DSP, and RISC Architectures for Embedded Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES ![In: Languages, Compilers, and Tools for Embedded Systems, ACM SIGPLAN Workshop LCTES'98, Montreal, Canada, June 1998, Proceedings, pp. 261, 1998, Springer, 3-540-65075-X. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
31 | Ali Maamar, G. Russell |
A 32-Bit Risc Processor with Concurrent Error Detection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROMICRO ![In: 24th EUROMICRO '98 Conference, Engineering Systems and Software for the Next Decade, 25-27 August 1998, Vesteras, Sweden, pp. 10461-10467, 1998, IEEE Computer Society, 0-8186-8646-4. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
31 | V. J. Fazio, R. D. Pose |
Distributed Route Initialization Algorithms for the Monash Secure RISC Multiprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HICSS (5) ![In: 30th Annual Hawaii International Conference on System Sciences (HICSS-30), 7-10 January 1997, Maui, Hawaii, USA, pp. 24-33, 1997, IEEE Computer Society, 0-8186-7734-1. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
31 | Luigi Carro, Altamiro Amadeu Susin |
A Risc Architecture to Explore HW/SW Parallelism in HW/SW Co-Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ECBS ![In: IEEE Symposium and Workshop on Engineering of Computer Based Systems (ECBS'96), March 11-15, 1996, Friedrichshafen, Germany., pp. 382-388, 1996, IEEE Computer Society, 0-8186-7355-9. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
31 | Pedro Furtado 0001, Henrique Madeira |
Fault Injection Evaluation of Assigned Signatures in a RISC Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EDCC ![In: Dependable Computing - EDCC-2, Second European Dependable Computing Conference, Taormina, Italy, October 2-4, 1996, Proceedings, pp. 55-72, 1996, Springer, 3-540-61772-8. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
31 | Rajiv Gupta 0001, Michael Epstein, Michael Whelan |
The design of a RISC based multiprocessor chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SC ![In: Proceedings Supercomputing '90, New York, NY, USA, November 12-16, 1990, pp. 920-929, 1990, IEEE Computer Society, 0-89791-412-0. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
31 | M. Castan, Elliott I. Organick |
µ3L: An HLL-RISC processor for parallel execution of FP-language programs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 9th International Symposium on Computer Architecture (ISCA 1982), Austin, TX, USA, April 26-29, 1982, pp. 239-247, 1982, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
1982 |
DBLP BibTeX RDF |
FP |
31 | David A. Patterson 0001, Richard S. Piepho |
RISC assessment: A high-level language experiment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 9th International Symposium on Computer Architecture (ISCA 1982), Austin, TX, USA, April 26-29, 1982, pp. 3-8, 1982, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
1982 |
DBLP BibTeX RDF |
|
29 | Hans Eberle |
Architektur moderner RISC-Mikroprozessoren. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Inform. Spektrum ![In: Inform. Spektrum 20(5), pp. 259-267, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
Mikroprozessoren, Pipelineverarbeitung, Cachespeicher, RISC |
29 | Stephanie Dogimont, Martin Gumm, Friederich Mombers, Daniel Mlynek, Alessandro Torielli |
Conception and design of a RISC CPU for the use as embedded controller within a parallel multimedia architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 1997 International Conference on Application-Specific Systems, Architectures, and Processors (ASAP '97), 14-16 July 1997, Zurich, Switzerland, pp. 412-421, 1997, IEEE Computer Society, 0-8186-7958-1. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
RISC CPU, parallel multimedia architecture, high performance control structure, parallel motion estimation architecture, MPEG2 coding, combined MIMD-SIMD approach, motion estimation, ASIP, subword parallelism, embedded controller |
29 | Chia-Hsing Chien, Mark A. Franklin, Tienyo Pan, Prithvi Prabhu |
ARAS: asynchronous RISC architecture simulator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: Second Working Conference on Asynchronous Design Methodologies, May 30-31, 1995, London, England, UK, pp. 210-, 1995, IEEE Computer Society, 0-8186-7098-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
asynchronous RISC architecture simulator, ARAS, pipeline instruction simulator, benchmark programs, pipeline configuration, asynchronous pipeline architectures, performance evaluation, parallel architectures, virtual machines, performance measurements, pipeline processing |
29 | John-David Wellman, Edward S. Davidson |
The resource conflict methodology for early-stage design space exploration of superscalar RISC processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1995 International Conference on Computer Design (ICCD '95), VLSI in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings, pp. 110-115, 1995, IEEE Computer Society, 0-8186-7165-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
resource conflict methodology, early-stage design space exploration, superscalar RISC processors, execution trace driven simulation, hardware element model, analysis program, performance evaluation, virtual machines, computer architecture, reduced instruction set computing, design cycle |
29 | Ramayya Kumar, Sofiène Tahar |
Formal verification of pipeline conflicts in RISC processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EURO-DAC ![In: Proceedings EURO-DAC'94, European Design Automation Conference, Grenoble, France, September 19-22, 1994, pp. 284-289, 1994, IEEE Computer Society, 0-89791-685-9. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
RISC |
29 | Hidekazu Terai, Kazutoshi Gemma, Yohsuke Nagao, Yasuo Satoh, Yasuhiro Ohno |
Basic Concept of Cooperative Timing-driven Design Automation Technology for High-speed RISC Processor HARP-1. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 31st Conference on Design Automation, San Diego, California, USA, June 6-10, 1994., pp. 262-269, 1994, ACM Press, 0-7803-1836-6. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
RISC |
29 | David H. Bailey |
RISC microprocessors and scientific computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SC ![In: Proceedings Supercomputing '93, Portland, Oregon, USA, November 15-19, 1993, pp. 645-654, 1993, ACM, 0-8186-4340-4. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
RISC, Intel i860 |
29 | John Wood, Harold C. Grossman |
Interprocedural register allocation for RISC machines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Southeast Regional Conference ![In: Proceedings of the 30th Annual Southeast Regional Conference, 1992, Raleigh, North Carolina, USA, April 8-10, 1992, pp. 188-195, 1992, ACM, 0-89791-506-2. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
Interprocedural Register Allocation, RISC Computer, Webs, Graph Coloring |
29 | Kristy Andrews, Duane Sand |
Migrating a CISC Computer Family onto RISC via Object Code Translation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASPLOS ![In: ASPLOS-V Proceedings - Fifth International Conference on Architectural Support for Programming Languages and Operating Systems, Boston, Massachusetts, USA, October 12-15, 1992., pp. 213-222, 1992, ACM Press, 0-89791-534-8. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
RISC, CISC |
29 | C. Brian Hall, Kevin O'Brien |
Performance Characteristics of Architectural Features of the IBM RISC System/6000. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASPLOS ![In: ASPLOS-IV Proceedings - Forth International Conference on Architectural Support for Programming Languages and Operating Systems, Santa Clara, California, USA, April 8-11, 1991., pp. 303-309, 1991, ACM Press, 0-89791-380-9. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
RISC, VAX |
29 | Dileep Bhandarkar, Douglas W. Clark |
Performance From Architecture: Comparing a RISC and CISC with Similar Hardware Organization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASPLOS ![In: ASPLOS-IV Proceedings - Forth International Conference on Architectural Support for Programming Languages and Operating Systems, Santa Clara, California, USA, April 8-11, 1991., pp. 310-319, 1991, ACM Press, 0-89791-380-9. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
RISC, CISC |
29 | Walter A. Helbig, Veljko M. Milutinovic |
A DCFL E/D-MESFET GaAs Experimental RISC Machine. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 38(2), pp. 263-274, 1989. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
RCA, DCFL E/D-MESFET, RISC machine, GaAs microprocessor, instruction execution sequence, III-V semiconductors, microprocessor chips, instruction set architecture, software environment, reduced instruction set computing, 32 bit, field effect integrated circuits, gallium arsenide |
29 | Yashwant K. Malaiya, Sheng Feng |
Design of a testable RISC-to-CISC control architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 21st Annual Workshop and Symposium on Microprogramming and Microarchitecture, 1988, San Diego, California, USA, November 28 - December 2, 1988, pp. 57-59, 1988, ACM/IEEE, 0-8186-1919-8. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP BibTeX RDF |
RISC |
29 | Manuel Alfonseca 0001, David Selby |
APL2 - A RISC Business. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APL ![In: Proceedings of the international conference on APL, APL 1988, Sydney, Australia, February 1-5, 1988., pp. 1-4, 1988, ACM, 0-89791-253-5. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
IBM System/370, APL, RISC, IBM PC |
29 | Jack W. Davidson, Joseph V. Gresh |
Cint: a RISC interpreter for the C programming language. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PLDI ![In: Proceedings of the Symposium on Interpreters and Interpretive Techniques, 1987, St. Paul, Minnesota, USA, June 24 - 26, 1987, pp. 189-198, 1987, ACM, 0-89791-235-7. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
C, RISC |
29 | Yuval Tamir, Carlo H. Séquin |
Strategies for Managing the Register File in RISC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 32(11), pp. 977-989, 1983. The full citation details ...](Pics/full.jpeg) |
1983 |
DBLP DOI BibTeX RDF |
VLSI processor, Cache fetch strategies, register file management, computer architecture, RISC, procedure calls |
27 | Wolfgang Windsteiger, Bruno Buchberger, Markus Rosenkranz |
Theorema. ![Search on Bibsonomy](Pics/bibsonomy.png) |
The Seventeen Provers of the World ![In: The Seventeen Provers of the World, Foreword by Dana S. Scott, pp. 96-107, 2006, Springer, 3-540-30704-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
27 | Fei Gao, Suleyman Sair |
Exploiting Intra-function Correlation with the Global History Stack. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAMOS ![In: Embedded Computer Systems: Architectures, Modeling, and Simulation 5th International Workshop, SAMOS 2005, Samos, Greece, July 18-20, 2005, Proceedings, pp. 172-181, 2005, Springer, 3-540-26969-X. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
27 | Wayne Lyons |
Meeting the Embedded Design Needs of Automotive Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2005 Design, Automation and Test in Europe Conference and Exposition (DATE 2005), 7-11 March 2005, Munich, Germany, pp. 142-147, 2005, IEEE Computer Society, 0-7695-2288-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
27 | V. Parthasarathy, S. Aram valartha Bharathi, V. Rhymend Uthariaraj |
Performance Analysis of Embedded Media Applications in Newer ARM Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPP Workshops ![In: 34th International Conference on Parallel Processing Workshops (ICPP 2005 Workshops), 14-17 June 2005, Oslo, Norway, pp. 210-214, 2005, IEEE Computer Society, 0-7695-2381-1. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
ARM v6, DSP Extensions, Instruction set architecture (ISA), Single Instruction Multiple Data (SIMD) |
27 | Shiliang Hu, James E. Smith 0001 |
Using Dynamic Binary Translation to Fuse Dependent Instructions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CGO ![In: 2nd IEEE / ACM International Symposium on Code Generation and Optimization (CGO 2004), 20-24 March 2004, San Jose, CA, USA, pp. 213-226, 2004, IEEE Computer Society, 0-7695-2102-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
27 | Matías J. Garrido, César Sanz, Marcos Jiménez, Juan M. Meneses |
A Flexible H.263 Video Coder Prototype Based on FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE International Workshop on Rapid System Prototyping ![In: 13th IEEE International Workshop on Rapid System Prototyping (RSP 2002), 1-3 July 2002, Darmstadt, Germany, pp. 34-41, 2002, IEEE Computer Society, 0-7695-1703-X. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
27 | Rolf B. Hilgendorf, Wolfram Sauer |
Instruction translation for an experimental S/390 processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGARCH Comput. Archit. News ![In: SIGARCH Comput. Archit. News 29(1), pp. 37-42, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
IBM System/390 |
27 | Naehyuck Chang, Kwanho Kim, Hyung Gyu Lee |
Cycle-accurate energy consumption measurement and analysis: case study of ARM7TDMI. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000, Rapallo, Italy, July 25-27, 2000, pp. 185-190, 2000, ACM, 1-58113-190-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
27 | Ryuichi Takahashi, Noriyoshi Yoshida |
Diagonal Examples for Design Space Exploration in an Educational Environment CITY-1. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MSE ![In: IEEE International Conference on Microelectronic Systems Education, MSE 1999, Arlington, Virginia, USA, July 19-21, 1999, pp. 71-73, 1999, IEEE Computer Society, 0-7695-0312-8. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
27 | Giuliano Donzellini, Stefano Nervi, Domenico Ponta, Sergio Rossi, Stefano Rovetta |
Object Oriented ARM7 Coprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HICSS (3) ![In: Thirty-First Annual Hawaii International Conference on System Sciences, Kohala Coast, Hawaii, USA, January 6-9, 1998, pp. 243-252, 1998, IEEE Computer Society, 0-8186-8255-8. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
26 | Yao-Ming Kuo, Mark F. Flanagan, Francisco Garcia-Herrero, Oscar Ruano, Juan Antonio Maestro |
Integration of a Real-Time CCSDS 410.0-B-32 Error-Correction Decoder on FPGA-Based RISC-V SoCs Using RISC-V Vector Extension. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Aerosp. Electron. Syst. ![In: IEEE Trans. Aerosp. Electron. Syst. 59(5), pp. 5835-5846, October 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
26 | Nick Brown 0001, Maurice Jamieson, Joseph K. L. Lee, Paul Wang |
Is RISC-V ready for HPC prime-time: Evaluating the 64-core Sophon SG2042 RISC-V CPU. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2309.00381, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
26 | Loïc Buckwell, Olivier Gilles, Daniel Gracia Pérez, Nikolai Kosmatov |
Execution at RISC: Stealth JOP Attacks on RISC-V Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2307.12648, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
26 | Loïc Buckwell, Olivier Gilles, Daniel Gracia Pérez, Nikolai Kosmatov |
Execution at RISC: Stealth JOP Attacks on RISC-V Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESORICS Workshops (2) ![In: Computer Security. ESORICS 2023 International Workshops - CPS4CIP, ADIoT, SecAssure, WASP, TAURIN, PriST-AI, and SECAI, The Hague, The Netherlands, September 25-29, 2023, Revised Selected Papers, Part II, pp. 377-391, 2023, Springer, 978-3-031-54128-5. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
26 | Lukas Gerlach 0001, Daniel Weber 0007, Ruiyi Zhang, Michael Schwarz 0001 |
A Security RISC: Microarchitectural Attacks on Hardware RISC-V CPUs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SP ![In: 44th IEEE Symposium on Security and Privacy, SP 2023, San Francisco, CA, USA, May 21-25, 2023, pp. 2321-2338, 2023, IEEE, 978-1-6654-9336-9. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
26 | Nick Brown 0002, Maurice Jamieson, Joseph K. L. Lee, Paul Wang |
Is RISC-V ready for HPC prime-time: Evaluating the 64-core Sophon SG2042 RISC-V CPU. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SC Workshops ![In: Proceedings of the SC '23 Workshops of The International Conference on High Performance Computing, Network, Storage, and Analysis, SC-W 2023, Denver, CO, USA, November 12-17, 2023, pp. 1566-1574, 2023, ACM. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
26 | Rieul Ducousso |
Sécurisation des accès aux périphériques et depuis les périphériques dans une architecture multicœur RISC-V utilisée pour la virtualisation. (Securing access to and from devices in a RISC-V multicore architecture used for virtualization). ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2023 |
RDF |
|
26 | Farhad Taheri, Siavash Bayat Sarmadi, Shahriar Hadayeghparast |
RISC-HD: Lightweight RISC-V Processor for Efficient Hyperdimensional Computing Inference. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Internet Things J. ![In: IEEE Internet Things J. 9(23), pp. 24030-24037, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
26 | Olivier Gilles, Franck Viguier, Nikolai Kosmatov, Daniel Gracia Pérez |
Control-Flow Integrity at RISC: Attacking RISC-V by Jump-Oriented Programming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2211.16212, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
26 | Nils-Johan Wessman, Fabio Malatesta, Stefano Ribes, Jan Andersson, Antonio García-Vilanova, Miguel Masmano, Vicente Nicolau, Paco Gomez, Jimmy Le Rhun, Sergi Alcaide, Guillem Cabo, Francisco Bas, Pedro Benedicte, Fabio Mazzocchetti, Jaume Abella 0001 |
De-RISC: A Complete RISC-V Based Space-Grade Platform. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2022 Design, Automation & Test in Europe Conference & Exhibition, DATE 2022, Antwerp, Belgium, March 14-23, 2022, pp. 802-807, 2022, IEEE, 978-3-9819263-6-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
26 | Christopher Nitta, Aaron Kaloti, Shuotong Wang |
RISC-V Console: A Containerized RISC-V Based Game Console Emulator for Education. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITiCSE (1) ![In: ITiCSE 2022: Innovation and Technology in Computer Science Education, Dublin, Ireland, July 8 - 13, 2022, Volume 1, pp. 145-150, 2022, ACM, 978-1-4503-9201-3. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
26 | Marc Reichenbach, Johannes Knödtel, Sebastian Rachuj, Dietmar Fey |
RISC-V3: A RISC-V Compatible CPU With a Data Path Based on Redundant Number Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 9, pp. 43684-43700, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
26 | Taoran Xiang, Lunkai Zhang, Shuqian An, Xiaochun Ye, Mingzhe Zhang, Yanhuan Liu, Mingyu Yan, Da Wang, Hao Zhang 0009, Wenming Li, Ninghui Sun, Dongrui Fan |
RISC-NN: Use RISC, NOT CISC as Neural Network Hardware Infrastructure. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2103.12393, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP BibTeX RDF |
|
26 | Yu Liu, Kejiang Ye, Cheng-Zhong Xu 0001 |
Performance Evaluation of Various RISC Processor Systems: A Case Study on ARM, MIPS and RISC-V. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CLOUD ![In: Cloud Computing - CLOUD 2021 - 14th International Conference, Held as Part of the Services Conference Federation, SCF 2021, Virtual Event, December 10-14, 2021, Proceedings, pp. 61-74, 2021, Springer, 978-3-030-96325-5. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
26 | Qiang Jiao, Wei Hu 0001, Fang Liu 0031, Yong Dong |
RISC-VTF: RISC-V Based Extended Instruction Set for Transformer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SMC ![In: 2021 IEEE International Conference on Systems, Man, and Cybernetics, SMC 2021, Melbourne, Australia, October 17-20, 2021, pp. 1565-1570, 2021, IEEE, 978-1-6654-4207-7. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
26 | Karyofyllis Patsidis, Chrysostomos Nicopoulos, Georgios Ch. Sirakoulis, Giorgos Dimitrakopoulos |
RISC-V2: A Scalable RISC-V Vector Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2020, Sevilla, Spain, October 10-21, 2020, pp. 1-5, 2020, IEEE, 978-1-7281-3320-1. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
26 | Mark Akoev, Olga Moskaleva, Vladimir Pislyakov |
Confidence and RISC: How Russian papers indexed in the national citation database Russian Index of Science Citation (RISC) characterize universities and research institutes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1808.05701, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP BibTeX RDF |
|
26 | Christoph Baumhof, Frank Müller, Otto Müller, Manfred Schlett |
A novel 32 bit RISC architecture unifying RISC and DSP. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICASSP ![In: 1997 IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP '97, Munich, Germany, April 21-24, 1997, pp. 587-590, 1997, IEEE Computer Society, 0-8186-7919-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
26 | Ulrich Golze |
Der RISC-Prozessor TOOBSIE - Hintergrundband zum Buch "VLSI-Entwurf eines RISC-Prozessors" für den Entwurfsspezialisten. ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
1995 |
RDF |
|
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