Search results for "RLC"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
97	Vit Krichl	SDU Discard Function of RLC Protocol in UMTS. (PDF / PS)	PWC	2007	DBLP DOI BibTeX RDF	Radio Link Control, SDU discard, performance, UMTS, RLC
90	Wei Luo, Krishna Balachandran, Sanjiv Nanda, K. K. Chang	Delay analysis of selective-repeat ARQ with applications to link adaptation in wireless packet data systems.	IEEE Trans. Wirel. Commun.	2005	DBLP DOI BibTeX RDF
86	Juan J. Alcaraz, Fernando Cerdán, Joan García-Haro	Optimizing TCP and RLC interaction in the UMTS radio access network.	IEEE Netw.	2006	DBLP DOI BibTeX RDF
86	Yehea I. Ismail, Eby G. Friedman	Repeater insertion in RLC lines for minimum propagation delay.	ISCAS (6)	1999	DBLP DOI BibTeX RDF
84	Zuying Luo, Yici Cai, Sheldon X.-D. Tan, Xianlong Hong, Xiaoyi Wang, Zhu Pan, Jingjing Fu	Time-domain analysis methodology for large-scale RLC circuits and its applications.	Sci. China Ser. F Inf. Sci.	2006	DBLP DOI BibTeX RDF	RLC circuits, analog circuit analysis, P/G networks, algorithm complexity, time-domain analysis
74	Fan Yang 0001, Xuan Zeng 0001, Yangfeng Su, Dian Zhou	RLCSYN: RLC Equivalent Circuit Synthesis for Structure-Preserved Reduced-order Model of Interconnect.	ISCAS	2007	DBLP DOI BibTeX RDF
74	Boyuan Yan, Sheldon X.-D. Tan, Pu Liu, Bruce McGaughy	SBPOR: Second-Order Balanced Truncation for Passive Order Reduction of RLC Circuits.	DAC	2007	DBLP DOI BibTeX RDF
74	Jinjun Xiong, Lei He 0001	Full-chip routing optimization with RLC crosstalk budgeting.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
74	Yehea I. Ismail, Eby G. Friedman, José Luis Neves	Inductance Effects in RLC Trees.	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF
67	Juan J. Alcaraz, Gaspar Pedreño, Fernando Cerdán, Joan García-Haro	Simulation of 3G DCHs supporting TCP traffic: design, experiments and insights on parameter tuning.	SimuTools	2008	DBLP DOI BibTeX RDF	simulation, TCP, 3G, OMNeT++, parameter setting, RLC
63	Chia-Chun Tsai, Jan-Ou Wu, Trong-Yen Lee, Rong-Shue Hsiao	Propagation Delay Minimization on RLC-Based Bus with Repeater Insertion.	APCCAS	2006	DBLP DOI BibTeX RDF
63	Yu Cao 0001, Xiaodong Yang, Xuejue Huang, Dennis Sylvester	Switch-factor based loop RLC modeling for efficient timing analysis.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
63	Kai-Sheng Lu, Guo-Zhang Gao	The node voltage equations and structural conditions of observability for RLC networks over F(z).	ISCAS (1)	2005	DBLP DOI BibTeX RDF
63	Xiao Xu, Yi-Chiun Chen, Hua Xu, Eren Gonen, Peijuan Liu	Parallel and distributed systems: simulation analysis of RLC timers in UMTS systems.	WSC	2002	DBLP DOI BibTeX RDF
63	James D. Z. Ma, Lei He 0001	Towards global routing with RLC crosstalk constraints.	DAC	2002	DBLP DOI BibTeX RDF
63	Yehea I. Ismail, Eby G. Friedman, José Luis Neves	Equivalent Elmore delay for RLC trees.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
63	Kevin J. Kerns, Andrew T. Yang	Preservation of passivity during RLC network reduction via split congruence transformations.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
62	Chia-Chun Tsai, Jan-Ou Wu, Chung-Chieh Kuo, Trong-Yen Lee, Wen-Ta Lee	Zero-Skew Driven for RLC Clock Tree Construction in SoC.	ICITA (1)	2005	DBLP DOI BibTeX RDF	RLC delay model, Upward propagation, SoC, Clock tree, Zero skew
62	Yu Cao 0001, Xiaodong Yang, Xuejue Huang, Dennis Sylvester	Switch-Factor Based Loop RLC Modeling for Efficient Timing Analysis.	ICCAD	2003	DBLP DOI BibTeX RDF	RLC model, loop inductance, switch-factor, current return loop, data-bus and clock, static timing analysis, slew rate
62	Raguraman Venkatesan, Jeffrey A. Davis, James D. Meindl	A physical model for the transient response of capacitively loaded distributed rlc interconnects.	DAC	2002	DBLP DOI BibTeX RDF	distributed rlc lines, overshoot, interconnects, crosstalk, time delay, repeaters, transient response
62	Jason Cong, Cheng-Kok Koh	Interconnect layout optimization under higher-order RLC model.	ICCAD	1997	DBLP DOI BibTeX RDF	RATS trees, Steiner routings, bounded-radius Steiner trees, higher-order RLC model, incremental moment computation algorithm, interconnect layout optimization, nonmonotone signal response, required-arrival-time Steiner trees, resistance-inductance-capacitance circuits, routing area, routing cost, routing topologies, shortest-path Steiner trees, signal delay, signal settling time, voltage overshoot, waveform optimization, waveform quality evaluation, wire-sizing optimization, circuit optimisation, topology optimization, delay optimization
56	Yungseon Eo, Jongin Shim, William R. Eisenstadt	A traveling-wave-based waveform approximation technique for thetiming verification of single transmission lines.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
56	Yehea I. Ismail, Eby G. Friedman	DTT: direct truncation of the transfer function - an alternative tomoment matching for tree structured interconnect.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
56	Yehea I. Ismail, Eby G. Friedman	Effects of inductance on the propagation delay and repeater insertion in VLSI circuits.	IEEE Trans. Very Large Scale Integr. Syst.	2000	DBLP DOI BibTeX RDF
52	Massimo Alioto, Massimo Poli, Gaetano Palumbo	Explicit energy evaluation in RLC tree circuits with ramp inputs.	ISCAS	2008	DBLP DOI BibTeX RDF
52	Zhanyuan Jiang, Shiyan Hu, Jiang Hu, Zhuo Li 0001, Weiping Shi	A new RLC buffer insertion algorithm.	ICCAD	2006	DBLP DOI BibTeX RDF
52	Jinjun Xiong, Lei He 0001	Extended global routing with RLC crosstalk constraints.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
52	Lacina M. Coulibaly, H. J. Kadim	Analytical crosstalk noise and its induced-delay estimation for distributed RLC interconnects under ramp excitation.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
52	Quming Zhou, Kartik Mohanram	Analysis of delay caused by bridging faults in RLC interconnects.	ITC	2004	DBLP DOI BibTeX RDF
52	Jinjun Xiong, Jun Chen 0008, James D. Z. Ma, Lei He 0001	Post global routing RLC crosstalk budgeting.	ICCAD	2002	DBLP DOI BibTeX RDF
52	Yehea I. Ismail, Eby G. Friedman, José Luis Neves	Signal waveform characterization in RLC trees.	ISCAS (6)	1999	DBLP DOI BibTeX RDF
51	J. V. R. Ravindra, Srinivas Bala Mandalika	Modeling and analysis of crosstalk for distributed RLC interconnects using difference model approach.	SBCCI	2007	DBLP DOI BibTeX RDF	RC, distributed RLC, interconnect, SPICE, circuit, RL
51	Selim G. Akl, Weiguang Yao	A Parallel Approach Eliminates Measurement Perturbations in RLC Circuits.	J. Supercomput.	2006	DBLP DOI BibTeX RDF	RLC-circuit, parallel computation, measurement, dynamical system, oscillation, perturbation, damping
51	Yuichi Tanji, Hideki Asai	Closed-form expressions of distributed RLC interconnects for analysis of on-chip inductance effects.	DAC	2004	DBLP DOI BibTeX RDF	RLC distributed interconnects, inductance effects
51	Falah R. Awwad, Mohamed Nekili	Variable-segment & variable-driver parallel regeneration techniques for RLC VLSI interconnects.	ACM Great Lakes Symposium on VLSI	2002	DBLP DOI BibTeX RDF	parallel regeneration, VLSI, repeater, RLC interconnect
51	Q. Su, Venkataramanan Balakrishnan, Cheng-Kok Koh	Efficient Approximate Balanced Truncation of General Large-Scale RLC Systems via Krylov Methods.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF	Krylov, large scale systems, model reduction, RLC interconnects, balanced truncation
51	Q. Su, Venkataramanan Balakrishnan, Cheng-Kok Koh	A factorization-based framework for passivity-preserving model reduction of RLC systems.	DAC	2002	DBLP DOI BibTeX RDF	passivity preserving, factorization, large scale systems, model reduction, RLC interconnect
45	Supratim Deb, Muriel Médard, Clifford Choute	Algebraic gossip: a network coding approach to optimal multiple rumor mongering.	IEEE Trans. Inf. Theory	2006	DBLP DOI BibTeX RDF	message dissemination, network coding, gossip algorithms
45	N. Enderle, Xavier Lagrange	Radio link control-acknowledged mode protocol performance modeling in UMTS.	MWCN	2002	DBLP DOI BibTeX RDF
45	Yehea I. Ismail, Eby G. Friedman, José Luis Neves	Figures of merit to characterize the importance of on-chip inductance.	IEEE Trans. Very Large Scale Integr. Syst.	1999	DBLP DOI BibTeX RDF
45	Yehea I. Ismail, Eby G. Friedman, José Luis Neves	Repeater insertion in tree structured inductive interconnect.	ICCAD	1999	DBLP DOI BibTeX RDF
45	Yehea I. Ismail, Eby G. Friedman, José Luis Neves	Figures of Merit to Characterize the Importance of On-Chip Inductance.	DAC	1998	DBLP DOI BibTeX RDF
44	George Xylomenos, Michael Makidis	Adaptive link layer protocols for shared wireless links.	MobiMedia	2007	DBLP DOI BibTeX RDF	selective repeat, UMTS, link layer, RLC
44	Liang Zhang 0038, Wentai Liu, Rizwan Bashirullah, John M. Wilson 0002, Paul D. Franzon	Simplified delay design guidelines for on-chip global interconnects.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	effective attenuation constant, first incident switching, lossy transmission line, delay, global interconnects, RLC
43	Boyuan Yan, Sheldon X.-D. Tan, Pu Liu, Bruce McGaughy	Passive Interconnect Macromodeling Via Balanced Truncation of Linear Systems in Descriptor Form.	ASP-DAC	2007	DBLP DOI BibTeX RDF	moment-matching methods, passive interconnect macromodeling, descriptor form, passive model order reduction, projection-based truncated balanced realization method, large RLC interconnect circuits, Lur'e equation, algebraic Riccati equations, generalized Lyapunov equations, passivity preservation, congruence transformation, large scale interconnect circuit, linear systems, structure information, Krylov-subspace methods, block structure, balanced truncation
43	Altan Odabasioglu, Mustafa Celik, Lawrence T. Pileggi	PRIMA: passive reduced-order interconnect macromodeling algorithm.	ICCAD	1997	DBLP DOI BibTeX RDF	MPVL, PRIMA, RLC interconnect circuits, block Arnoldi technique, driver-load models, guaranteed passivity, macromodel passivity, macromodel stability, passive reduced-order interconnect macromodeling algorithm, path tracing algorithm, reduced order N-port models, simulation, CAD, integrated circuit layout, frequency domain, circuit stability
41	DiaaEldin Khalil, Yehea I. Ismail	Approximate Frequency Response Models for RLC Power Grids.	ISCAS	2007	DBLP DOI BibTeX RDF
41	Zhanyuan Jiang, Shiyan Hu, Jiang Hu, Weiping Shi	An Efficient Algorithm for RLC Buffer Insertion.	ISQED	2007	DBLP DOI BibTeX RDF
41	Kanak Agarwal, Dennis Sylvester, David T. Blaauw	Modeling and analysis of crosstalk noise in coupled RLC interconnects.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
41	Shang-Wei Tu, Yao-Wen Chang, Jing-Yang Jou	RLC Coupling-Aware Simulation and On-Chip Bus Encoding for Delay Reduction.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
41	Guoqing Chen, Eby G. Friedman	Effective capacitance of RLC loads for estimating short-circuit power.	ISCAS	2006	DBLP DOI BibTeX RDF
41	Guoqing Chen, Eby G. Friedman	Low power repeaters driving RLC interconnects with delay and bandwidth constraints.	ISCAS (1)	2005	DBLP DOI BibTeX RDF
41	Kanak Agarwal, Dennis Sylvester, David T. Blaauw	A library compatible driver output model for on-chip RLC transmission lines.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
41	Kanak Agarwal, Dennis Sylvester, David T. Blaauw	A simplified transmission-line based crosstalk noise model for on-chip RLC wiring.	ASP-DAC	2004	DBLP DOI BibTeX RDF
41	Herng-Jer Lee, Chia-Chi Chu, Wu-Shiung Feng	Moment Computations of Nonuniform Distributed Coupled RLC Trees with Applications to Estimating Crosstalk Noise.	ISQED	2004	DBLP DOI BibTeX RDF
41	Noha H. Mahmoud, Yehea I. Ismail	Accurate rise time and overshoots estimation in RLC interconnects.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
41	Kaustav Banerjee, Amit Mehrotra	Analysis of on-chip inductance effects for distributed RLC interconnects.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
41	Qinwei Xu, Pinaki Mazumder, Li Ding 0002	Novel macromodeling for on-chip RC/RLC interconnects.	ISCAS (4)	2002	DBLP DOI BibTeX RDF
41	Jun Chen 0008, Lei He 0001	A decoupling method for analysis of coupled RLC interconnects.	ACM Great Lakes Symposium on VLSI	2002	DBLP DOI BibTeX RDF
41	Herng-Jer Lee, Chia-Chi Chu, Wu-Shiung Feng	Crosstalk estimation in high-speed VLSI interconnect using coupled RLC-tree models.	APCCAS (1)	2002	DBLP DOI BibTeX RDF
41	Liang Yin, Lei He 0001	An efficient analytical model of coupled on-chip RLC interconnects.	ASP-DAC	2001	DBLP DOI BibTeX RDF
41	Norman Chang, Shen Lin, O. Sam Nakagawa, Weize Xie, Lei He 0001	Clocktree RLC Extraction with Efficient Inductance Modeling.	DATE	2000	DBLP DOI BibTeX RDF
41	Bernard N. Sheehan	Projective Convolution: RLC Model-Order Reduction Using the Impulse Response.	DATE	1999	DBLP DOI BibTeX RDF
41	Xiaodong Yang, Walter H. Ku, Chung-Kuan Cheng	RLC interconnect delay estimation via moments of amplitude and phase response.	ICCAD	1999	DBLP DOI BibTeX RDF
41	Altan Odabasioglu, Mustafa Celik, Lawrence T. Pileggi	Practical considerations for passive reduction of RLC circuits.	ICCAD	1999	DBLP DOI BibTeX RDF
41	Kunsheng Lu, Kai-Sheng Lu	Controllability and observability of RLC networks over F(z).	ISCAS (5)	1999	DBLP DOI BibTeX RDF
41	Ibrahim M. Elfadel, David D. Ling	A block rational Arnoldi algorithm for multipoint passive model-order reduction of multiport RLC networks.	ICCAD	1997	DBLP DOI BibTeX RDF	Arnoldi iteration, multipoint Pade' approximation, passivity, model-order reduction
41	Kevin J. Kerns, Andrew T. Yang	Preservation of Passivity During RLC Network Reduction via Split Congruence Transformations.	DAC	1997	DBLP DOI BibTeX RDF
41	Luís Miguel Silveira, Mattan Kamon, Ibrahim M. Elfadel, Jacob White 0001	A coordinate-transformed Arnoldi algorithm for generating guaranteed stable reduced-order models of RLC circuits.	ICCAD	1996	DBLP DOI BibTeX RDF
40	Magdy A. El-Moursy, Eby G. Friedman	Optimum wire sizing of RLC interconnect with repeaters.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	power delay product, transient power dissipation, propagation delay, repeater insertion, wire sizing, RLC interconnect
34	Shanq-Jang Ruan, Tsang-Chi Kan, Jih-Chieh Hsu	A novel crosstalk quantitative approach for simultaneously reducing power, noise, and delay based on bus-invert encoding schemes.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	bus-invert, coupling, interconnect delay
34	George Xylomenos, Michael Makidis	Link Layer Adaptation for Shared Wireless Links.	Mob. Networks Appl.	2008	DBLP DOI BibTeX RDF	adaptive selective repeat, radio link control, link layer protocols
34	Yikang Xiang, Tao Jin, Jijun Luo, Egon Schulz, Carmelita Görg	User Plane Protocol Optimization in Cellular Networks with Decode-and-Forward Type of Relay.	VTC Spring	2008	DBLP DOI BibTeX RDF
34	Ahmed Shebaita, Dusan Petranovic, Yehea I. Ismail	Including inductance in static timing analysis.	ICCAD	2007	DBLP DOI BibTeX RDF
34	Li-Chun Wang 0001, Chih-Wen Chang	Gap Processing Time Analysis of Stall Avoidance Schemes for High-Speed Downlink Packet Access with Parallel HARQ Mechanisms.	IEEE Trans. Mob. Comput.	2006	DBLP DOI BibTeX RDF	stall, stall avoidance, multichannel SAW HARQ, gap processing time, HSDPA, HARQ
34	Umberto Manzoli, Maria Luisa Merani	Goodput and delay analysis of a radio link control protocol operating over a multicarrier DS-CDMA architecture.	IEEE Trans. Wirel. Commun.	2006	DBLP DOI BibTeX RDF
34	Denis Deschacht	DSM interconnects: importance of inductance effects and corresponding range of length.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
34	Sara Arasteh, Chih-Cheng Hung, Enmin Song	Adaptive dynamic run-length coding for image segmentation.	SAC	2006	DBLP DOI BibTeX RDF	dynamic run-length coding, image segmentation
34	Juan J. Alcaraz, Fernando Cerdán	Performance Evaluation of AQM Schemes in Rate-Varying 3G Links. (PDF / PS)	PWC	2006	DBLP DOI BibTeX RDF
34	Magdy A. El-Moursy, Eby G. Friedman	Shielding effect of on-chip interconnect inductance.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
34	Jun Chen 0008, Lei He 0001	Worst case crosstalk noise for nonswitching victims in high-speed buses.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
34	Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera	Representative frequency for interconnect R(f)L(f)C extraction.	ASP-DAC	2004	DBLP DOI BibTeX RDF
34	Roland W. Freund	SPRIM: structure-preserving reduced-order interconnect macromodeling.	ICCAD	2004	DBLP DOI BibTeX RDF
34	Yu Cao 0001, Xuejue Huang, N. H. Chang, Shen Lin, O. Sam Nakagawa, Weize Xie, Dennis Sylvester, Chenming Hu	Effective on-chip inductance modeling for multiple signal lines and application to repeater insertion.	IEEE Trans. Very Large Scale Integr. Syst.	2002	DBLP DOI BibTeX RDF
34	Yu Cao 0001, Xuejue Huang, Chenming Hu, Norman Chang, Shen Lin, O. Sam Nakagawa, Weize Xie	Effective On-chip Inductance Modeling for Multiple Signal Lines and Application on Repeater Insertion.	ISQED	2001	DBLP DOI BibTeX RDF
33	Shizhong Mei, Chirayu S. Amin, Yehea I. Ismail	Efficient model order reduction including skin effect.	DAC	2003	DBLP DOI BibTeX RDF	simulation, VLSI, model order reduction, skin effect, RLC
32	Sunghoon Chun, YongJoon Kim, Sungho Kang 0001	MDSI: Signal Integrity Interconnect Fault Modeling and Testing for SoCs.	J. Electron. Test.	2007	DBLP DOI BibTeX RDF	RLC interconnect model, fault modeling, signal integrity, interconnect test
32	Juan J. Alcaraz, Fernando Cerdán	Combining ACK rate control and AQM to enhance TCP performance over 3G links.	PM2HW2N	2006	DBLP DOI BibTeX RDF	TCP over 3G links, radio link control (RLC)
32	Andrew B. Kahng, Kei Masuko, Sudhakar Muddu	Analytical delay models for VLSI interconnects under ramp input.	ICCAD	1996	DBLP DOI BibTeX RDF	SPICE-computed delay, VLSI routing topologies layout, analytical delay models, arbitrary interconnect trees, interconnect transfer function, performance-driven synthesis, ramp input, source-sink delays, VLSI, Elmore delay, interconnect delays, VLSI interconnects, RLC interconnections
30	Kaveh Shakeri, James D. Meindl	Accelerated Modeling of Massively Coupled RLC Interconnects Using the Relative Inductance Extraction Method.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
30	Peng-Yang Hung, Ying-Shu Lou, Yih-Lang Li	Minimum Shield Insertion on Full-Chip RLC Crosstalk Budgeting Routing.	ISQED	2008	DBLP DOI BibTeX RDF	Shield insertion, track routing, crosstalk optimization, global routing
30	Taehoon Kim, Dongchul Kim, Jung-A Lee, Yungseon Eo	Compact Models for Signal Transient and Crosstalk Noise of Coupled RLC Interconnect Lines with Ramp Inputs.	DELTA	2008	DBLP DOI BibTeX RDF	inductance effect, signal transient, crosstalk, transmission lines
30	Shanq-Jang Ruan, Shang-Fang Tsai, Yu-Ting Pai	Design and Analysis of Low Power Dynamic Bus Based on RLC simulation.	ISVLSI	2007	DBLP DOI BibTeX RDF
30	Guoqing Chen, Eby G. Friedman	Low-power repeaters driving RC and RLC interconnects with delay and bandwidth constraints.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
30	Junmou Zhang, Eby G. Friedman	Crosstalk modeling for coupled RLC interconnects with application to shield insertion.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
30	Yuichi Tanji, Takayuki Watanabe, Hidemasa Kubota, Hideki Asai	Large scale RLC circuit analysis using RLCG-MNA formulation.	DATE	2006	DBLP DOI BibTeX RDF
30	Trong-Yen Lee, Yang-Hsin Fan, Chia-Chun Tsai	Reduction of RLC Tree Delay Using Bidirectional Buffer Repeater Insertion.	ICICIC (2)	2006	DBLP DOI BibTeX RDF
30	Magdy A. El-Moursy, Eby G. Friedman	Optimum wire tapering for minimum power dissipation in RLC interconnects.	ISCAS	2006	DBLP DOI BibTeX RDF
30	H. J. Kadim, Lacina M. Coulibaly	Wave propagation based analytical model for distributed on-chip RLC interconnects.	ISCAS	2006	DBLP DOI BibTeX RDF
30	Chia-Chun Tsai, Jan-Ou Wu, Chien-Wen Kao, Trong-Yen Lee, Rong-Shue Hsiao	Coupling aware RLC-based clock routings for crosstalk minimization.	ISCAS	2006	DBLP DOI BibTeX RDF