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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 27 occurrences of 25 keywords
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Results
Found 30 publication records. Showing 30 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
138 | Richard H. Stern |
Coming down the home stretch in the Rambus standardization skullduggery saga: To levy or not to levy royalties. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Micro ![In: IEEE Micro 27(2), pp. 80-82, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Rambus, antitrust violation, skullduggery, Secret Squirrel, DDR SDRAM, JEDEC, standardization, law, patents, SDRAM |
110 | Richard H. Stern |
FTC Piles onto Rambus' Standardization Skullduggery. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Micro ![In: IEEE Micro 22(4), pp. 6-7, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
96 | Richard H. Stern |
Another Update on Standardization Skullduggery. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Micro ![In: IEEE Micro 21(5), pp. 8-10, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
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96 | Richard H. Stern |
More standardization skullduggery. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Micro ![In: IEEE Micro 21(4), pp. 12-15, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
91 | Richard H. Stern |
Weird Turn of Events in Continuing Rambus Saga. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Micro ![In: IEEE Micro 23(1), pp. 76-80, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
86 | Wei-Fen Lin, Steven K. Reinhardt, Doug Burger |
Designing a Modern Memory Hierarchy with Hardware Prefetching. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 50(11), pp. 1202-1218, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
Rambus DRAM, caches, Prefetching, memory bandwidth, spatial locality, memory system design |
71 | Philip Machanick, Pierre Salverda, Lance Pompe |
Hardware-Software Trade-Offs in a Direct Rambus Implementation of the RAMpage Memory Hierarchy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASPLOS ![In: ASPLOS-VIII Proceedings of the 8th International Conference on Architectural Support for Programming Languages and Operating Systems, San Jose, California, USA, October 3-7, 1998., pp. 105-114, 1998, ACM Press, 1-58113-107-0. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
67 | Vinodh Cuppu, Bruce L. Jacob, Brian Davis, Trevor N. Mudge |
High-Performance DRAMs in Workstation Environments. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 50(11), pp. 1133-1153, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
DRAM architectures, DRAM performance, DRAM systems, DDR DRAM, Direct Rambus DRAM, PC100 SDRAM, DDR2 DRAM, system modeling |
67 | J. Bruce Millar, Peter Gillingham |
Two High-Bandwidth Memory Bus Structures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 16(1), pp. 42-52, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
SLDRAM, Direct Rambus, DRAM, memory design |
67 | Mircea R. Stan, Wayne P. Burleson |
Coding a terminated bus for low power. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 5th Great Lakes Symposium on VLSI (GLS-VLSI '95), March 16-18, 1995, The State University of New York at Buffalo, USA, pp. 70-73, 1995, IEEE Computer Society, 0-8186-7035-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
pull-up terminators, bus liner, limited-weight codes, parallel terminated buses, Rambus, perfect k/2-limited weight code, nonperfect 3-limited weight code, error correction codes, encoding, decoding, power dissipation, random-access storage, system buses |
58 | Wei-Fen Lin, Steven K. Reinhardt, Doug Burger |
Reducing DRAM Latencies with an Integrated Memory Hierarchy Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: Proceedings of the Seventh International Symposium on High-Performance Computer Architecture (HPCA'01), Nuevo Leone, Mexico, January 20-24, 2001, pp. 301-312, 2001, IEEE Computer Society, 0-7695-1019-1. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
52 | Sung I. Hong, Sally A. McKee, Maximo H. Salinas, Robert H. Klenke, James H. Aylor, William A. Wulf |
Access Order and Effective Bandwidth for Streams on a Direct Rambus Memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: Proceedings of the Fifth International Symposium on High-Performance Computer Architecture, Orlando, FL, USA, January 9-12, 1999, pp. 80-89, 1999, IEEE Computer Society, 0-7695-0004-8. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
38 | Vinodh Cuppu, Bruce L. Jacob, Brian Davis, Trevor N. Mudge |
A Performance Comparison of Contemporary DRAM Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: Proceedings of the 26th Annual International Symposium on Computer Architecture, ISCA 1999, Atlanta, Georgia, USA, May 2-4, 1999, pp. 222-233, 1999, IEEE Computer Society, 0-7695-0170-2. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
33 | Ibtissem Seghaier, Sofiène Tahar |
Reliability Analysis of CMOS Rambus Oscillator under Device Mismatch Effects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NEWCAS ![In: 16th IEEE International New Circuits and Systems Conference, NEWCAS 2018, Montréal, QC, Canada, June 24-27, 2018, pp. 209-212, 2018, IEEE, 978-1-5386-4859-9. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
33 | Richard H. Stern |
One of the Last Updates on Rambus Standardization Skullduggery. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Micro ![In: IEEE Micro 29(1), pp. 139-143, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
33 | Richard H. Stern |
Micro Law: An End to the Rambus Skullduggery Saga. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Micro ![In: IEEE Micro 29(4), pp. 86, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
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33 | John Privitera, Steven Woo, Craig Soldat |
Pattern generation tools for the development of memory core test patterns for Rambus devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 2000, Atlantic City, NJ, USA, October 2000, pp. 444-453, 2000, IEEE Computer Society, 0-7803-6546-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
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33 | Kazumasa Suzuki, Masayuki Daito, Tomoo Inoue, Kouhei Nadehara, Masahiro Nomura, Masayuki Mizuno, Tomofumi Iima, Shoichiro Sato, Terumi Fukuda, Tomohisa Arai, Ichiro Kuroda, Masakazu Yamashina |
A 2000-MOPS embedded RISC processor with a Rambus DRAM controller. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 34(7), pp. 1010-1021, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
33 | Richard Crisp |
Direct RAMbus technology: the new main memory standard. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Micro ![In: IEEE Micro 17(6), pp. 18-28, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
33 | K. D. Jones, J. P. Privitera |
The Automatic Generation of Functional Test Vectors for Rambus Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 33st Conference on Design Automation, Las Vegas, Nevada, USA, Las Vegas Convention Center, June 3-7, 1996., pp. 415-420, 1996, ACM Press, 0-89791-779-0. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
19 | Mark R. Greenstreet, Suwen Yang |
Verifying start-up conditions for a ring oscillator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, Orlando, Florida, USA, May 4-6, 2008, pp. 201-206, 2008, ACM, 978-1-59593-999-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
formal verification, dynamical systems, oscillators |
19 | Nevine AbouGhazaleh, Bruce R. Childers, Daniel Mossé, Rami G. Melhem |
Near-Memory Caching for Improved Energy Consumption. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 56(11), pp. 1441-1455, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Memory power management, Cached DRAM, Power Management, Energy-aware systems, Memory design |
19 | P. Yeung, A. Torres, P. Batra |
Interactive presentation: Novel test infrastructure and methodology used for accelerated bring-up and in-system characterization of the multi-gigahertz interfaces on the cell processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2007 Design, Automation and Test in Europe Conference and Exposition, DATE 2007, Nice, France, April 16-20, 2007, pp. 725-730, 2007, EDA Consortium, San Jose, CA, USA, 978-3-9810801-2-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
19 | Anand Eswaran, Raj Rajkumar |
Energy-Aware Memory Firewalling for QoS-Sensitive Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ECRTS ![In: 17th Euromicro Conference on Real-Time Systems (ECRTS 2005), 6-8 July 2005, Palma de Mallorca, Spain, Proceedings, pp. 11-20, 2005, IEEE Computer Society, 0-7695-2400-1. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
19 | Zhichun Zhu, Zhao Zhang 0010 |
A Performance Comparison of DRAM Memory System Optimizations for SMT Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: 11th International Conference on High-Performance Computer Architecture (HPCA-11 2005), 12-16 February 2005, San Francisco, CA, USA, pp. 213-224, 2005, IEEE Computer Society, 0-7695-2275-0. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
19 | Zhichun Zhu, Zhao Zhang 0010, Xiaodong Zhang 0001 |
Fine-Grain Priority Scheduling on Multi-Channel Memory Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: Proceedings of the Eighth International Symposium on High-Performance Computer Architecture (HPCA'02), Boston, Massachusettes, USA, February 2-6, 2002, pp. 107-116, 2002, IEEE Computer Society, 0-7695-1525-8. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
DRAM configurations, fine-grain priority scheduling, memory-intensive applications and multi-channel memory systems |
19 | Vinodh Cuppu, Bruce L. Jacob |
Concurrency, latency, or system overhead: which has the largest impact on uniprocessor DRAM-system performance?. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: Proceedings of the 28th Annual International Symposium on Computer Architecture, ISCA 2001, Göteborg, Sweden, June 30-July 4, 2001, pp. 62-71, 2001, ACM, 0-7695-1162-7. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
Systems Application Architecture |
19 | Sally A. McKee, William A. Wulf, James H. Aylor, Robert H. Klenke, Maximo H. Salinas, Sung I. Hong, Dee A. B. Weikle |
Dynamic Access Ordering for Streamed Computations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 49(11), pp. 1255-1271, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Memory systems architecture, memory access ordering, memory access scheduling, memory bandwidth, memory latency |
19 | Chengqiang Zhang, Sally A. McKee |
Hardware-only stream prefetching and dynamic access ordering. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICS ![In: Proceedings of the 14th international conference on Supercomputing, ICS 2000, Santa Fe, NM, USA, May 8-11, 2000, pp. 167-175, 2000, ACM, 1-58113-270-0. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
19 | Norman Margolus |
An FPGA architecture for DRAM-based systolic computations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 5th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '97), 16-18 April 1997, Napa Valley, CA, USA, pp. 2-11, 1997, IEEE Computer Society, 0-8186-8159-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
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