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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 38 occurrences of 34 keywords
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Results
Found 16 publication records. Showing 16 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
200 | C. P. Ravikumar, Hemant Joshi |
HISCOAP: a hierarchical testability analysis tool. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 272-277, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
HISCOAP, hierarchical testability analysis tool, SCOAP measure, gate-level netlist, SCOAP expression diagrams, VLSI, logic testing, controllability, controllability, sequential circuits, sequential circuits, combinational circuits, combinational circuits, observability, observability, circuit analysis computing, integrated logic circuits, VLSI circuits, functional modules, stuck at fault model |
53 | Waleed K. Al-Assadi, Sindhu Kakarla |
Design for Test of Asynchronous NULL Convention Logic (NCL) Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 25(1), pp. 117-126, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
NULL convention logic (NCL), SCOAP, ATPG, Asynchronous circuits, Design for test (DFT) |
53 | C. P. Ravikumar, Gurjeet S. Saund, Nidhi Agrawal |
A STAFAN-like functional testability measure for register-level circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 4th Asian Test Symposium (ATS '95), November 23-24, 1995. Bangalore, India, pp. 192-198, 1995, IEEE Computer Society, 0-8186-7129-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
functional testability measure, register-level circuits, testability analysis programs, SCOAP, gate-level digital circuits, testability-driven synthesis, busses, F-STAFAN, Sun/SPARC workstation, performance evaluation, fault diagnosis, logic testing, high-level synthesis, statistical analysis, design for testability, fault simulation, fault coverage, circuit analysis computing, adders, multipliers, multiplexers, digital circuit, shift registers, logic gates, reliability theory, stuck-at fault model |
35 | Richa Sharma, G. K. Sharma 0001, Manisha Pattanaik, V. S. S. Prashant |
Structural and SCOAP Features Based Approach for Hardware Trojan Detection Using SHAP and Light Gradient Boosting Model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 39(4), pp. 465-485, August 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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35 | Chi-Wei Chen, Pei-Yu Lo, Wei-Ting Hsu, Chih-Wei Chen, Chin-Wei Tien, Sy-Yen Kuo |
A Hardware Trojan Insertion Framework against Gate-Level Netlist Structural Feature-based and SCOAP-based Detection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MWSCAS ![In: 65th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2022, Fukuoka, Japan, August 7-10, 2022, pp. 1-5, 2022, IEEE, 978-1-6654-0279-8. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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35 | Pei-Yu Lo, Chi-Wei Chen, Wei-Ting Hsu, Chih-Wei Chen, Chin-Wei Tien, Sy-Yen Kuo |
Semi-supervised Trojan Nets Classification Using Anomaly Detection Based on SCOAP Features. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2022, Austin, TX, USA, May 27 - June 1, 2022, pp. 2423-2427, 2022, IEEE, 978-1-6654-8485-5. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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35 | Seyyede Maryam Ghasemy, Maryam Rajabalipanah, Saeideh Sarmadi, Zainalabedin Navabi |
SCOAP-based Directed Random Test Generation for Combinational Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EWDTS ![In: 2019 IEEE East-West Design & Test Symposium, EWDTS 2019, Batumi, Georgia, September 13-16, 2019, pp. 1-5, 2019, IEEE, 978-1-7281-1003-5. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
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35 | Chee Hoo Kok, Chia Yee Ooi, Mehrdad Moghbel, Nordinah Ismail, Hau Sim Choo, Michiko Inoue |
Classification of Trojan Nets Based on SCOAP Values using Supervised Learning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2019, Sapporo, Japan, May 26-29, 2019, pp. 1-5, 2019, IEEE, 978-1-7281-0397-6. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
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35 | Nam Ky Giang, Minkeun Ha, Daeyoung Kim 0001 |
SCoAP: An integration of CoAP protocol with web-based application. ![Search on Bibsonomy](Pics/bibsonomy.png) |
GLOBECOM ![In: 2013 IEEE Global Communications Conference, GLOBECOM 2013, Atlanta, GA, USA, December 9-13, 2013, pp. 2648-2653, 2013, IEEE, 978-1-4799-1353-4. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
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35 | C. P. Ravikumar, Hemant Joshi |
SCOAP-based Testability Analysis from Hierarchical Netlists. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: VLSI Design 7(2), pp. 131-141, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
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35 | Lawrence H. Goldstein, Evelyn L. Thigpen |
SCOAP: Sandia controllability/observability analysis program. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 17th Design Automation Conference, DAC '80, Minneapolis, Minnesota, USA, June 23-25, 1980, pp. 190-196, 1980, ACM/IEEE, 0-89791-020-6. The full citation details ...](Pics/full.jpeg) |
1980 |
DBLP DOI BibTeX RDF |
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23 | Shih-Chieh Chang, Wen-Ben Jone, Shi-Sen Chang |
TAIR: testability analysis by implication reasoning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(1), pp. 152-160, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
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23 | M. H. Konijnenburg, Hans van der Linden, Ad J. van de Goor |
Fault (In)Dependent Cost Estimates and Conflict-Directed Backtracking to Guide Sequential Circuit Test Generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 8th Asian Test Symposium (ATS '99), 16-18 November 1999, Shanghai, China, pp. 185-191, 1999, IEEE Computer Society, 0-7695-0315-2. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
sequential circuit TPG, back-jumping, conflict-directed backtrack, three-state (tri-state) circuit TPG, ATPG, cost estimates |
23 | Kim T. Le, Kewal K. Saluja |
A Heuristic Measure to Maximize Detected Faults per Test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 13(1), pp. 57-60, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
combinational circuit testing, dynamic test compaction, fault selection, test generation, testability measures, backtrace |
23 | Marie-Lise Flottes, R. Pires, Bruno Rouzeyre |
Analyzing testability from behavioral to RT level. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ED&TC ![In: European Design and Test Conference, ED&TC '97, Paris, France, 17-20 March 1997, pp. 158-165, 1997, IEEE Computer Society, 0-8186-7786-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
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23 | Eric Schell, M. Ray Mercer |
CADTOOLS: a CAD algorithm development system. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 22nd ACM/IEEE conference on Design automation, DAC 1985, Las Vegas, Nevada, USA, 1985., pp. 658-666, 1985, ACM, 0-8186-0635-5. The full citation details ...](Pics/full.jpeg) |
1985 |
DBLP DOI BibTeX RDF |
software engineering, CAD |
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