Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
201 | Jinzhan Peng, Guei-Yuan Lueh, Gansha Wu, Xiaogang Gou, Ryan N. Rakvic |
A comprehensive study of hardware/software approaches to improve TLB performance for java applications on embedded systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Memory System Performance and Correctness ![In: Proceedings of the 2006 workshop on Memory System Performance and Correctness, San Jose, California, USA, October 11, 2006, pp. 102-111, 2006, ACM, 1-59593-578-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
TLB performance, Java, embedded system |
169 | Rupak Samanta, Jason Surprise, Rabi N. Mahapatra |
Dynamic Aggregation of Virtual Addresses in TLB Using TCAM Cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 21st International Conference on VLSI Design (VLSI Design 2008), 4-8 January 2008, Hyderabad, India, pp. 243-248, 2008, IEEE Computer Society, 0-7695-3083-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
169 | Yen-Jen Chang, Maofeng Lan |
Two New Techniques Integrated for Energy-Efficient TLB Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 15(1), pp. 13-23, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
156 | Abhishek Bhattacharjee, Margaret Martonosi |
Inter-core cooperative TLB for chip multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASPLOS ![In: Proceedings of the 15th International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2010, Pittsburgh, Pennsylvania, USA, March 13-17, 2010, pp. 359-370, 2010, ACM, 978-1-60558-839-1. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
parallelism, prefetching, translation lookaside buffer |
144 | Yen-Jen Chang |
An ultra low-power TLB design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006, pp. 1122-1127, 2006, European Design and Automation Association, Leuven, Belgium, 3-9810801-1-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
132 | Reiley Jeyapaul, Sandeep Marathe, Aviral Shrivastava |
Code Transformations for TLB Power Reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: VLSI Design 2009: Improving Productivity through Higher Abstraction, The 22nd International Conference on VLSI Design, New Delhi, India, 5-9 January 2009, pp. 413-418, 2009, IEEE Computer Society, 978-0-7695-3506-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
132 | Cheol Ho Park, JaeWoong Chung, Byeong Hag Seong, Yangwoo Roh, Daeyeon Park |
Boosting superpage utilization with the shadow memory and the partial-subblock TLB. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICS ![In: Proceedings of the 14th international conference on Supercomputing, ICS 2000, Santa Fe, NM, USA, May 8-11, 2000, pp. 187-195, 2000, ACM, 1-58113-270-0. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
132 | Madhusudhan Talluri, Mark D. Hill |
Surpassing the TLB Performance of Superpages with Less Operating System Support. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASPLOS ![In: ASPLOS-VI Proceedings - Sixth International Conference on Architectural Support for Programming Languages and Operating Systems, San Jose, California, USA, October 4-7, 1994., pp. 171-182, 1994, ACM Press, 0-89791-660-3. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
123 | Todd M. Austin, Gurindar S. Sohi |
High-Bandwidth Address Translation for Multiple-Issue Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: Proceedings of the 23rd Annual International Symposium on Computer Architecture, Philadelphia, PA, USA, May 22-24, 1996, pp. 158-167, 1996, ACM, 0-89791-786-3. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
119 | Jin-Hyuck Choi, Jung-Hoon Lee, Gi-Ho Park, Shin-Dug Kim |
An Advanced Filtering TLB for Low Power Consumption. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBAC-PAD ![In: 14th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2002), 28-30 October 2002, Vitoria, Espirito Santo, Brazil, pp. 93-99, 2002, IEEE Computer Society, 0-7695-1772-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
107 | Jung-Hoon Lee, Gi-Ho Park, Sung-Bae Park, Shin-Dug Kim |
A selective filter-bank TLB system. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003, Seoul, Korea, August 25-27, 2003, pp. 312-317, 2003, ACM, 1-58113-682-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
performance evaluation, translation lookaside buffer, low power consumption, filtering mechanism |
103 | Chinnakrishnan S. Ballapuram, Kiran Puttaswamy, Gabriel H. Loh, Hsien-Hsin S. Lee |
Entropy-based low power data TLB design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2006 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2006, Seoul, Korea, October 22-25, 2006, pp. 304-311, 2006, ACM, 1-59593-543-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
low-power TLB, spatial and temporal locality, entropy |
98 | Xiaogang Qiu, Michel Dubois 0001 |
Moving Address Translation Closer to Memory in Distributed Shared-Memory Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 16(7), pp. 612-623, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
dynamic address translation, virtual-address caches, simulations, Multiprocessors, distributed shared memory, virtual memory |
98 | David Channon, David Koch |
Performance Analysis of Re-configurable Partitioned TLBs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HICSS (5) ![In: 30th Annual Hawaii International Conference on System Sciences (HICSS-30), 7-10 January 1997, Maui, Hawaii, USA, pp. 168-177, 1997, IEEE Computer Society, 0-8186-7734-1. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
Computer Architecture, Memory Management, Partitioning Algorithm, Address Translation |
95 | Satoshi Yamada, Shigeru Kusakabe |
Effect of context aware scheduler on TLB. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 22nd IEEE International Symposium on Parallel and Distributed Processing, IPDPS 2008, Miami, Florida USA, April 14-18, 2008, pp. 1-8, 2008, IEEE. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
95 | Gokul B. Kandiraju, Anand Sivasubramaniam |
Characterizing the d-TLB behavior of SPEC CPU2000 benchmarks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGMETRICS ![In: Proceedings of the International Conference on Measurements and Modeling of Computer Systems, SIGMETRICS 2002, June 15-19, 2002, Marina Del Rey, California, USA, pp. 129-139, 2002, ACM, 1-58113-531-9. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
95 | Mark R. Swanson, Leigh Stoller, John B. Carter |
Increasing TLB Reach Using Superpages Backed by Shadow Memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: Proceedings of the 25th Annual International Symposium on Computer Architecture, ISCA 1998, Barcelona, Spain, June 27 - July 1, 1998, pp. 204-213, 1998, IEEE Computer Society, 0-8186-8491-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
95 | Theodore H. Romer, Wayne H. Ohlrich, Anna R. Karlin, Brian N. Bershad |
Reducing TLB and Memory Overhead Using Online Superpage Promotion. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: Proceedings of the 22nd Annual International Symposium on Computer Architecture, ISCA '95, Santa Margherita Ligure, Italy, June 22-24, 1995, pp. 176-187, 1995, ACM, 0-89791-698-0. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
92 | Dongrui Fan, Zhimin Tang, Hailin Huang, Guang R. Gao |
An energy efficient TLB design methodology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005, San Diego, California, USA, August 8-10, 2005, pp. 351-356, 2005, ACM, 1-59593-137-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Godson-I, embedded processor design, single-port RAM, energy efficient, TLB, low-power consumption |
91 | Chinnakrishnan S. Ballapuram, Hsien-Hsin S. Lee, Milos Prvulovic |
Synonymous address compaction for energy reduction in data TLB. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005, San Diego, California, USA, August 8-10, 2005, pp. 357-362, 2005, ACM, 1-59593-137-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
low-power TLB, spatial and temporal locality, multi-porting |
86 | Omesh Tickoo, Hari Kannan, Vineet Chadha, Ramesh Illikkal, Ravi R. Iyer 0001, Donald Newell |
qTLB: Looking Inside the Look-Aside Buffer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HiPC ![In: High Performance Computing - HiPC 2007, 14th International Conference, Goa, India, December 18-21, 2007, Proceedings, pp. 107-118, 2007, Springer, 978-3-540-77219-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
83 | Xiantao Zhang, Anthony X. F. Xu, Qi Li 0002, David K. Y. Yau, Sihan Qing, Huanguo Zhang |
A hash-TLB approach for MMU virtualization in xen/IA64. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 22nd IEEE International Symposium on Parallel and Distributed Processing, IPDPS 2008, Miami, Florida USA, April 14-18, 2008, pp. 1-8, 2008, IEEE. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
83 | Naohiko Shimizu, Ken Takatori |
A transparent Linux super page kernel for Alpha, Sparc64 and IA32: reducing TLB misses of applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGARCH Comput. Archit. News ![In: SIGARCH Comput. Archit. News 31(1), pp. 75-84, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Linux |
83 | Gokul B. Kandiraju, Anand Sivasubramaniam |
Going the Distance for TLB Prefetching: An Application-Driven Study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 29th International Symposium on Computer Architecture (ISCA 2002), 25-29 May 2002, Anchorage, AK, USA, pp. 195-206, 2002, IEEE Computer Society, 0-7695-1605-X. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Application-driven Study, Simulation, Prefetching, Memory Hierarchy, Translation Lookaside Buffer |
83 | Ashley Saulsbury, Fredrik Dahlgren, Per Stenström |
Recency-based TLB preloading. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 27th International Symposium on Computer Architecture (ISCA 2000), June 10-14, 2000, Vancouver, BC, Canada, pp. 117-127, 2000, IEEE Computer Society, 978-1-58113-232-8. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
82 | Yukikazu Nakamoto |
Operating System Supports to Enhance Fault Tolerance of Real-Time Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WORDS ![In: 8th IEEE International Workshop on Object-Oriented Real-Time Dependable Systems (WORDS 2003), 15-17 January 2003, Guadalajara, Mexico, pp. 10-17, 2003, IEEE Computer Society, 0-7695-1929-6. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Virtual Memory Management, Translation Look a side Buffer (TLB), Real-time Operating System, RISC Processor |
78 | Han-Xin Sun, Kun-Peng Yang, Yulai Zhao 0003, Dong Tong 0001, Xu Cheng 0001 |
CASA: A New IFU Architecture for Power-Efficient Instruction Cache and TLB Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Comput. Sci. Technol. ![In: J. Comput. Sci. Technol. 23(1), pp. 141-153, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
instruction TLB, instruction fetch unit, power-efficient design, computer architecture, dynamic voltage scaling, instruction cache |
74 | Cristan Szmajda, Gernot Heiser |
Variable Radix Page Table: A Page Table for Modern Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asia-Pacific Computer Systems Architecture Conference ![In: Advances in Computer Systems Architecture, 8th Asia-Pacific Conference, ACSAC 2003, Aizu-Wakamatsu, Japan, September 23-26, 2003, Proceedings, pp. 290-304, 2003, Springer, 3-540-20122-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
74 | David L. Black 0001, Richard F. Rashid, David B. Golub, Charles R. Hill, Robert V. Baron |
Translation Lookaside Buffer Consistency: A Software Approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASPLOS ![In: ASPLOS-III Proceedings - Third International Conference on Architectural Support for Programming Languages and Operating Systems, Boston, Massachusetts, USA, April 3-6, 1989., pp. 113-122, 1989, ACM Press, 0-89791-300-0. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
UNIX |
71 | Kelvin K. Lee, Samuel T. Chanson |
Transient analysis of cell loss control mechanisms in ATM networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCCN ![In: Proceedings of the 4th International Conference on Computer Communications and Networks (ICCCN '95), September 20-23, 1995, Las Vegas, Nevada, USA, pp. 240, 1995, IEEE Computer Society, 0-8186-7180-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
cell loss control mechanisms, partial buffer sharing, cell loss control mechanism, threshold-based loss balancing, violation probability, ATM networks, transient analysis, transient analysis, TLB, network utilization, queue length distributions, PBS |
70 | Karthik Ganesan 0006, Deepak Panwar, Lizy K. John |
Generation, Validation and Analysis of SPEC CPU2006 Simulation Points Based on Branch, Memory and TLB Characteristics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SPEC Benchmark Workshop ![In: Computer Performance Evaluation and Benchmarking, SPEC Benchmark Workshop 2009, Austin, TX, USA, January 25, 2009. Proceedings, pp. 121-137, 2009, Springer, 978-3-540-93798-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
70 | Adam Wiggins, Harvey Tuch, Volkmar Uhlig, Gernot Heiser |
Implementation of Fast Address-Space Switching and TLB Sharing on the StrongARM Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asia-Pacific Computer Systems Architecture Conference ![In: Advances in Computer Systems Architecture, 8th Asia-Pacific Conference, ACSAC 2003, Aizu-Wakamatsu, Japan, September 23-26, 2003, Proceedings, pp. 352-364, 2003, Springer, 3-540-20122-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
70 | David F. Bacon, Jyh-Herng Chow, Dz-Ching Ju, Kalyan Muthukumar, Vivek Sarkar |
A compiler framework for restructuring data declarations to enhance cache and TLB effectiveness. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASCON ![In: Proceedings of the 1994 Conference of the Centre for Advanced Studies on Collaborative Research, October 31 - November 3, 1994, Toronto, Ontario, Canada, pp. 3, 1994, IBM. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP BibTeX RDF |
|
70 | Neungsoo Park, Bo Hong, Viktor K. Prasanna |
Tiling, Block Data Layout, and Memory Hierarchy Performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 14(7), pp. 640-654, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Block data layout, TLB misses, memory hierarchy, tiling, cache misses |
66 | Ilya Chukhman, Peter Petrov |
Context-aware TLB preloading for interference reduction in embedded multi-tasked systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, Providence, Rhode Island, USA, May 16-18 2010, pp. 401-404, 2010, ACM, 978-1-4503-0012-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
TLB management, real-time multi-processing |
66 | Hsien-Hsin S. Lee, Chinnakrishnan S. Ballapuram |
Energy efficient D-TLB and data cache using semantic-aware multilateral partitioning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003, Seoul, Korea, August 25-27, 2003, pp. 306-311, 2003, ACM, 1-58113-682-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
low-power TLB, multi-ported memory structures, energy optimization, low-power cache |
63 | Andrei Tatar, Daniël Trujillo, Cristiano Giuffrida, Herbert Bos |
TLB;DR: Enhancing TLB-based Attacks with TLB Desynchronized Reverse Engineering. ![Search on Bibsonomy](Pics/bibsonomy.png) |
USENIX Security Symposium ![In: 31st USENIX Security Symposium, USENIX Security 2022, Boston, MA, USA, August 10-12, 2022, pp. 989-1007, 2022, USENIX Association, 978-1-939133-31-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP BibTeX RDF |
|
61 | Joshua Magee, Apan Qasem |
A case for compiler-driven superpage allocation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Southeast Regional Conference ![In: Proceedings of the 47th Annual Southeast Regional Conference, 2009, Clemson, South Carolina, USA, March 19-21, 2009, 2009, ACM, 978-1-60558-421-8. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
61 | Peter Petrov, Alex Orailoglu |
Virtual Page Tag Reduction for Low-power TLBs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 21st International Conference on Computer Design (ICCD 2003),VLSI in Computers and Processors, 13-15 October 2003, San Jose, CA, USA, Proceedings, pp. 371-374, 2003, IEEE Computer Society, 0-7695-2025-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
61 | Yefim Shuf, Mauricio J. Serrano, Manish Gupta 0002, Jaswinder Pal Singh |
Characterizing the memory behavior of Java workloads: a structured view and opportunities for optimizations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGMETRICS/Performance ![In: Proceedings of the Joint International Conference on Measurements and Modeling of Computer Systems, SIGMETRICS/Performance 2001, June 16-20, 2001, Cambridge, MA, USA, pp. 194-205, 2001, ACM, 1-58113-334-0. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
58 | Michael D. Adams 0001, David S. Wise |
Seven at one stroke: results from a cache-oblivious paradigm for scalable matrix algorithms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Memory System Performance and Correctness ![In: Proceedings of the 2006 workshop on Memory System Performance and Correctness, San Jose, California, USA, October 11, 2006, pp. 41-50, 2006, ACM, 1-59593-578-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Morton-hybrid, parallel processing, paging, quadtrees, Cholesky factorization, cache misses, TLB |
58 | Feihui Li, Mahmut T. Kandemir |
Increasing Data TLB Resilience to Transient Errors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), New Frontiers in VLSI Design, 11-12 May 2005, Tampa, FL, USA, pp. 297-298, 2005, IEEE Computer Society, 0-7695-2365-X. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
58 | Shivakumar Swaminathan, Sanjay B. Patel, James Dieffenderfer, Joel Silberman |
Reducing Power Consumption during TLB Lookups in a PowerPC Embedded Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 6th International Symposium on Quality of Electronic Design (ISQED 2005), 21-23 March 2005, San Jose, CA, USA, pp. 54-58, 2005, IEEE Computer Society, 0-7695-2301-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
58 | Mahmut T. Kandemir, Ismail Kadayif, Guilin Chen |
Compiler-directed code restructuring for reducing data TLB energy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2004, Stockholm, Sweden, September 8-10, 2004, pp. 98-103, 2004, ACM, 1-58113-937-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
code restructuring |
57 | Vincent Loechner, Benoît Meister, Philippe Clauss |
Data Sequence Locality: A Generalization of Temporal Locality. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Euro-Par ![In: Euro-Par 2001: Parallel Processing, 7th International Euro-Par Conference Manchester, UK August 28-31, 2001, Proceedings, pp. 262-272, 2001, Springer, 3-540-42495-4. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
cache and TLB performance, parameterized polyhedra, Ehrhart polynomials, Memory hierarchy, temporal locality, loop nests |
55 | André Seznec |
Concurrent Support of Multiple Page Sizes on a Skewed Associative TLB. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 53(7), pp. 924-927, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
multiple page size, skewed associativity, TLB |
55 | Nathan Kalyanasundharam, Nital Patwa |
Simultaneous Switching Noise Considerations in the Design of a High Speed, Multiported TLB of a Server-Class Microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings of the IEEE International Conference On Computer Design, VLSI in Computers and Processors, ICCD '99, Austin, Texas, USA, October 10-13, 1999, pp. 118-123, 1999, IEEE Computer Society, 0-7695-0406-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
multiported, supply inductance, TLB, simultaneous switching noise, decoupling capacitance |
49 | Vineet Chadha, Ramesh Illikkal, Ravi R. Iyer 0001, Jaideep Moses, Donald Newell, Renato J. O. Figueiredo |
I/O processing in a virtualized platform: a simulation-driven approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VEE ![In: Proceedings of the 3rd International Conference on Virtual Execution Environments, VEE 2007, San Diego, California, USA, June 13-15, 2007, pp. 116-125, 2007, ACM, 978-1-59593-630-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
simulation, virtual machines, virtualization, performance model, xen |
49 | Victor Delaluz, Mahmut T. Kandemir, Anand Sivasubramaniam, Mary Jane Irwin, Narayanan Vijaykrishnan |
Reducing dTLB Energy Through Dynamic Resizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 21st International Conference on Computer Design (ICCD 2003),VLSI in Computers and Processors, 13-15 October 2003, San Jose, CA, USA, Proceedings, pp. 358-363, 2003, IEEE Computer Society, 0-7695-2025-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
49 | Neungsoo Park, Bo Hong, Viktor K. Prasanna |
Analysis of Memory Hierarchy Performance of Block Data Layout. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPP ![In: 31st International Conference on Parallel Processing (ICPP 2002), 20-23 August 2002, Vancouver, BC, Canada, pp. 35-46, 2002, IEEE Computer Society, 0-7695-1677-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
49 | Bryan S. Rosenburg |
Low-Synchronization Translation Lookaside Buffer Consistency in Large-Scale Shared-Memory Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SOSP ![In: Proceedings of the Twelfth ACM Symposium on Operating System Principles, SOSP 1989, The Wigwam, Litchfield Park, Arizona, USA, December 3-6, 1989, pp. 137-146, 1989, ACM, 0-89791-338-8. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
46 | Mel Gorman, Patrick Healy |
Supporting superpage allocation without additional hardware support. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMM ![In: Proceedings of the 7th International Symposium on Memory Management, ISMM 2008, Tucson, AZ, USA, June 7-8, 2008, pp. 41-50, 2008, ACM, 978-1-60558-134-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
superpage, fragmentation, replacement policy, tlb |
46 | Martin Hirzel |
Data layouts for object-oriented programs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGMETRICS ![In: Proceedings of the 2007 ACM SIGMETRICS International Conference on Measurement and Modeling of Computer Systems, SIGMETRICS 2007, San Diego, California, USA, June 12-16, 2007, pp. 265-276, 2007, ACM, 978-1-59593-639-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
GC, cache, data placement, spatial locality, data layout, TLB, hardware performance counters, memory subsystem |
46 | Collin McCurdy, Alan L. Cox, Jeffrey S. Vetter |
Investigating the TLB Behavior of High-end Scientific Applications on Commodity Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPASS ![In: IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS 2008, April 20-22, 2008, Austin, Texas, USA, Proceedings, pp. 95-104, 2008, IEEE Computer Society, 978-1-4244-2232-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
46 | Ismail Kadayif, Partho Nath, Mahmut T. Kandemir, Anand Sivasubramaniam |
Reducing Data TLB Power via Compiler-Directed Address Generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(2), pp. 312-324, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
46 | Ismail Kadayif, Anand Sivasubramaniam, Mahmut T. Kandemir, Gokul B. Kandiraju, Guangyu Chen |
Optimizing instruction TLB energy using software and hardware techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 10(2), pp. 229-257, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
instruction locality, translation look-aside buffer, Power consumption, compiler optimization, cache design |
46 | Jack J. Dongarra, Shirley Moore, Philip Mucci, Keith Seymour, Haihang You |
Accurate Cache and TLB Characterization Using Hardware Counters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
International Conference on Computational Science ![In: Computational Science - ICCS 2004, 4th International Conference, Kraków, Poland, June 6-9, 2004, Proceedings, Part III, pp. 432-439, 2004, Springer, 3-540-22116-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
46 | Philip Machanick, Zunaid Patel |
L1 Cache and TLB Enhancements to the RAMpage Memory Hierarchy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asia-Pacific Computer Systems Architecture Conference ![In: Advances in Computer Systems Architecture, 8th Asia-Pacific Conference, ACSAC 2003, Aizu-Wakamatsu, Japan, September 23-26, 2003, Proceedings, pp. 305-319, 2003, Springer, 3-540-20122-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
46 | Ismail Kadayif, Anand Sivasubramaniam, Mahmut T. Kandemir, Gokul B. Kandiraju, Guangyu Chen |
Generating physical addresses directly for saving instruction TLB energy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 35th Annual International Symposium on Microarchitecture, Istanbul, Turkey, November 18-22, 2002, pp. 185-196, 2002, ACM/IEEE Computer Society, 0-7695-1859-1. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
46 | Magnus Ekman, Per Stenström, Fredrik Dahlgren |
TLB and snoop energy-reduction using virtual caches in low-power chip-multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002, Monterey, California, USA, August 12-14, 2002, pp. 243-246, 2002, ACM, 1-58113-475-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
virtual caches, low-power, CMP, snoop |
45 | Richard Uhlig, David Nagle, Timothy J. Stanley, Trevor N. Mudge, Stuart Sechrest, Richard B. Brown |
Design Tradeoffs for Software-Managed TLBs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Comput. Syst. ![In: ACM Trans. Comput. Syst. 12(3), pp. 175-205, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
translation lookaside buffer (TLB), trap-driven simulation, hardware monitoring |
42 | Farid Yuli Martin Adiyatma, Dwi Joko Suroso, Panarat Cherntanomwong |
TLB & WC-TLB-MM: The Improved Min-Max Algorithms for Multi Targets Indoor Localization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 11, pp. 129733-129748, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
42 | Bang Di, Daokun Hu, Zhen Xie, Jianhua Sun 0002, Hao Chen 0002, Jinkui Ren, Dong Li 0001 |
TLB-pilot: Mitigating TLB Contention Attack on GPUs with Microarchitecture-Aware Scheduling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Archit. Code Optim. ![In: ACM Trans. Archit. Code Optim. 19(1), pp. 9:1-9:23, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
42 | Andrés Rainiero Hernández Coronado, Wei-Ming Lin |
Effective TLB thrashing: unveiling the true short reach of modern TLB designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAC ![In: SAC '22: The 37th ACM/SIGAPP Symposium on Applied Computing, Virtual Event, April 25 - 29, 2022, pp. 1704-1712, 2022, ACM, 978-1-4503-8713-2. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
42 | Jesung Kim, Jongmin Lee 0002, Soontae Kim |
TLB Index-Based Tagging for Reducing Data Cache and TLB Energy Consumption. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 66(7), pp. 1200-1211, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
42 | Amro Awad, Arkaprava Basu, Sergey Blagodurov, Yan Solihin, Gabriel H. Loh |
Avoiding TLB Shootdowns Through Self-Invalidating TLB Entries. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PACT ![In: 26th International Conference on Parallel Architectures and Compilation Techniques, PACT 2017, Portland, OR, USA, September 9-13, 2017, pp. 273-287, 2017, IEEE Computer Society, 978-1-5090-6764-0. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
42 | Jee Ho Ryoo, Nagendra Gulur, Shuang Song 0007, Lizy K. John |
Rethinking TLB Designs in Virtualized Environments: A Very Large Part-of-Memory TLB. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: Proceedings of the 44th Annual International Symposium on Computer Architecture, ISCA 2017, Toronto, ON, Canada, June 24-28, 2017, pp. 469-480, 2017, ACM, 978-1-4503-4892-8. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
42 | Chang Hyun Park 0001, Taekyung Heo, Jungi Jeong, Jaehyuk Huh 0001 |
Hybrid TLB Coalescing: Improving TLB Translation Coverage under Diverse Fragmented Memory Allocations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: Proceedings of the 44th Annual International Symposium on Computer Architecture, ISCA 2017, Toronto, ON, Canada, June 24-28, 2017, pp. 444-456, 2017, ACM, 978-1-4503-4892-8. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
42 | Carlos Villavieja, Vasileios Karakostas, Lluís Vilanova, Yoav Etsion, Alex Ramírez, Avi Mendelson, Nacho Navarro, Adrián Cristal, Osman S. Unsal |
DiDi: Mitigating the Performance Impact of TLB Shootdowns Using a Shared TLB Directory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PACT ![In: 2011 International Conference on Parallel Architectures and Compilation Techniques, PACT 2011, Galveston, TX, USA, October 10-14, 2011, pp. 340-349, 2011, IEEE Computer Society, 978-1-4577-1794-9. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
42 | Byeong Hag Seong, Donggook Kim, Yangwoo Roh, Kyu Ho Park, Daeyeon Park |
TLB Update-Hint: A Scalable TLB Consistency Algorithm for Cache-Coherent Non-uniform Memory Access Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Inf. Syst. ![In: IEICE Trans. Inf. Syst. 87-D(7), pp. 1682-1692, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP BibTeX RDF |
|
41 | Girish Venkatasubramanian, Renato J. O. Figueiredo, Ramesh Illikkal |
On the Performance of Tagged Translation Lookaside Buffers: A Simulation-Driven Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MASCOTS ![In: MASCOTS 2011, 19th Annual IEEE/ACM International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems, Singapore, 25-27 July, 2011, pp. 139-149, 2011, IEEE Computer Society, 978-1-4577-0468-0. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
hardware-managed TLB, tagged TLB, virtualization, Translation lookaside buffer, full-system simulation |
37 | Xiaogang Qiu, Michel Dubois 0001 |
The Synonym Lookaside Buffer: A Solution to the Synonym Problem in Virtual Caches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 57(12), pp. 1585-1599, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
37 | Aamer Jaleel, Bruce L. Jacob |
In-Line Interrupt Handling and Lock-Up Free Translation Lookaside Buffers (TLBs). ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 55(5), pp. 559-574, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Reorder-buffer (ROB), exception handlers, in-line interrupt, lock-up free, translation lookaside buffers (TLBs), performance modeling, precise interrupts |
37 | David Siegwart, Martin Hirzel |
Improving locality with parallel hierarchical copying GC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMM ![In: Proceedings of the 5th International Symposium on Memory Management, ISMM 2006, Ottawa, Ontario, Canada, June 10-11, 2006, pp. 52-63, 2006, ACM, 1-59593-221-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
parallel, generational, cache locality |
37 | Wayne Pfeiffer |
Memory Performance Model for Loops and Kernels on Power3 Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), CD-ROM / Abstracts Proceedings, 26-30 April 2004, Santa Fe, New Mexico, USA, 2004, IEEE Computer Society, 0-7695-2132-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
37 | Xiaogang Qiu, Michel Dubois 0001 |
Towards Virtually-Addressed Memory Hierarchies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: Proceedings of the Seventh International Symposium on High-Performance Computer Architecture (HPCA'01), Nuevo Leone, Mexico, January 20-24, 2001, pp. 51-62, 2001, IEEE Computer Society, 0-7695-1019-1. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
37 | Zhen Fang 0002, Lixin Zhang 0002, John B. Carter, Wilson C. Hsieh, Sally A. McKee |
Reevaluating Online Superpage Promotion with Hardware Support. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: Proceedings of the Seventh International Symposium on High-Performance Computer Architecture (HPCA'01), Nuevo Leone, Mexico, January 20-24, 2001, pp. 63-72, 2001, IEEE Computer Society, 0-7695-1019-1. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
37 | Xiaogang Qiu, Michel Dubois 0001 |
Options for Dynamic Address Translation in COMAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: Proceedings of the 25th Annual International Symposium on Computer Architecture, ISCA 1998, Barcelona, Spain, June 27 - July 1, 1998, pp. 214-225, 1998, IEEE Computer Society, 0-8186-8491-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
34 | Rui Min, Wen-Ben Jone, Yiming Hu |
Location cache: a low-power L2 cache system. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004, Newport Beach, California, USA, August 9-11, 2004, pp. 120-125, 2004, ACM. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
L1/L2 caches, data location, power, TLB, set-associative caches |
34 | Rui Min, Yiming Hu |
Improving Performance of Large Physically Indexed Caches by Decoupling Memory Addresses from Cache Addresses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 50(11), pp. 1191-1201, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
Novel memory architectures, cache, memory systems, TLB, performance enhancement |
34 | Richard Uhlig, David Nagle, Trevor N. Mudge, Stuart Sechrest |
Trap-driven Simulation with Tapeworm II. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASPLOS ![In: ASPLOS-VI Proceedings - Sixth International Conference on Architectural Support for Programming Languages and Operating Systems, San Jose, California, USA, October 4-7, 1994., pp. 132-144, 1994, ACM Press, 0-89791-660-3. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
trap-driven simulation, cache, trace-driven simulation, memory system, TLB |
33 | |
Translation Lookaside Buffer (TLB). ![Search on Bibsonomy](Pics/bibsonomy.png) |
Encyclopedia of Database Systems ![In: Encyclopedia of Database Systems, pp. 3172, 2009, Springer US, 978-0-387-35544-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
33 | Stefan Groesbrink, Timo Kerstan |
Modular paging with dynamic TLB partitioning for embedded real-time systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIES ![In: IEEE Third International Symposium on Industrial Embedded Systems, SIES 2008, Montpellier / La Grande Motte, France, June 11-13, 2008, pp. 261-264, 2008, IEEE, 978-1-4244-1994-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
33 | Ismail Kadayif, Mahmut T. Kandemir, I. Demirkiran |
Compiler-Guided Code Restructuring for Improving Instruction TLB Energy Behavior. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Euro-Par ![In: Euro-Par 2004 Parallel Processing, 10th International Euro-Par Conference, Pisa, Italy, August 31-September 3, 2004, Proceedings, pp. 304-309, 2004, Springer, 3-540-22924-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
33 | Naila Rahman |
Algorithms for Hardware Caches and TLB. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Algorithms for Memory Hierarchies ![In: Algorithms for Memory Hierarchies, Advanced Lectures [Dagstuhl Research Seminar, March 10-14, 2002], pp. 171-192, 2002, Springer, 3-540-00883-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
33 | Aamer Jaleel, Bruce L. Jacob |
Improving the Precise Interrupt Mechanism of Software-Managed TLB Miss Handlers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HiPC ![In: High Performance Computing - HiPC 2001, 8th International Conference, Hyderabad, India, December, 17-20, 2001, Proceedings, pp. 282-293, 2001, Springer, 3-540-43009-1. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
33 | Bruce L. Jacob, Trevor N. Mudge |
A Look at Several Memory Management Units, TLB-Refill Mechanisms, and Page Table Organizations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASPLOS ![In: ASPLOS-VIII Proceedings of the 8th International Conference on Architectural Support for Programming Languages and Operating Systems, San Jose, California, USA, October 3-7, 1998., pp. 295-306, 1998, ACM Press, 1-58113-107-0. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
25 | Ryan W. Moore, José Baiocchi, Bruce R. Childers, Jack W. Davidson, Jason Hiser |
Addressing the challenges of DBT for the ARM architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES ![In: Proceedings of the 2009 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems, LCTES 2009, Dublin, Ireland, June 19-20, 2009, pp. 147-156, 2009, ACM, 978-1-60558-356-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
virtualization, dynamic binary translation, arm |
25 | Moon-Sang Lee, Joonwon Lee, Seungryoul Maeng |
Context-aware address translation for high performance SMP cluster system. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CLUSTER ![In: Proceedings of the 2008 IEEE International Conference on Cluster Computing, 29 September - 1 October 2008, Tsukuba, Japan, pp. 292-297, 2008, IEEE Computer Society, 978-1-4244-2640-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
25 | Jaume Abella 0001, Antonio González 0001 |
SAMIE-LSQ: set-associative multiple-instruction entry load/store queue. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), Proceedings, 25-29 April 2006, Rhodes Island, Greece, 2006, IEEE. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
25 | Yen-Jen Chang |
An Alternative Real-Time Filter Scheme to Block Buffering. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 19th International Conference on VLSI Design (VLSI Design 2006), 3-7 January 2006, Hyderabad, India, pp. 762-765, 2006, IEEE Computer Society, 0-7695-2502-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
25 | Xiangrong Zhou, Peter Petrov |
Arithmetic-based address translation for energy-efficient virtual memory support in low-power, real-time embedded systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 18th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2005, Florianolpolis, Brazil, September 4-7, 2005, pp. 86-91, 2005, ACM. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
25 | Ismail Kadayif, Partho Nath, Mahmut T. Kandemir, Anand Sivasubramaniam |
Compiler-directed physical address generation for reducing dTLB power. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPASS ![In: 2004 IEEE International Symposium on Performance Analysis of Systems and Software, March 10-12, 2004, Austin, Texas, USA, Proceedings, pp. 161-168, 2004, IEEE Computer Society, 0-7803-8385-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
25 | Danko Butorac |
Talking Linux for the Blind - A CD Distribution with Speech. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCHP ![In: Computers Helping People with Special Needs, 9th International Conference, ICCHP 2004, Paris, France, July 7-9, 2004, Proceedings, pp. 552-559, 2004, Springer, 3-540-22334-7. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
25 | Rajeev Balasubramonian, David H. Albonesi, Alper Buyuktosunoglu, Sandhya Dwarkadas |
A Dynamically Tunable Memory Hierarchy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 52(10), pp. 1243-1258, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
High performance microprocessors, energy and performance of on-chip caches, memory hierarchy, reconfigurable architectures |
25 | Adam Wiggins, Simon Winwood, Harvey Tuch, Gernot Heiser |
Legba: Fast Hardware Support for Fine-Grained Protection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asia-Pacific Computer Systems Architecture Conference ![In: Advances in Computer Systems Architecture, 8th Asia-Pacific Conference, ACSAC 2003, Aizu-Wakamatsu, Japan, September 23-26, 2003, Proceedings, pp. 320-336, 2003, Springer, 3-540-20122-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
25 | Ruoming Jin, Gagan Agrawal |
Performance prediction for random write reductions: a case study in modeling shared memory programs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGMETRICS ![In: Proceedings of the International Conference on Measurements and Modeling of Computer Systems, SIGMETRICS 2002, June 15-19, 2002, Marina Del Rey, California, USA, pp. 117-128, 2002, ACM, 1-58113-531-9. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
25 | Yen-Jen Chang, Feipei Lai, Shanq-Jang Ruan |
Cache Design for Eliminating the Address Translation Bottleneck and Reducing the Tag Area Cost. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 20th International Conference on Computer Design (ICCD 2002), VLSI in Computers and Processors, 16-18 September 2002, Freiburg, Germany, Proceedings, pp. 334-339, 2002, IEEE Computer Society, 0-7695-1700-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
25 | Michael Penner, Viktor K. Prasanna |
Cache-Friendly Implementations of Transitive Closure. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE PACT ![In: 2001 International Conference on Parallel Architectures and Compilation Techniques (PACT 2001), 8-12 September 2001, Barcelona, Spain, pp. 185-196, 2001, IEEE Computer Society, 0-7695-1363-8. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
25 | Naila Rahman, Richard Cole 0001, Rajeev Raman |
Optimised Predecessor Data Structures for Internal Memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WAE ![In: Algorithm Engineering, 5th International Workshop, WAE 2001 Aarhus, Denmark, August 28-31, 2001, Proceedings, pp. 67-78, 2001, Springer, 3-540-42500-4. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|