Search results for "WDDL"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
194	Sylvain Guilley, Laurent Sauvage, Philippe Hoogvorst, Renaud Pacalet, Guido Marco Bertoni, Sumanta Chaudhuri	Security Evaluation of WDDL and SecLib Countermeasures against Power Attacks.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF
129	Yuan-man Tong, Zhiying Wang 0003, Kui Dai, Hongyi Lu	Designing Power Analysis Resistant and High Performance Block Cipher Coprocessor Using WDDL and Wave-Pipelining.	Inscrypt	2006	DBLP DOI BibTeX RDF	WDDL, power analysis resistant, block cipher, design flow, Wave-pipelining
83	Kris Tiri, David D. Hwang, Alireza Hodjat, Bo-Cheng Lai, Shenglin Yang, Patrick Schaumont, Ingrid Verbauwhede	Prototype IC with WDDL and Differential Routing - DPA Resistance Assessment.	CHES	2005	DBLP DOI BibTeX RDF	dual rail with precharge, wave dynamic differential logic (WDDL), differential routing, parasitic capacitance matching, side-channel attack (SCA), differential power analysis (DPA), countermeasure
69	Toru Akishita, Masanobu Katagi, Yoshikazu Miyato, Asami Mizuno, Kyoji Shibutani	A Practical DPA Countermeasure with BDD Architecture.	CARDIS	2008	DBLP DOI BibTeX RDF	dual-rail pre-charge logic, DPA, Binary Decision Diagram, countermeasure
56	Robert P. McEvoy, Colin C. Murphy, William P. Marnane, Michael Tunstall	Isolated WDDL: A Hiding Countermeasure for Differential Power Analysis on FPGAs.	ACM Trans. Reconfigurable Technol. Syst.	2009	DBLP DOI BibTeX RDF	secure logic, FPGA, Side-channel attacks, DPA, Whirlpool
46	Sylvain Guilley, Laurent Sauvage, Jean-Luc Danger, Philippe Hoogvorst	Area optimization of cryptographic co-processors implemented in dual-rail with precharge positive logic.	FPL	2008	DBLP DOI BibTeX RDF
46	Daisuke Suzuki, Minoru Saeki	Security Evaluation of DPA Countermeasures Using Dual-Rail Pre-charge Logic Style.	CHES	2006	DBLP DOI BibTeX RDF
33	Emna Amouri, Shivam Bhasin, Yves Mathieu, Tarik Graba, Jean-Luc Danger, Habib Mehrez	Balancing WDDL dual-rail logic in a tree-based FPGA to enhance physical security.	FPL	2014	DBLP DOI BibTeX RDF
33	Emna Amouri, Habib Mehrez, Zied Marrakchi	Impact of Dual Placement and Routing on WDDL Netlist Security in FPGA.	Int. J. Reconfigurable Comput.	2013	DBLP DOI BibTeX RDF
33	Emna Amouri, Zied Marrakchi, Habib Mehrez	Differential pair routing to balance dual signals of WDDL designs in cluster-based Mesh FPGA.	ReCoSoC	2011	DBLP DOI BibTeX RDF
33	Yang Li 0001, Kazuo Ohta, Kazuo Sakiyama	Revisit fault sensitivity analysis on WDDL-AES.	HOST	2011	DBLP DOI BibTeX RDF
33	Emna Amouri, Zied Marrakchi, Habib Mehrez	Controlled placement and routing techniques to improve timing balance of WDDL designs in Mesh-based FPGA.	APCCAS	2010	DBLP DOI BibTeX RDF
33	Laurent Sauvage, Sylvain Guilley, Jean-Luc Danger, Yves Mathieu, Maxime Nassar	Successful attack on an FPGA-based WDDL DES cryptoprocessor without place and route constraints.	DATE	2009	DBLP DOI BibTeX RDF
33	Emna Amouri, Hayder Mrabet, Zied Marrakchi, Habib Mehrez	Placement and routing techniques to improve delay balance of WDDL netlist in MFPGA.	ICECS	2009	DBLP DOI BibTeX RDF
33	Nidhal Selmane, Shivam Bhasin, Sylvain Guilley, Tarik Graba, Jean-Luc Danger	WDDL is Protected against Setup Time Violation Attacks.	FDTC	2009	DBLP DOI BibTeX RDF
27	Emna Amouri, Hayder Mrabet, Zied Marrakchi, Habib Mehrez	Improving the Security of Dual Rail Logic in FPGA Using Controlled Placement and Routing.	ReConFig	2009	DBLP DOI BibTeX RDF	MFPGA, Timing balance, WDDL, Routing, Placement, Differential Power Analysis
27	Laurent Sauvage, Maxime Nassar, Sylvain Guilley, Florent Flament, Jean-Luc Danger, Yves Mathieu	DPL on Stratix II FPGA: What to Expect?.	ReConFig	2009	DBLP DOI BibTeX RDF	Dual-rail with Precharge Logic (DPL), Wave Dynamic Differential Logic (WDDL), Field Programmable Gates Array (FPGA), Differential Power Analysis (DPA), Commercial Off-The-Shelf (COTS), Side-Channel Analysis (SCA)
27	Jianping Quan, Guoqiang Bai 0001	A New Method to Reduce the Side-Channel Leakage Caused by Unbalanced Capacitances of Differential Interconnections in Dual-Rail Logic Styles.	ITNG	2009	DBLP DOI BibTeX RDF	WDDL, TDPL, NSDDL, unbalanced interconnections, early propagation effect, routing
27	Sylvain Guilley, Laurent Sauvage, Jean-Luc Danger, Tarik Graba, Yves Mathieu	Evaluation of Power-Constant Dual-Rail Logic as a Protection of Cryptographic Applications in FPGAs.	SSIRI	2008	DBLP DOI BibTeX RDF	Power Constant Logic, WDDL, Positive Dual-Rail with Precharge Logic, FPGA, Side-Channel Attacks
23	Zhimin Chen, Yujie Zhou	Dual-Rail Random Switching Logic: A Countermeasure to Reduce Side Channel Leakage.	CHES	2006	DBLP DOI BibTeX RDF	Gate Level Masking, DRSL, Dual-Rail, Pre-charge, Side Channel Attacks, DPA
23	Kris Tiri, David D. Hwang, Alireza Hodjat, Bo-Cheng Lai, Shenglin Yang, Patrick Schaumont, Ingrid Verbauwhede	A side-channel leakage free coprocessor IC in 0.18µm CMOS for embedded AES-based cryptographic and biometric processing.	DAC	2005	DBLP DOI BibTeX RDF	security IC, encryption, smart card, side-channel attack, differential power analysis, countermeasure