Search results for "Wave-pipelining"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
97	Chuan-Hua Chang, Edward S. Davidson, Karem A. Sakallah	Maximum rate single-phase clocking of a closed pipeline including wave pipelining, stoppability, and startability.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
95	Rajesh S. Parthasarathy, Ramalingam Sridhar	Double Pass Transistor Logic for High Performance Wave Pipeline Circuits.	VLSI Design	1998	DBLP DOI BibTeX RDF
95	Yuan-man Tong, Zhiying Wang 0003, Kui Dai, Hongyi Lu	Designing Power Analysis Resistant and High Performance Block Cipher Coprocessor Using WDDL and Wave-Pipelining.	Inscrypt	2006	DBLP DOI BibTeX RDF	WDDL, power analysis resistant, block cipher, design flow, Wave-pipelining
95	Jiang Xu 0001, Wayne H. Wolf	Wave pipelining for application-specific networks-on-chips.	CASES	2002	DBLP DOI BibTeX RDF	system-on-chip (SoC), interconnection, networks-on-chip (NoC), wave pipelining, coupling capacitance
83	Wayne P. Burleson, Maciej J. Ciesielski, Fabian Klass, W. Liu	Wave-pipelining: a tutorial and research survey.	IEEE Trans. Very Large Scale Integr. Syst.	1998	DBLP DOI BibTeX RDF
83	Debabrata Ghosh, S. K. Nandy 0001	Design and realization of high-performance wave-pipelined 8×8 b multiplier in CMOS technology.	IEEE Trans. Very Large Scale Integr. Syst.	1995	DBLP DOI BibTeX RDF
83	G. Enrique Fernandez, R. Sridhar	Dual rail static CMOS architecture for wave pipelining.	VLSI Design	1996	DBLP DOI BibTeX RDF	dual rail static CMOS architecture, gate capacitance, storage elements, DRSCMOS, multi-functional basic building blocks, combinational logic block, delays, timing, throughput, combinational circuits, power consumption, pipeline processing, CMOS logic circuits, digital systems, capacitance, wave pipelining, delay variations
70	Fabian Klass, Michael J. Flynn, Ad J. van de Goor	Fast multiplication in VLSI using wave pipelining techniques.	J. VLSI Signal Process.	1994	DBLP DOI BibTeX RDF
69	Derek C. Wong, Giovanni De Micheli, Michael J. Flynn	Designing high-performance digital circuits using wave pipelining: algorithms and practical experiences.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
63	Eduardo I. Boemo, Sergio López-Buedo, Juan M. Meneses	Some experiments about wave pipelining on FPGA's.	IEEE Trans. Very Large Scale Integr. Syst.	1998	DBLP DOI BibTeX RDF
61	V. Vireen, N. Venugopalachary, G. Seetharaman, B. Venkataramani	Built in Self Test Based Design of Wave-Pipelined Circuits in ASICs.	VLSI Design	2009	DBLP DOI BibTeX RDF
61	G. Seetharaman, B. Venkataramani	Automation Schemes for FPGA Implementation of Wave-Pipelined Circuits.	ACM Trans. Reconfigurable Technol. Syst.	2009	DBLP DOI BibTeX RDF	FPGA, pipelining, SOC, CORDIC, wave-pipelining, DAA
60	Masa-Aki Fukase, Ryusuke Egawa, Tomoaki Sato, Tadao Nakamura	Scaling Up Of Wave Pipelines.	VLSI Design	2001	DBLP DOI BibTeX RDF
55	Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk	High-throughput interconnect wave-pipelining for global communication in FPGAs.	FPGA	2008	DBLP DOI BibTeX RDF
54	Paul Teehan, Guy G. Lemieux, Mark R. Greenstreet	Towards reliable 5Gbps wave-pipelined and 3Gbps surfing interconnect in 65nm FPGAs.	FPGA	2009	DBLP DOI BibTeX RDF	on-chip serdes, fpga, reliable, network-on-chip, interconnect, programmable, wave pipelining, bit-serial, surfing
47	Mitrajit Chatterjee, Savita Banerjee, Dhiraj K. Pradhan	Buffer Assignment Algorithms on Data Driven ASICs.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	throughput, Application specific integrated circuits, buffers, data flow graph, wave-pipelining, data driven architecture
46	Oliver Hauck, A. Katoch, Sorin A. Huss	VLSI System Design Using Asynchronous Wave Pipelines: A 0.35?m CMOS 1.5 GHz Elliptic Curve Public Key Cryptosystem Chip.	ASYNC	2000	DBLP DOI BibTeX RDF
46	Debabrata Ghosh, Soumitra Kumar Nandy	Wave pipelined architecture folding: a method to achieve low power and low area.	VLSI Design	1995	DBLP DOI BibTeX RDF	wave pipelined architecture folding, clock-free wave pipelining scheme, chip area reduction, VLSI, low power design, logic design, pipeline processing, integrated circuit design, digital integrated circuits
43	Jos Sulistyo, Dong Sam Ha	5 GHz pipelined multiplier and MAC in 0.18µm complementary static CMOS.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
41	José G. Delgado-Frias, Jabulani Nyathi, Laxmi N. Bhuyan	A wave-pipelined router architecture using ternary associative memory.	ACM Great Lakes Symposium on VLSI	2000	DBLP DOI BibTeX RDF
40	Hong-Yean Hsieh, Wentai Liu, Ralph K. Cavin III, C. Thomas Gray	Concurrent timing optimization of latch-based digital systems.	ICCD	1995	DBLP DOI BibTeX RDF	concurrent timing optimization, latch-based digital systems, digital system timing, intentional clock skew, latch-based designed systems, multi-phase clocking, resynchronization, latches insertion, optimisation, timing, logic design, flip-flops, retiming, mixed integer linear program, race conditions, integrated framework, wave pipelining, hazards and race conditions, clock period
35	Donald A. Joy, Maciej J. Ciesielski	Clock period minimization with wave pipelining.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
34	C. Thomas Gray, Wentai Liu, Ralph K. Cavin III	Timing constraints for wave-pipelined systems.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
33	José Duato, Pedro López 0001, Sudhakar Yalamanchili	Deadlock- and Livelock-Free Routing Protocols for Wave Switching.	IPPS	1997	DBLP DOI BibTeX RDF
29	Chung-Sheng Li, Kumar N. Sivarajan, David G. Messerschmitt	Statistical analysis of timing rules for high-speed synchronous VLSI systems.	IEEE Trans. Very Large Scale Integr. Syst.	1999	DBLP DOI BibTeX RDF
28	Terrence S. T. Mak, Crescenzo D'Alessandro, N. Pete Sedcole, Peter Y. K. Cheung, Alexandre Yakovlev, Wayne Luk	Implementation of Wave-Pipelined Interconnects in FPGAs.	NOCS	2008	DBLP DOI BibTeX RDF
28	Woo Jin Kim, Yong-Bin Kim	Automating Wave-Pipelined Circuit Design.	IEEE Des. Test Comput.	2003	DBLP DOI BibTeX RDF
28	Karem A. Sakallah, Trevor N. Mudge, Timothy M. Burks, Edward S. Davidson	Synchronization of pipelines.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
28	Abdulqader Nael Mahmoud, Frederic Vanderveken, Christoph Adelmann, Florin Ciubotaru, Said Hamdioui, Sorin Cotofana	Achieving Wave Pipelining in Spin Wave Technology.	ISQED	2021	DBLP DOI BibTeX RDF
26	Suryanarayana Tatapudi, José G. Delgado-Frias	A High Performance Hybrid Wave-Pipelined Multiplier.	ISVLSI	2005	DBLP DOI BibTeX RDF
26	Ram K. Krishnamurthy, Ramalingam Sridhar	A CMOS wave-pipelined image processor for real-time morphology .	ICCD	1995	DBLP DOI BibTeX RDF	CMOS wave-pipelined image processor, real-time morphology, high-speed morphological image processor, wave-pipelined transmission gate logic, two-stage morphological skeleton transform filter, regular pipelined architectures, real-time systems, computational complexity, image processing, latency, pipeline processing, CMOS integrated circuits, hardware complexity
26	Ajay Joshi, Jeffrey A. Davis	Wave-pipelined 2-slot time division multiplexed (WP/2-TDM) routing.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	interconnect sharing, time division, wave-pipelining
26	Michael J. Flynn, Kevin J. Nowka, Gary Bewick, Eric M. Schwarz, Nhon T. Quach	The SNAP Project: Towards Sub-Nanosecond Arithmetic.	IEEE Symposium on Computer Arithmetic	1995	DBLP DOI BibTeX RDF	floating-point multiplication, computer arithmetic, floating-point arithmetic, wave pipelining, floating-point addition
21	Odysseas Zografos, A. De Meester, Eleonora Testa, Mathias Soeken, Pierre-Emmanuel Gaillardon, Giovanni De Micheli, Luca Gaetano Amarù, Praveen Raghavan, Francky Catthoor, Rudy Lauwereins	Wave pipelining for majority-based beyond-CMOS technologies.	DATE	2017	DBLP DOI BibTeX RDF
21	M. Madheswaran, T. Menakadevi	An Improved Direct Digital Synthesizer Using Hybrid Wave Pipelining and CORDIC algorithm for Software Defined Radio.	Circuits Syst. Signal Process.	2013	DBLP DOI BibTeX RDF
21	Venkatasubramanian Adhinarayanan, Rengaprabhu Paramasivam, Seetharaman Gopalakrishnan	ASIC Implementation of One Level 2D-DWT Using Wave-Pipelining.	Asia International Conference on Modelling and Simulation	2013	DBLP DOI BibTeX RDF
21	Refik Sever, Murat Askar	8×8-Bit multiplier designed with a new wave-pipelining scheme.	ISCAS	2010	DBLP DOI BibTeX RDF
21	Miguel Eduardo Litvin, Samiha Mourad	Wave Pipelining Using Self Reset Logic.	VLSI Design	2008	DBLP DOI BibTeX RDF
21	Miguel Eduardo Litvin, Samiha Mourad, William Terry, Janice Terry	Wave Pipelining using Self Reset Logic.	ICECS	2006	DBLP DOI BibTeX RDF
21	Suryanarayana Tatapudi, José G. Delgado-Frias	A Pipelined Multiplier Using A Hybrid Wave-Pipelining Scheme.	CDES	2005	DBLP BibTeX RDF
21	Stephan Hermanns, Sorin A. Huss	Synchronisierungsprobleme von Schaltwerken in Wave Pipelining Architektur und ihre Auswirkungen auf die Wahl der Schaltungstechnik.	GI Jahrestagung (1)	2005	DBLP BibTeX RDF
21	Brian D. Winters, Mark R. Greenstreet	Surfing: a robust form of wave pipelining using self-timed circuit techniques.	Microprocess. Microsystems	2003	DBLP DOI BibTeX RDF
21	Arindam Mukherjee 0001, Malgorzata Marek-Sadowska, Stephen I. Long	Wave pipelining YADDs-a feasibility study.	CICC	1999	DBLP DOI BibTeX RDF
21	Chuan-Hua Chang	Performance optimization of pipeline circuits with latches and wave pipelining.		1996	RDF
21	Kevin J. Nowka, Michael J. Flynn	System Design Using Wave-Pipelining: A CMOS VLSI Vector Unit.	ISCAS	1995	DBLP DOI BibTeX RDF
21	Wayne P. Burleson, Leonard W. Cotten, Fabian Klass, Maciej J. Ciesielski	Forum: Wave-pipelining: Is it Practical?	ISCAS	1994	DBLP DOI BibTeX RDF
21	Fabian Klass, Johannes M. Mulder	Use of CMOS Technology in Wave Pipelining.	VLSI Design	1992	DBLP DOI BibTeX RDF
21	C. Thomas Gray, Thomas A. Hughes, Sanjay Arora, Wentai Liu, Ralph K. Cavin III	Theoretical and Practical Issues in CMOS Wave Pipelining.	VLSI	1991	DBLP BibTeX RDF
21	Derek C. Wong, Giovanni De Micheli, Michael J. Flynn	Inserting active delay elements to achieve wave pipelining.	ICCAD	1989	DBLP DOI BibTeX RDF
21	John R. Feehrer, Harry F. Jordan	Timing uncertainty analysis for time-of-flight systems.	ICCAD	1994	DBLP DOI BibTeX RDF
20	Mark R. Greenstreet, Brian D. Winters	A Negative-Overhead, Self-Timed Pipeline.	ASYNC	2002	DBLP DOI BibTeX RDF
14	Masa-Aki Fukase, Kazunori Noda, Atsuko Yokoyama, Tomoaki Sato	Design and chip implementation of the ubiquitous processor HCgorilla.	ASP-DAC	2009	DBLP DOI BibTeX RDF
14	Phi-Hung Pham, Yogendera Kumar, Chulwoo Kim	High Performance and Area-Efficient Circuit-Switched Network on Chip Design.	CIT	2006	DBLP DOI BibTeX RDF
14	Miguel Eduardo Litvin, Samiha Mourad	Self-reset logic for fast arithmetic applications.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
14	Brian Von Herzen	Signal processing at 250 MHz using high-performance FPGA's.	IEEE Trans. Very Large Scale Integr. Syst.	1998	DBLP DOI BibTeX RDF
14	Shangzhi Sun, David Hung-Chang Du, Hsi-Chuan Chen	Efficient timing analysis for CMOS circuits considering data dependent delays.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF