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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 68 occurrences of 53 keywords
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Results
Found 56 publication records. Showing 56 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
97 | Chuan-Hua Chang, Edward S. Davidson, Karem A. Sakallah |
Maximum rate single-phase clocking of a closed pipeline including wave pipelining, stoppability, and startability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(12), pp. 1526-1545, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
95 | Rajesh S. Parthasarathy, Ramalingam Sridhar |
Double Pass Transistor Logic for High Performance Wave Pipeline Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 11th International Conference on VLSI Design (VLSI Design 1991), 4-7 January 1998, Chennai, India, pp. 495-500, 1998, IEEE Computer Society, 0-8186-8224-8. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
95 | Yuan-man Tong, Zhiying Wang 0003, Kui Dai, Hongyi Lu |
Designing Power Analysis Resistant and High Performance Block Cipher Coprocessor Using WDDL and Wave-Pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Inscrypt ![In: Information Security and Cryptology, Second SKLOIS Conference, Inscrypt 2006, Beijing, China, November 29 - December 1, 2006, Proceedings, pp. 66-77, 2006, Springer, 3-540-49608-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
WDDL, power analysis resistant, block cipher, design flow, Wave-pipelining |
95 | Jiang Xu 0001, Wayne H. Wolf |
Wave pipelining for application-specific networks-on-chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES 2002, Greenoble, France, October 8-11, 2002, pp. 198-201, 2002, ACM, 1-58113-575-0. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
system-on-chip (SoC), interconnection, networks-on-chip (NoC), wave pipelining, coupling capacitance |
83 | Wayne P. Burleson, Maciej J. Ciesielski, Fabian Klass, W. Liu |
Wave-pipelining: a tutorial and research survey. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 6(3), pp. 464-474, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
83 | Debabrata Ghosh, S. K. Nandy 0001 |
Design and realization of high-performance wave-pipelined 8×8 b multiplier in CMOS technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 3(1), pp. 36-48, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
83 | G. Enrique Fernandez, R. Sridhar |
Dual rail static CMOS architecture for wave pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 9th International Conference on VLSI Design (VLSI Design 1996), 3-6 January 1996, Bangalore, India, pp. 335-336, 1996, IEEE Computer Society, 0-8186-7228-5. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
dual rail static CMOS architecture, gate capacitance, storage elements, DRSCMOS, multi-functional basic building blocks, combinational logic block, delays, timing, throughput, combinational circuits, power consumption, pipeline processing, CMOS logic circuits, digital systems, capacitance, wave pipelining, delay variations |
70 | Fabian Klass, Michael J. Flynn, Ad J. van de Goor |
Fast multiplication in VLSI using wave pipelining techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 7(3), pp. 233-248, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
69 | Derek C. Wong, Giovanni De Micheli, Michael J. Flynn |
Designing high-performance digital circuits using wave pipelining: algorithms and practical experiences. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(1), pp. 25-46, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
63 | Eduardo I. Boemo, Sergio López-Buedo, Juan M. Meneses |
Some experiments about wave pipelining on FPGA's. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 6(2), pp. 232-237, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
61 | V. Vireen, N. Venugopalachary, G. Seetharaman, B. Venkataramani |
Built in Self Test Based Design of Wave-Pipelined Circuits in ASICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: VLSI Design 2009: Improving Productivity through Higher Abstraction, The 22nd International Conference on VLSI Design, New Delhi, India, 5-9 January 2009, pp. 473-478, 2009, IEEE Computer Society, 978-0-7695-3506-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
61 | G. Seetharaman, B. Venkataramani |
Automation Schemes for FPGA Implementation of Wave-Pipelined Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Reconfigurable Technol. Syst. ![In: ACM Trans. Reconfigurable Technol. Syst. 2(2), pp. 11:1-11:19, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
FPGA, pipelining, SOC, CORDIC, wave-pipelining, DAA |
60 | Masa-Aki Fukase, Ryusuke Egawa, Tomoaki Sato, Tadao Nakamura |
Scaling Up Of Wave Pipelines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 14th International Conference on VLSI Design (VLSI Design 2001), 3-7 January 2001, Bangalore, India, pp. 439-445, 2001, IEEE Computer Society, 0-7695-0831-6. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
55 | Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk |
High-throughput interconnect wave-pipelining for global communication in FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 16th International Symposium on Field Programmable Gate Arrays, FPGA 2008, Monterey, California, USA, February 24-26, 2008, pp. 258, 2008, ACM, 978-1-59593-934-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
54 | Paul Teehan, Guy G. Lemieux, Mark R. Greenstreet |
Towards reliable 5Gbps wave-pipelined and 3Gbps surfing interconnect in 65nm FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, FPGA 2009, Monterey, California, USA, February 22-24, 2009, pp. 43-52, 2009, ACM, 978-1-60558-410-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
on-chip serdes, fpga, reliable, network-on-chip, interconnect, programmable, wave pipelining, bit-serial, surfing |
47 | Mitrajit Chatterjee, Savita Banerjee, Dhiraj K. Pradhan |
Buffer Assignment Algorithms on Data Driven ASICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 49(1), pp. 16-32, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
throughput, Application specific integrated circuits, buffers, data flow graph, wave-pipelining, data driven architecture |
46 | Oliver Hauck, A. Katoch, Sorin A. Huss |
VLSI System Design Using Asynchronous Wave Pipelines: A 0.35?m CMOS 1.5 GHz Elliptic Curve Public Key Cryptosystem Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000), 2-6 April 2000, Eilat, Israel, pp. 188-, 2000, IEEE Computer Society, 0-7695-0586-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
46 | Debabrata Ghosh, Soumitra Kumar Nandy |
Wave pipelined architecture folding: a method to achieve low power and low area. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 184-, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
wave pipelined architecture folding, clock-free wave pipelining scheme, chip area reduction, VLSI, low power design, logic design, pipeline processing, integrated circuit design, digital integrated circuits |
43 | Jos Sulistyo, Dong Sam Ha |
5 GHz pipelined multiplier and MAC in 0.18µm complementary static CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 117-120, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
41 | José G. Delgado-Frias, Jabulani Nyathi, Laxmi N. Bhuyan |
A wave-pipelined router architecture using ternary associative memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 10th ACM Great Lakes Symposium on VLSI 2000, Chicago, Illinois, USA, March 2-4, 2000, pp. 67-70, 2000, ACM, 1-58113-251-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
40 | Hong-Yean Hsieh, Wentai Liu, Ralph K. Cavin III, C. Thomas Gray |
Concurrent timing optimization of latch-based digital systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1995 International Conference on Computer Design (ICCD '95), VLSI in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings, pp. 680-685, 1995, IEEE Computer Society, 0-8186-7165-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
concurrent timing optimization, latch-based digital systems, digital system timing, intentional clock skew, latch-based designed systems, multi-phase clocking, resynchronization, latches insertion, optimisation, timing, logic design, flip-flops, retiming, mixed integer linear program, race conditions, integrated framework, wave pipelining, hazards and race conditions, clock period |
35 | Donald A. Joy, Maciej J. Ciesielski |
Clock period minimization with wave pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(4), pp. 461-472, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
34 | C. Thomas Gray, Wentai Liu, Ralph K. Cavin III |
Timing constraints for wave-pipelined systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(8), pp. 987-1004, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
33 | José Duato, Pedro López 0001, Sudhakar Yalamanchili |
Deadlock- and Livelock-Free Routing Protocols for Wave Switching. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPPS ![In: 11th International Parallel Processing Symposium (IPPS '97), 1-5 April 1997, Geneva, Switzerland, Proceedings, pp. 570-577, 1997, IEEE Computer Society, 0-8186-7792-9. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
29 | Chung-Sheng Li, Kumar N. Sivarajan, David G. Messerschmitt |
Statistical analysis of timing rules for high-speed synchronous VLSI systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 7(4), pp. 477-482, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
28 | Terrence S. T. Mak, Crescenzo D'Alessandro, N. Pete Sedcole, Peter Y. K. Cheung, Alexandre Yakovlev, Wayne Luk |
Implementation of Wave-Pipelined Interconnects in FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NOCS ![In: Second International Symposium on Networks-on-Chips, NOCS 2008, 5-6 April 2008, Newcastle University, UK. Proceedings, pp. 213-214, 2008, IEEE Computer Society, 978-0-7695-3098-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
28 | Woo Jin Kim, Yong-Bin Kim |
Automating Wave-Pipelined Circuit Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 20(6), pp. 51-58, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
28 | Karem A. Sakallah, Trevor N. Mudge, Timothy M. Burks, Edward S. Davidson |
Synchronization of pipelines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(8), pp. 1132-1146, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
28 | Abdulqader Nael Mahmoud, Frederic Vanderveken, Christoph Adelmann, Florin Ciubotaru, Said Hamdioui, Sorin Cotofana |
Achieving Wave Pipelining in Spin Wave Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 22nd International Symposium on Quality Electronic Design, ISQED 2021, Santa Clara, CA, USA, April 7-9, 2021, pp. 54-59, 2021, IEEE, 978-1-7281-7641-3. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
26 | Suryanarayana Tatapudi, José G. Delgado-Frias |
A High Performance Hybrid Wave-Pipelined Multiplier. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), New Frontiers in VLSI Design, 11-12 May 2005, Tampa, FL, USA, pp. 282-283, 2005, IEEE Computer Society, 0-7695-2365-X. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
26 | Ram K. Krishnamurthy, Ramalingam Sridhar |
A CMOS wave-pipelined image processor for real-time morphology . ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1995 International Conference on Computer Design (ICCD '95), VLSI in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings, pp. 638-643, 1995, IEEE Computer Society, 0-8186-7165-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
CMOS wave-pipelined image processor, real-time morphology, high-speed morphological image processor, wave-pipelined transmission gate logic, two-stage morphological skeleton transform filter, regular pipelined architectures, real-time systems, computational complexity, image processing, latency, pipeline processing, CMOS integrated circuits, hardware complexity |
26 | Ajay Joshi, Jeffrey A. Davis |
Wave-pipelined 2-slot time division multiplexed (WP/2-TDM) routing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, Chicago, Illinois, USA, April 17-19, 2005, pp. 446-451, 2005, ACM, 1-59593-057-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
interconnect sharing, time division, wave-pipelining |
26 | Michael J. Flynn, Kevin J. Nowka, Gary Bewick, Eric M. Schwarz, Nhon T. Quach |
The SNAP Project: Towards Sub-Nanosecond Arithmetic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 12th Symposium on Computer Arithmetic (ARITH-12 '95), July 19-21, 1995, Bath, England, UK, pp. 75-, 1995, IEEE Computer Society, 0-8186-7089-4. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
floating-point multiplication, computer arithmetic, floating-point arithmetic, wave pipelining, floating-point addition |
21 | Odysseas Zografos, A. De Meester, Eleonora Testa, Mathias Soeken, Pierre-Emmanuel Gaillardon, Giovanni De Micheli, Luca Gaetano Amarù, Praveen Raghavan, Francky Catthoor, Rudy Lauwereins |
Wave pipelining for majority-based beyond-CMOS technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation & Test in Europe Conference & Exhibition, DATE 2017, Lausanne, Switzerland, March 27-31, 2017, pp. 1306-1311, 2017, IEEE, 978-3-9815370-8-6. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
21 | M. Madheswaran, T. Menakadevi |
An Improved Direct Digital Synthesizer Using Hybrid Wave Pipelining and CORDIC algorithm for Software Defined Radio. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Circuits Syst. Signal Process. ![In: Circuits Syst. Signal Process. 32(3), pp. 1219-1238, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
21 | Venkatasubramanian Adhinarayanan, Rengaprabhu Paramasivam, Seetharaman Gopalakrishnan |
ASIC Implementation of One Level 2D-DWT Using Wave-Pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asia International Conference on Modelling and Simulation ![In: Proceedings of the Asia Modelling Symposium 2013, Seventh Asia International Conference on Mathematical Modelling and Computer Simulation, AMS 2013, 23 July, 2013, Hong Kong, China / 25 July, 2013, Kuala Lumpur, Malaysia, pp. 172-175, 2013, IEEE, 978-0-7695-5101-2. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
21 | Refik Sever, Murat Askar |
8×8-Bit multiplier designed with a new wave-pipelining scheme. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2010), May 30 - June 2, 2010, Paris, France, pp. 2095-2098, 2010, IEEE, 978-1-4244-5308-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
21 | Miguel Eduardo Litvin, Samiha Mourad |
Wave Pipelining Using Self Reset Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: VLSI Design 2008, pp. 738983:1-738983:6, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
21 | Miguel Eduardo Litvin, Samiha Mourad, William Terry, Janice Terry |
Wave Pipelining using Self Reset Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 13th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2006, Nice, France, December 10-13, 2006, pp. 1280-1283, 2006, IEEE, 1-4244-0395-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
21 | Suryanarayana Tatapudi, José G. Delgado-Frias |
A Pipelined Multiplier Using A Hybrid Wave-Pipelining Scheme. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CDES ![In: Proceedings of the 2005 International Conference on Computer Design, CDES 2005, Las Vegas, Nevada, USA, June 27-30, 2005, pp. 191-197, 2005, CSREA Press, 1-932415-54-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP BibTeX RDF |
|
21 | Stephan Hermanns, Sorin A. Huss |
Synchronisierungsprobleme von Schaltwerken in Wave Pipelining Architektur und ihre Auswirkungen auf die Wahl der Schaltungstechnik. ![Search on Bibsonomy](Pics/bibsonomy.png) |
GI Jahrestagung (1) ![In: 35. Jahrestagung der Gesellschaft für Informatik, Informatik LIVE!, INFORMATIK 2005, Bonn, Germany, September 19-22, 2005, Band 1, pp. 449, 2005, GI, 3-88579-396-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP BibTeX RDF |
|
21 | Brian D. Winters, Mark R. Greenstreet |
Surfing: a robust form of wave pipelining using self-timed circuit techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microprocess. Microsystems ![In: Microprocess. Microsystems 27(9), pp. 409-419, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
21 | Arindam Mukherjee 0001, Malgorzata Marek-Sadowska, Stephen I. Long |
Wave pipelining YADDs-a feasibility study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CICC ![In: Proceedings of the IEEE 1999 Custom Integrated Circuits Conference, CICC 1999, San Diego, CA, USA, May 16-19, 1999, pp. 559-562, 1999, IEEE, 0-7803-5443-5. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
21 | Chuan-Hua Chang |
Performance optimization of pipeline circuits with latches and wave pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
1996 |
RDF |
|
21 | Kevin J. Nowka, Michael J. Flynn |
System Design Using Wave-Pipelining: A CMOS VLSI Vector Unit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30 - May 3, 1995, pp. 2301-2304, 1995, IEEE, 0-7803-2570-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
21 | Wayne P. Burleson, Leonard W. Cotten, Fabian Klass, Maciej J. Ciesielski |
Forum: Wave-pipelining: Is it Practical? ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30 - June 2, 1994, pp. 163-166, 1994, IEEE, 0-7803-1916-8. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
21 | Fabian Klass, Johannes M. Mulder |
Use of CMOS Technology in Wave Pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: Proceedings of the Fifth International Conference on VLSI Design, VLSI Design 1992, Bangalore, India, January 4-7, 1992, pp. 303-308, 1992, IEEE Computer Society, 0-8186-2465-5. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
21 | C. Thomas Gray, Thomas A. Hughes, Sanjay Arora, Wentai Liu, Ralph K. Cavin III |
Theoretical and Practical Issues in CMOS Wave Pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI ![In: VLSI 91, Proceedings of the IFIP TC10/WG 10.5 International Conference on Very Large Scale Integration, Edinburgh, Scotland, 20-22 August, 1991, pp. 397-409, 1991, North-Holland, 0-444-89019-X. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP BibTeX RDF |
|
21 | Derek C. Wong, Giovanni De Micheli, Michael J. Flynn |
Inserting active delay elements to achieve wave pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 1989 IEEE International Conference on Computer-Aided Design, ICCAD 1989, Santa Clara, CA, USA, November 5-9, 1989. Digest of Technical Papers, pp. 270-273, 1989, IEEE Computer Society, 0-8186-1986-4. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
21 | John R. Feehrer, Harry F. Jordan |
Timing uncertainty analysis for time-of-flight systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1994, San Jose, California, USA, November 6-10, 1994, pp. 728-735, 1994, IEEE Computer Society / ACM, 0-89791-690-5. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
20 | Mark R. Greenstreet, Brian D. Winters |
A Negative-Overhead, Self-Timed Pipeline. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 8th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2002), 9-11 April 2002, Manchester, UK, pp. 37-46, 2002, IEEE Computer Society, 0-7695-1540-1. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
14 | Masa-Aki Fukase, Kazunori Noda, Atsuko Yokoyama, Tomoaki Sato |
Design and chip implementation of the ubiquitous processor HCgorilla. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 14th Asia South Pacific Design Automation Conference, ASP-DAC 2009, Yokohama, Japan, January 19-22, 2009, pp. 129-130, 2009, IEEE, 978-1-4244-2748-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
14 | Phi-Hung Pham, Yogendera Kumar, Chulwoo Kim |
High Performance and Area-Efficient Circuit-Switched Network on Chip Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CIT ![In: Sixth International Conference on Computer and Information Technology (CIT 2006), 20-22 September 2006, Seoul, Korea, pp. 243, 2006, IEEE Computer Society, 0-7695-2687-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
14 | Miguel Eduardo Litvin, Samiha Mourad |
Self-reset logic for fast arithmetic applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 13(4), pp. 462-475, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
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14 | Brian Von Herzen |
Signal processing at 250 MHz using high-performance FPGA's. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 6(2), pp. 238-246, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
14 | Shangzhi Sun, David Hung-Chang Du, Hsi-Chuan Chen |
Efficient timing analysis for CMOS circuits considering data dependent delays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(6), pp. 546-552, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
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