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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 845 occurrences of 538 keywords
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Found 5134 publication records. Showing 5134 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
92 | Like Yan, Gang Wang, Tianzhou Chen |
The input-aware dynamic adaptation of area and performance for reconfigurable accelerator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, FPGA 2009, Monterey, California, USA, February 22-24, 2009, pp. 281, 2009, ACM, 978-1-60558-410-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
dynamic adaption, reconfigurable system, loop unrolling, loop accelerator |
84 | Gokhan Memik, Seda Ogrenci Memik, William H. Mangione-Smith |
Design and Analysis of a Layer Seven Network Processor Accelerator Using Reconfigurable Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 10th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2002), 22-24 April 2002, Napa, CA, USA, Proceedings, pp. 131-, 2002, IEEE Computer Society, 0-7695-1801-X. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
84 | Michael Cox, Narendra Bhandari, Michael Shantz |
Multi-Level Texture Caching for 3D Graphics Hardware. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: Proceedings of the 25th Annual International Symposium on Computer Architecture, ISCA 1998, Barcelona, Spain, June 27 - July 1, 1998, pp. 86-97, 1998, IEEE Computer Society, 0-8186-8491-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
82 | Gokhan Memik, William H. Mangione-Smith |
A flexible accelerator for layer 7 networking applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 39th Design Automation Conference, DAC 2002, New Orleans, LA, USA, June 10-14, 2002, pp. 646-651, 2002, ACM, 1-58113-461-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
pattern matching, network processor, accelerator, table lookup, application-specific processor, networking applications |
75 | Jungmin Lee, Zhiling Lan, James F. Amundson, Panagiotis Spentzouris |
Evaluating Performance and Scalability of Advanced Accelerator Simulations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCGRID ![In: Sixth IEEE International Symposium on Cluster Computing and the Grid (CCGrid 2006), 16-19 May 2006, Singapore, pp. 209-216, 2006, IEEE Computer Society, 0-7695-2585-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
66 | Satnam Singh |
Declarative data-parallel programming with the accelerator system. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAMP ![In: Proceedings of the POPL 2010 Workshop on Declarative Aspects of Multicore Programming, DAMP 2010, Madrid, Spain, January 19, 2010, pp. 1-2, 2010, ACM, 978-1-60558-859-9. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
data-parallelsim |
65 | Jae-Gon Lee, Chong-Min Kyung |
PrePack: Predictive Packetizing Scheme for Reducing Channel Traffic in Transaction-Level Hardware/Software Co-Emulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(10), pp. 1935-1949, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
64 | Junho Ahn, Jung-Hi Min, Hojung Cha, Rhan Ha |
A Power Management mechanism for Handheld Systems having a Multimedia Accelerator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PerCom ![In: Sixth Annual IEEE International Conference on Pervasive Computing and Communications (PerCom 2008), 17-21 March 2008, Hong Kong, pp. 663-668, 2008, IEEE Computer Society, 978-0-7695-3113-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
handheld systems, multimedia accelerator, power management, CPU |
61 | Reiner W. Hartenstein, Jürgen Becker 0001, Michael Herz, Rainer Kress 0002, Ulrich Nageldinger |
A Partitioning Programming Environment for a Novel Parallel Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPPS ![In: Proceedings of IPPS '96, The 10th International Parallel Processing Symposium, April 15-19, 1996, Honolulu, Hawaii, USA, pp. 544-548, 1996, IEEE Computer Society, 0-8186-7255-2. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
partitioning programming environment, novel parallel architecture, embedded accelerator, reconfigurable datapath hardware, accelerator partitioning, profiling-driven partitioning, resource-driven sequential partitioning, resource-driven structural partitioning, parallel architectures, software tools, programming environments, reconfigurable architectures, software performance evaluation, parallelizing compiler, performance optimization, program interpreters, parallelising compilers, parallelizing programming environment, optimising compilers, C programs |
56 | Hamid Noori, Farhad Mehdipour, Morteza Saheb Zamani, Koji Inoue, Kazuaki J. Murakami |
Handling Control Data Flow Graphs for a Tightly Coupled Reconfigurable Accelerator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICESS ![In: Embedded Software and Systems, [Third] International Conference, ICESS 2007, Daegu, Korea, May 14-16, 2007, Proceedings, pp. 249-260, 2007, Springer, 978-3-540-72684-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
56 | Robert D. Ryne |
High energy physics - 25 years of accelerator modeling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SC ![In: Proceedings of the ACM/IEEE SC2006 Conference on High Performance Networking and Computing, November 11-17, 2006, Tampa, FL, USA, pp. 60, 2006, ACM Press, 0-7695-2700-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
56 | Catherine H. Crawford, Paul Henning, Michael Kistler, Cornell Wright |
Accelerating computing with the cell broadband engine processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Conf. Computing Frontiers ![In: Proceedings of the 5th Conference on Computing Frontiers, 2008, Ischia, Italy, May 5-7, 2008, pp. 3-12, 2008, ACM, 978-1-60558-077-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
hybrid programming models, accelerators |
56 | Jae-Gon Lee, Moo-Kyoung Chung, Ki-Yong Ahn, Sang-Heon Lee 0006, Chong-Min Kyung |
A Prediction Packetizing Scheme for Reducing Channel Traffic in Transaction-Level Hardware/Software Co-Emulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2005 Design, Automation and Test in Europe Conference and Exposition (DATE 2005), 7-11 March 2005, Munich, Germany, pp. 384-389, 2005, IEEE Computer Society, 0-7695-2288-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
55 | Zhili Zhang, Ling Zhang, Dang-en Xie, Hongchao Xu, Haina Hu |
A Novel DNS Accelerator Design and Implementation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APNOMS ![In: Management Enabling the Future Internet for Changing Business and New Computing Services, 12th Asia-Pacific Network Operations and Management Symposium, APNOMS 2009, Jeju, South Korea, September 23-25, 2009, Proceedings, pp. 458-461, 2009, Springer, 978-3-642-04491-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Renewal policy, Accelerator, DNS, TTL |
52 | Reiner W. Hartenstein, Jürgen Becker 0001 |
Hardware/Software Co-Design for Data-Driven Xputer-based Accelerators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 10th International Conference on VLSI Design (VLSI Design 1997), 4-7 January 1997, Hyderabad, India, pp. 146-150, 1997, IEEE Computer Society, 0-8186-7755-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
data-driven Xputer-based accelerators, CoDe-X, profiling-driven host/accelerator partitioning, resource-driven sequential/structural partitioning, accelerator source code, reconfigurable resources, C dialect, data-procedural language features, parallel programming, partitioning, performance optimization, hardware/software co-design, parallelizing programming environment |
52 | Patrick Schaumont, Bart Vanthournout, Ivo Bolsens, Hugo De Man |
Synthesis of pipelined DSP accelerators with dynamic scheduling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSS ![In: Proceedings of the 8th International Symposium on System Synthesis (ISSS 1995), September 13-15, 1995, Cannes, France, pp. 72-77, 1995, ACM, 0-89791-771-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
DSP algorithms, FFT butterfly accelerator block, application specific DSP accelerators, highly pipelined data paths, pipelined DSP accelerator synthesis, pipelined bit-parallel hardware, silicon, scheduling, parallel architectures, application specific integrated circuits, dynamic scheduling, pipeline processing, circuit CAD, digital signal processing chips, datapath, controller architecture, network synthesis, run-time schedules |
47 | Gang Wang, Du Chen, Jian Chen, Jianliang Ma, Tianzhou Chen |
A Performance Model for Run-Time Reconfigurable Hardware Accelerator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APPT ![In: Advanced Parallel Processing Technologies, 8th International Symposium, APPT 2009, Rapperswil, Switzerland, August 24-25, 2009, Proceedings, pp. 54-66, 2009, Springer, 978-3-642-03643-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
47 | John D. Davis, Zhangxi Tan, Fang Yu 0002, Lintao Zhang |
Designing an Efficient Hardware Implication Accelerator for SAT Solving. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAT ![In: Theory and Applications of Satisfiability Testing - SAT 2008, 11th International Conference, SAT 2008, Guangzhou, China, May 12-15, 2008. Proceedings, pp. 48-62, 2008, Springer, 978-3-540-79718-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
47 | Alexander Maili, Christian Steger, Reinhold Weiss, Rob Quigley, Damian Dalton |
Reducing the Communication Bottleneck via On-Chip Cosimulation of Gate-Level HDL and C-Models on a Hardware Accelerator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), New Frontiers in VLSI Design, 11-12 May 2005, Tampa, FL, USA, pp. 290-291, 2005, IEEE Computer Society, 0-7695-2365-X. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
47 | Cyprian Grassmann, Joachim K. Anlauf |
RACER - A Rapid Prototyping Accelerator for Pulsed Neural Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 10th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2002), 22-24 April 2002, Napa, CA, USA, Proceedings, pp. 277-278, 2002, IEEE Computer Society, 0-7695-1801-X. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
47 | Shao-Yi Chien, Yu-Wen Huang, Liang-Gee Chen |
A hardware accelerator for video segmentation using programmable morphology PE array. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2002 International Symposium on Circuits and Systems, ISCAS 2002, Scottsdale, Arizona, USA, May 26-29, 2002, pp. 341-344, 2002, IEEE, 0-7803-7448-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
47 | Andrei Vladimirescu, David Weiss, Manolis Katevenis, Zvika Bronstein, Alon Kifir, Karja Danuwidjaja, K. C. Ng, Niraj Jain, Steven Lass |
A Vector Hardware Accelerator with Circuit Simulation Emphasis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 24th ACM/IEEE Design Automation Conference. Miami Beach, FL, USA, June 28 - July 1, 1987., pp. 89-94, 1987, IEEE Computer Society Press / ACM. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
|
46 | Peter Bertels, Wim Heirman, Erik H. D'Hollander, Dirk Stroobandt |
Efficient memory management for hardware accelerated Java Virtual Machines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 14(4), pp. 48:1-48:18, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Java Virtual Machine, hardware acceleration, Dynamic memory management |
46 | Kevin Fan, Manjunath Kudlur, Ganesh S. Dasika, Scott A. Mahlke |
Bridging the computation gap between programmable processors and hardwired accelerators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: 15th International Conference on High-Performance Computer Architecture (HPCA-15 2009), 14-18 February 2009, Raleigh, North Carolina, USA, pp. 313-322, 2009, IEEE Computer Society, 978-1-4244-2932-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
46 | Jeff H. Derby, Robert K. Montoye, José E. Moreira |
VICTORIA: VMX indirect compute technology oriented towards in-line acceleration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Conf. Computing Frontiers ![In: Proceedings of the Third Conference on Computing Frontiers, 2006, Ischia, Italy, May 3-5, 2006, pp. 303-312, 2006, ACM, 1-59593-302-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
VMX, SIMD, accelerators, powerPC |
45 | Alejandro Rico, Jeff H. Derby, Robert K. Montoye, Timothy H. Heil, Chen-Yong Cher, Pradip Bose |
Performance and power evaluation of an in-line accelerator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Conf. Computing Frontiers ![In: Proceedings of the 7th Conference on Computing Frontiers, 2010, Bertinoro, Italy, May 17-19, 2010, pp. 81-82, 2010, ACM, 978-1-4503-0044-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
vmx, accelerator, powerpc, simd |
45 | Jue Wang, Beihua Ying, Yongpan Liu, Huazhong Yang, Hui Wang 0004 |
Energy efficient architecture of sensor network node based on compression accelerator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, Boston Area, MA, USA, May 10-12 2009, pp. 117-120, 2009, ACM, 978-1-60558-522-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
compression accelerator, wireless sensor network, energy efficient, chip design |
45 | Manjunath Kudlur, Kevin Fan, Scott A. Mahlke |
Streamroller: : automatic synthesis of prescribed throughput accelerator pipelines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2006, Seoul, Korea, October 22-25, 2006, pp. 270-275, 2006, ACM, 1-59593-370-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
system-level synthesis, loop accelerator, application-specific hardware |
45 | Daniel Dietterle, Rolf Kraemer |
A hardware accelerated implementation of the IEEE 802.15.3 MAC protocol. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Telecommun. Syst. ![In: Telecommun. Syst. 40(3-4), pp. 161-167, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Hardware accelerator, Personal area networks, Protocol implementation |
45 | Lars Bauer, Muhammad Shafique 0001, Jörg Henkel |
MinDeg: a performance-guided replacement policy for run-time reconfigurable accelerators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2009, Grenoble, France, October 11-16, 2009, pp. 335-342, 2009, ACM, 978-1-60558-628-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
extensible embedded processor, reconfigurable computing, kernel, accelerator, replacement, run-time adaptation |
45 | Kris Gaj, Tarek A. El-Ghazawi, Nikitas A. Alexandridis, Jacek R. Radzikowski, Mohamed Taher, Frederic Vroman |
Effective Utilization and Reconfiguration of Distributed Hardware Resources Using Job Management Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 22-26 April 2003, Nice, France, CD-ROM/Abstracts Proceedings, pp. 177, 2003, IEEE Computer Society, 0-7695-1926-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
distributed hardware resources, Job Management Systems, accelerator boards, FPGA, job scheduling, reconfigurable hardware |
38 | Yahya Jan, Lech Józwiak |
CABAC Accelerator Architectures for Video Compression in Future Multimedia: A Survey. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAMOS ![In: Embedded Computer Systems: Architectures, Modeling, and Simulation, 9th International Workshop, SAMOS 2009, Samos, Greece, July 20-23, 2009. Proceedings, pp. 24-35, 2009, Springer, 978-3-642-03137-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
RC hardware architectures, UHDTV, H.264/AVC, video compression, accelerators, multimedia processing, CABAC |
38 | Alan Kennedy, Xiaojun Wang 0001, Bin Liu 0001 |
Energy efficient packet classification hardware accelerator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 22nd IEEE International Symposium on Parallel and Distributed Processing, IPDPS 2008, Miami, Florida USA, April 14-18, 2008, pp. 1-8, 2008, IEEE. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
38 | Kimmo U. Järvinen, Jorma O. Skyttä |
High-Speed Elliptic Curve Cryptography Accelerator for Koblitz Curves. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 16th IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2008, 14-15 April 2008, Stanford, Palo Alto, California, USA, pp. 109-118, 2008, IEEE Computer Society, 978-0-7695-3307-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
38 | Kangtao Kendall Chuang, Sudhakar Yalamanchili, Ada Gavrilovska, Karsten Schwan |
ShareStreams-V: A Virtualized QoS Packet Scheduling Accelerator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 16th IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2008, 14-15 April 2008, Stanford, Palo Alto, California, USA, pp. 265-268, 2008, IEEE Computer Society, 978-0-7695-3307-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
38 | Stamatis Vassiliadis, Filipa Duarte, Stephan Wong |
A Load/Store Unit for a Memcpy Hardware Accelerator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: FPL 2007, International Conference on Field Programmable Logic and Applications, Amsterdam, The Netherlands, 27-29 August 2007, pp. 537-541, 2007, IEEE, 1-4244-1060-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
38 | Salem Fawaz Adra, Ian Griffin, Peter J. Fleming |
An informed convergence accelerator for evolutionary multiobjective optimiser. ![Search on Bibsonomy](Pics/bibsonomy.png) |
GECCO ![In: Genetic and Evolutionary Computation Conference, GECCO 2007, Proceedings, London, England, UK, July 7-11, 2007, pp. 734-740, 2007, ACM, 978-1-59593-697-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
evolutionary multiobjective optimisation, convergence acceleration |
38 | David Tarditi, Sidd Puri, Jose Oglesby |
Accelerator: using data parallelism to program GPUs for general-purpose uses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASPLOS ![In: Proceedings of the 12th International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2006, San Jose, CA, USA, October 21-25, 2006, pp. 325-335, 2006, ACM, 1-59593-451-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
graphics processing units, data parallelism, just-in time compilation |
38 | Zheng Liang, Juha Plosila, Lu Yan, Kaisa Sere |
Implementing a Self-Timed Low-Power Java Accelerator for Network-on-Chip Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PDCAT ![In: Seventh International Conference on Parallel and Distributed Computing, Applications and Technologies (PDCAT 2006), 4-7 December 2006, Taipei, Taiwan, pp. 344-347, 2006, IEEE Computer Society, 0-7695-2736-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
38 | Jayaprakash Pisharath, Alok N. Choudhary |
Design of a Hardware Accelerator for Density Based Clustering Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 16th IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP 2005), 23-25 July 2005, Samos, Greece, pp. 101-106, 2005, IEEE Computer Society, 0-7695-2407-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
38 | Valery Biryukov, Angelika Drees, Raymond Patrick Fliller III, Nikolay Malitsky, Dejan Trbojevic |
Tracking Particles in Accelerator Optics with Crystal Elements. ![Search on Bibsonomy](Pics/bibsonomy.png) |
International Conference on Computational Science (3) ![In: Computational Science - ICCS 2002, International Conference, Amsterdam, The Netherlands, April 21-24, 2002. Proceedings, Part III, pp. 372-380, 2002, Springer, 3-540-43594-8. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
38 | Kwan-Liu Ma, Gregory L. Schussman, Brett Wilson, Kwok Ko, Ji Qiang, Robert D. Ryne |
Advanced visualization technology for terascale particle accelerator simulations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SC ![In: Proceedings of the 2002 ACM/IEEE conference on Supercomputing, Baltimore, Maryland, USA, November 16-22, 2002, CD-ROM, pp. 48:1-48:11, 2002, IEEE Computer Society, 0-7695-1524-X. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
field lines, hardware-assisted techniques, particle accelerators, perception, high-performance computing, volume rendering, texture mapping, scientific visualization, vector field visualization, time-varying data, point-based rendering, visual cues |
38 | Gerald Frank, Georg Hartmann, Axel Jahnke, Martin Schäfer |
An accelerator for neural networks with pulse-coded model neurons. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Neural Networks ![In: IEEE Trans. Neural Networks 10(3), pp. 527-538, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
38 | Björn Bergsten, Michel Couprie, Rubén González-Rubio, Brigitte Kerhervé, Mikal Ziane |
A Parallel Database Accelerator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PARLE (1) ![In: PARLE '89: Parallel Architectures and Languages Europe, Volume I: Parallel Architectures, Eindhoven, The Netherlands, June 12-16, 1989, Proceedings, pp. 397-412, 1989, Springer, 3-540-51284-5. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
37 | Isaac Gelado, Javier Cabezas, Nacho Navarro, John E. Stone, Sanjay J. Patel, Wen-mei W. Hwu |
An asymmetric distributed shared memory model for heterogeneous parallel systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASPLOS ![In: Proceedings of the 15th International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2010, Pittsburgh, Pennsylvania, USA, March 13-17, 2010, pp. 347-358, 2010, ACM, 978-1-60558-839-1. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
asymmetric distributed shared memory, data-centric programming models, heterogeneous systems |
37 | Maurice Keller, Andrew Byrne, William P. Marnane |
Elliptic Curve Cryptography on FPGA for Low-Power Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Reconfigurable Technol. Syst. ![In: ACM Trans. Reconfigurable Technol. Syst. 2(1), pp. 2:1-2:20, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
FPGA, low-power, Cryptography, elliptic curves |
37 | Peter Bertels, Wim Heirman, Dirk Stroobandt |
Strategies for dynamic memory allocation in hybrid architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Conf. Computing Frontiers ![In: Proceedings of the 6th Conference on Computing Frontiers, 2009, Ischia, Italy, May 18-20, 2009, pp. 217-220, 2009, ACM, 978-1-60558-413-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
java, memory management, hardware acceleration |
37 | Perry H. Wang, Jamison D. Collins, Gautham N. Chinya, Hong Jiang, Xinmin Tian, Milind Girkar, Nick Y. Yang, Guei-Yuan Lueh, Hong Wang 0003 |
EXOCHI: architecture and programming environment for a heterogeneous multi-core multithreaded system. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PLDI ![In: Proceedings of the ACM SIGPLAN 2007 Conference on Programming Language Design and Implementation, San Diego, California, USA, June 10-13, 2007, pp. 156-166, 2007, ACM, 978-1-59593-633-2. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
GPU, openMP, heterogeneous multi-cores |
37 | Antonin Hermanek, Michal Kunes, Michal Kvasnicka |
Using Reconfigurable HW for High Dimensional CAF Computation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), Madrid, Spain, August 28-30, 2006, pp. 1-4, 2006, IEEE, 1-4244-0312-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
37 | Jae-Gon Lee, Woo-Seung Yang, Young-Su Kwon, Young-Il Kim, Chong-Min Kyung |
Simulation acceleration of transaction-level models for SoC with RTL sub-blocks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005, pp. 499-502, 2005, ACM Press, 0-7803-8737-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
SoC, systemc, transaction-level modeling, TLM, simulation acceleration |
36 | Hyunchul Park 0001, Yongjun Park 0001, Scott A. Mahlke |
Polymorphic pipeline array: a flexible multicore accelerator with virtualized execution for mobile multimedia applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: 42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), December 12-16, 2009, New York, New York, USA, pp. 370-380, 2009, ACM, 978-1-60558-798-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
programmable accelerator, virtualization, software pipelining |
36 | Mark Hempstead, Gu-Yeon Wei, David M. Brooks |
An accelerator-based wireless sensor network processor in 130nm CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2009 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2009, Grenoble, France, October 11-16, 2009, pp. 215-222, 2009, ACM. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
accelerator-based, wireless sensor networks, ultra-low power |
36 | Michael J. Lyons 0003, David M. Brooks |
The design of a bloom filter hardware accelerator for ultra low power systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009, pp. 371-376, 2009, ACM, 978-1-60558-684-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
wireless sensor network, hardware accelerator, bloom filter |
36 | Jean-Luc Beuchat, Jérémie Detrey, Nicolas Estibals, Eiji Okamoto, Francisco Rodríguez-Henríquez |
Hardware Accelerator for the Tate Pairing in Characteristic Three Based on Karatsuba-Ofman Multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHES ![In: Cryptographic Hardware and Embedded Systems - CHES 2009, 11th International Workshop, Lausanne, Switzerland, September 6-9, 2009, Proceedings, pp. 225-239, 2009, Springer, 978-3-642-04137-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Karatsuba-Ofman multiplier, FPGA, elliptic curve, hardware accelerator, Tate pairing, finite field arithmetic, ? T pairing |
36 | John H. Kelm, Daniel R. Johnson, Matthew R. Johnson 0003, Neal Clayton Crago, William Tuohy, Aqeel Mahesri, Steven S. Lumetta, Matthew I. Frank, Sanjay J. Patel |
Rigel: an architecture and scalable programming interface for a 1000-core accelerator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 36th International Symposium on Computer Architecture (ISCA 2009), June 20-24, 2009, Austin, TX, USA, pp. 140-151, 2009, ACM, 978-1-60558-526-0. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
low-level programming interface, computer architecture, accelerator |
36 | Mario Porrmann, Ulf Witkowski, Heiko Kalte, Ulrich Rückert 0001 |
Implementation of Artificial Neural Networks on a Reconfigurable Hardware Accelerator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PDP ![In: 10th Euromicro Workshop on Parallel, Distributed and Network-Based Processing (PDP 2002), 9-11 January 2002, Canary Islands, Spain, pp. 243-, 2002, IEEE Computer Society, 0-7695-1444-8. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Kohonen, FPGA, Artificial Neural Networks, Self-organizing Map, Reconfigurable, RBF, Hardware Accelerator, Associative Memory |
35 | Liu Ling, Neal Oliver, Bhushan Chitlur, Qigang Wang, Alvin Chen, Wenbo Shen, Zhihong Yu, Arthur Sheiman, Ian McCallum, Joseph Grecco, Henry Mitchel, Dong Liu, Prabhat Gupta |
High-performance, energy-efficient platforms using in-socket FPGA accelerators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, FPGA 2009, Monterey, California, USA, February 22-24, 2009, pp. 261-264, 2009, ACM, 978-1-60558-410-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
in-socket accelerator, fpga, agility |
35 | Yong Dou, Fei Xia, Jingfei Jiang |
Fine-grained parallel application specific computing for RNA secondary structure prediction using SCFGS on FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2009 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2009, Grenoble, France, October 11-16, 2009, pp. 107-116, 2009, ACM. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
SCFGS, reconfigurable algorithm accelerator, secondary structure prediction, FPGA, RNA |
35 | Sébastien Lafond, Johan Lilius |
Interrupt Costs in Embedded System with Short Latency Hardware Accelerators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ECBS ![In: 15th Annual IEEE International Conference and Workshop on Engineering of Computer Based Systems (ECBS 2008), 31 March - 4 April 2008, Belfast, Northern Ireland, pp. 317-325, 2008, IEEE Computer Society, 978-0-7695-3141-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Interrupt, Hardware accelerator |
35 | John H. Kelm, Steven S. Lumetta |
HybridOS: runtime support for reconfigurable accelerators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 16th International Symposium on Field Programmable Gate Arrays, FPGA 2008, Monterey, California, USA, February 24-26, 2008, pp. 212-221, 2008, ACM, 978-1-59593-934-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
CPU/accelerator architecture, operating system, reconfigurable computing |
35 | Giray Kömürcü, Erkay Savas |
An Efficient Hardware Implementation of the Tate Pairing in Characteristic Three. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICONS ![In: The Third International Conference on Systems, ICONS 2008, April 13-18, 2008, Cancun, Mexico, pp. 23-28, 2008, IEEE Computer Society, 978-0-7695-3105-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Bilinear pairings, hardware accelerator, Tate Pairing, FPGA Implementation, Characteristic Three |
35 | Chen-Yong Cher, Michael Gschwind |
Cell GC: using the cell synergistic processor as a garbage collection coprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VEE ![In: Proceedings of the 4th International Conference on Virtual Execution Environments, VEE 2008, Seattle, WA, USA, March 5-7, 2008, pp. 141-150, 2008, ACM, 978-1-59593-796-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
BDW, SPU, explicitly managed memory hierarchies, local store, garbage collection, accelerator, SPE, coprocessor, cell, mark-sweep |
35 | Kevin Fan, Manjunath Kudlur, Hyunchul Park 0001, Scott A. Mahlke |
Increasing hardware efficiency with multifunction loop accelerators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2006, Seoul, Korea, October 22-25, 2006, pp. 276-281, 2006, ACM, 1-59593-370-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
multifunction design, high-level synthesis, modulo scheduling, loop accelerator, application-specific hardware |
35 | Monther Aldwairi, Thomas M. Conte, Paul D. Franzon |
Configurable string matching hardware for speeding up intrusion detection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGARCH Comput. Archit. News ![In: SIGARCH Comput. Archit. News 33(1), pp. 99-107, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
snort accelerator, string matchin, intrusion detection |
35 | Harald Simmler, Holger Singpiel, Reinhard Männer |
Real-Time Primer Design for DNA Chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 22-26 April 2003, Nice, France, CD-ROM/Abstracts Proceedings, pp. 153, 2003, IEEE Computer Society, 0-7695-1926-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Primer design, High performance parallel architecture, FPGA, Hardware accelerator, HPC |
35 | Rajeev Murgai, Masahiro Fujita, Fumiyasu Hirose |
Logic synthesis for a single large look-up table. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1995 International Conference on Computer Design (ICCD '95), VLSI in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings, pp. 415-424, 1995, IEEE Computer Society, 0-8186-7165-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
single large look-up table, LUT-based field-programmable gate array architectures, simulation time minimisation, compile-code, software simulation, field programmable gate arrays, Boolean function, logic design, logic synthesis, hardware accelerator, programmable logic arrays, table lookup, logic simulation, FPGA architectures, logic functions, on-chip memory, memory constraint |
28 | Jason Yu, Christopher Eagleston, Christopher Han-Yu Chou, Maxime Perreault, Guy G. Lemieux |
Vector Processing as a Soft Processor Accelerator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Reconfigurable Technol. Syst. ![In: ACM Trans. Reconfigurable Technol. Syst. 2(2), pp. 12:1-12:34, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
parallelism, Computer architecture, embedded processor, vector processor, multimedia processing, soft processor |
28 | Dimitris Theodoropoulos, Georgi Kuzmanov, Georgi Gaydadjiev |
Reconfigurable accelerator for WFS-based 3D-audio. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 23rd IEEE International Symposium on Parallel and Distributed Processing, IPDPS 2009, Rome, Italy, May 23-29, 2009, pp. 1-8, 2009, IEEE. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
28 | Yahya Jan, Lech Józwiak |
Survey of Advanced CABAC Accelerator Architectures for Future Multimedia. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARC ![In: Reconfigurable Computing: Architectures, Tools and Applications, 5th International Workshop, ARC 2009, Karlsruhe, Germany, March 16-18, 2009. Proceedings, pp. 342-348, 2009, Springer, 978-3-642-00640-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
RC hardware architectures, UHDTV, H.264/AVC, video compression, accelerators, multimedia processing, CABAC |
28 | Jason Yu, Guy G. Lemieux, Christopher Eagleston |
Vector processing as a soft-core CPU accelerator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 16th International Symposium on Field Programmable Gate Arrays, FPGA 2008, Monterey, California, USA, February 24-26, 2008, pp. 222-232, 2008, ACM, 978-1-59593-934-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
C2H, FPGA, configurable, embedded processor, application specific, soft processor, data-level parallelism |
28 | Ioannis Psaras, Vassilis Tsaoussidis |
AIRA: Additive Increase Rate Accelerator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Networking ![In: NETWORKING 2008, Ad Hoc and Sensor Networks, Wireless Networks, Next Generation Internet , 7th International IFIP-TC6 Networking Conference, Singapore, May 5-9, 2008, Proceedings, pp. 691-702, 2008, Springer, 978-3-540-79548-3. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
28 | Farhad Mehdipour, Hamid Noori, Morteza Saheb Zamani, Koji Inoue, Kazuaki J. Murakami |
Design space exploration for a coarse grain accelerator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 13th Asia South Pacific Design Automation Conference, ASP-DAC 2008, Seoul, Korea, January 21-24, 2008, pp. 685-690, 2008, IEEE, 978-1-4244-1921-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
28 | John D. Davis, Zhangxi Tan, Fang Yu 0002, Lintao Zhang |
A practical reconfigurable hardware accelerator for Boolean satisfiability solvers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008, pp. 780-785, 2008, ACM, 978-1-60558-115-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
BCP, FPGA, reconfigurable, SAT solver, co-processor |
28 | Antonino Tumeo, Matteo Monchiero, Gianluca Palermo, Fabrizio Ferrandi, Donatella Sciuto |
A Pipelined Fast 2D-DCT Accelerator for FPGA-based SoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), May 9-11, 2007, Porto Alegre, Brazil, pp. 331-336, 2007, IEEE Computer Society, 0-7695-2896-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
28 | Scott Sirowy, Yonghui Wu, Stefano Lonardi, Frank Vahid |
Two-level microprocessor-accelerator partitioning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2007 Design, Automation and Test in Europe Conference and Exposition, DATE 2007, Nice, France, April 16-20, 2007, pp. 313-318, 2007, EDA Consortium, San Jose, CA, USA, 978-3-9810801-2-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
28 | John A. Nestor, Jeremy Lavine |
L4: An FPGA-Based Accelerator for Detailed Maze Routing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: FPL 2007, International Conference on Field Programmable Logic and Applications, Amsterdam, The Netherlands, 27-29 August 2007, pp. 357-362, 2007, IEEE, 1-4244-1060-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
28 | Zdenek Pohl, Milan Tichý |
RLS Lattice Algorithm with Order Probability Evaluation as an Accelerator for the Microblaze Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: FPL 2007, International Conference on Field Programmable Logic and Applications, Amsterdam, The Netherlands, 27-29 August 2007, pp. 774-777, 2007, IEEE, 1-4244-1060-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
28 | Zhihua Cui, Jianchao Zeng 0001, Guoji Sun |
Using Accelerator Feedback to Improve Performance of Integral-Controller Particle Swarm Optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE ICCI ![In: Proceedings of the Firth IEEE International Conference on Cognitive Informatics, ICCI 2006, July 17-19, Beijing, China, pp. 665-668, 2006, IEEE Computer Society, 1-4244-0475-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
28 | Seung Wook Lee, Jong Tae Kim, Hongmoon Wang, Dae Jin Bae, Keon-Myung Lee, Jee-Hyung Lee, Jae Wook Jeon |
Architecture of RETE Network Hardware Accelerator for Real-Time Context-Aware System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
KES (1) ![In: Knowledge-Based Intelligent Information and Engineering Systems, 10th International Conference, KES 2006, Bournemouth, UK, October 9-11, 2006, Proceedings, Part I, pp. 401-408, 2006, Springer, 3-540-46535-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
28 | Wan-Yu Chen, Yu-Lin Chang, Hsu-Kuang Chiu, Shao-Yi Chien, Liang-Gee Chen |
Real-Time Depth Image based Rendering Hardware Accelerator for Advanced Three Dimensional Television System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICME ![In: Proceedings of the 2006 IEEE International Conference on Multimedia and Expo, ICME 2006, July 9-12 2006, Toronto, Ontario, Canada, pp. 2069-2072, 2006, IEEE Computer Society, 1-4244-0367-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
28 | Chung-Ho Chen, Yi-Cheng Chung, Chen-Hua Wang, Han-Chiang Chen |
Design of a Giga-bit Hardware Accelerator for the iSCSI Initiator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCN ![In: LCN 2006, The 31st Annual IEEE Conference on Local Computer Networks, Tampa, Florida, USA, 14-16 November 2006, pp. 257-263, 2006, IEEE Computer Society, 1-4244-0418-5. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
28 | Zheng Liang, Juha Plosila, Lu Yan, Kaisa Sere |
On-chip Debug for an Asynchronous Java Accelerator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PDCAT ![In: Sixth International Conference on Parallel and Distributed Computing, Applications and Technologies (PDCAT 2005), 5-8 December 2005, Dalian, China, pp. 312-315, 2005, IEEE Computer Society, 0-7695-2405-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Java, Debug, Embedded, Asynchronous, Co-design |
28 | Valery Sklyarov, Iouliia Skliarova, Arnaldo S. R. Oliveira, António de Brito Ferrari |
A Dynamically Reconfigurable Accelerator for Operations over Boolean and Ternary Vectors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 2003 Euromicro Symposium on Digital Systems Design (DSD 2003), Architectures, Methods and Tools, 3-5 September 2003, Belek-Antalya, Turkey, pp. 222-229, 2003, IEEE Computer Society, 0-7695-2003-0. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
28 | Jiri Novotný, Otto Fucík, David Antos |
Project of IPv6 Router with FPGA Hardware Accelerator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field Programmable Logic and Application, 13th International Conference, FPL 2003, Lisbon, Portugal, September 1-3, 2003, Proceedings, pp. 964-967, 2003, Springer, 3-540-40822-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Liberouter, Virtex II, FPGA, IPv6, router |
28 | Sheng-Bo Xu, Lejla Batina |
Efficient Implementation of Elliptic Curve Cryptosystems on an ARM7 with Hardware Accelerator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISC ![In: Information Security, 4th International Conference, ISC 2001, Malaga, Spain, October 1-3, 2001, Proceedings, pp. 266-279, 2001, Springer, 3-540-42662-0. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
28 | Donald L. Hung, Heng-Da Cheng, Savang Sengkhamyong |
Design of a configurable accelerator for moment computation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 8(6), pp. 741-746, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
28 | Shuichi Ichikawa, Hidemitsu Saito, Lerdtanaseangtham Udorn, Kouji Konishi |
Evaluation of Accelerator Designs for Subgraph Isomorphism Problem. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, FPL 2000, Villach, Austria, August 27-30, 2000, Proceedings, pp. 729-738, 2000, Springer, 3-540-67899-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
28 | Bertil Schmidt |
Design of a Parallel Accelerator for Volume Rendering. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Euro-Par ![In: Euro-Par 2000, Parallel Processing, 6th International Euro-Par Conference, Munich, Germany, August 29 - September 1, 2000, Proceedings., pp. 1095-1104, 2000, Springer, 3-540-67956-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
28 | L. Louis Zhang, Qiang Wang, David M. Lewis |
Design of a VLIW Compute Accelerator on the Transmogrifier-2. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 8th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2000), 17-19 April 2000, Napa Valley, CA, USA, Proceedings, pp. 3-12, 2000, IEEE Computer Society, 0-7695-0871-5. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
28 | Wayne P. Burleson, Jason Ko, Douglas Niehaus, Krithi Ramamritham, John A. Stankovic, Gary Wallace, Charles C. Weems |
The spring scheduling coprocessor: a scheduling accelerator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 7(1), pp. 38-47, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
28 | David M. Lewis |
A Programmable Hardware Accelerator for Compiled Electrical Simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 25th ACM/IEEE Conference on Design Automation, DAC '88, Anaheim, CA, USA, June 12-15, 1988., pp. 172-177, 1988, ACM. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP BibTeX RDF |
|
28 | Prathima Agrawal, William J. Dally, Ahmed K. Ezzat, W. C. Fischer, H. V. Jagadish, A. S. Krishnakumar |
Architecture and Design of the MARS Hardware Accelerator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 24th ACM/IEEE Design Automation Conference. Miami Beach, FL, USA, June 28 - July 1, 1987., pp. 101-107, 1987, IEEE Computer Society Press / ACM. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
|
28 | Youngju Won, Sartaj Sahni, Yacoub M. El-Ziq |
A Hardware Accelerator for Maze Routing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 24th ACM/IEEE Design Automation Conference. Miami Beach, FL, USA, June 28 - July 1, 1987., pp. 800-806, 1987, IEEE Computer Society Press / ACM. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
|
28 | Shaoshan Liu, Richard Neil Pittman, Alessandro Forin |
Energy reduction with run-time partial reconfiguration (abstract only). ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, FPGA 2010, Monterey, California, USA, February 21-23, 2010, pp. 292, 2010, ACM, 978-1-60558-911-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
fpga, energy |
28 | Ningyi Xu, Xiongfei Cai, Rui Gao, Lei Zhang 0001, Feng-Hsiung Hsu |
FPGA Acceleration of RankBoost in Web Search Engines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Reconfigurable Technol. Syst. ![In: ACM Trans. Reconfigurable Technol. Syst. 1(4), pp. 19:1-19:19, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
FPGA, hardware acceleration |
28 | Filip Blagojevic, Costin Iancu, Katherine A. Yelick, Matthew Curtis-Maury, Dimitrios S. Nikolopoulos, Benjamin Rose |
Scheduling dynamic parallelism on accelerators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Conf. Computing Frontiers ![In: Proceedings of the 6th Conference on Computing Frontiers, 2009, Ischia, Italy, May 18-20, 2009, pp. 161-170, 2009, ACM, 978-1-60558-413-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
cooperative scheduling, cell be |
28 | Mahdi Elghazali, Ahmed Elhossini, Shawki Areibi |
HW/SW co-design architecture exploration for VLSI maze routing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCECE ![In: Proceedings of the 22nd Canadian Conference on Electrical and Computer Engineering, CCECE 2009, 3-6 May 2009, Delta St. John's Hotel and Conference Centre, St. John's, Newfoundland, Canada, pp. 1188-1193, 2009, IEEE, 978-1-4244-3508-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
28 | Michael Kistler, John A. Gunnels, Daniel A. Brokenshire, Brad Benton |
Petascale computing with accelerators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PPoPP ![In: Proceedings of the 14th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, PPOPP 2009, Raleigh, NC, USA, February 14-18, 2009, pp. 241-250, 2009, ACM, 978-1-60558-397-6. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
hybrid programming models, accelerators |
28 | Seda Ogrenci Memik, Nikolaos Bellas, Somsubhra Mondal |
Presynthesis Area Estimation of Reconfigurable Streaming Accelerators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(11), pp. 2027-2038, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
28 | Giovanni Danese, Francesco Leporati, Marco Bera, Mauro Giachero, Nelson Nazzicari, Alvaro Spelgatti |
An Application Specific Processor for Montecarlo Simulations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PDP ![In: 15th Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP 2007), 7-9 February 2007, Naples, Italy, pp. 262-269, 2007, IEEE Computer Society, 0-7695-2784-1. The full citation details ...](Pics/full.jpeg) |
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