Search results for "analog/digital"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
121	Thelma Estrin	The UCLA Brain Research Institute data processing laboratory.	History of Medical Informatics	1987	DBLP DOI BibTeX RDF
57	Ami Litman, Shiri Moran-Schein	Smooth scheduling under variable rates or the analog-digital confinement game.	SPAA	2006	DBLP DOI BibTeX RDF	EDF schemes, EDF strategies, concurrent confinement games, confinement games, non-concurrent confinement games, smooth scheduling, variable rates, online scheduling, two players games
50	Rakesh Chadha, Chandramouli Visweswariah, Chin-Fu Chen	M3-a multilevel mixed-mode mixed A/D simulator.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1992	DBLP DOI BibTeX RDF
50	Anirudh Devgan, Ronald A. Rohrer	Efficient simulation of interconnect and mixed analog-digital circuits in ACES.	VLSI Design	1995	DBLP DOI BibTeX RDF	adaptively controlled explicit simulation, mixed analog-digital circuits, analog circuit simulation, interconnect circuit simulation, AWE macromodels, nonlinear terminations, variable accuracy device models, circuit topology constraints removal, timing, circuit analysis computing, transient analysis, analogue integrated circuits, integrated circuit interconnections, mixed analogue-digital integrated circuits, ACES, transient simulation, timing simulation
44	Valeriu Beiu	A Novel Highly Reliable Low-Power Nano Architecture When von Neumann Augments.	ASAP	2004	DBLP DOI BibTeX RDF
43	Arun Achyuthan, Mohamed I. Elmasry	Mixed analog/digital hardware synthesis of artificial neural networks.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
43	Daniele Bonomi, Giorgio Boselli, Gabriella Trucco, Valentino Liberali	Effects of digital switching noise on analog voltage references in mixed-signal CMOS ICs.	SBCCI	2006	DBLP DOI BibTeX RDF	crosstalk, mixed-signal ICs
39	Markus Bühler, Jürgen Koehl, Jeanne Bickford, Jason Hibbeler, Ulf Schlichtmann, Ralf Sommer, Michael Pronath, Andreas Ripp	DFM/DFY design for manufacturability and yield - influence of process variations in digital, analog and mixed-signal circuit design.	DATE	2006	DBLP DOI BibTeX RDF
38	Sree Ganesan, Ranga Vemuri	Analog-Digital Partitioning for Field-Programmable Mixed Signal Systems.	ARVLSI	2001	DBLP DOI BibTeX RDF
38	Brian A. A. Antao, Arthur J. Brodersen	ARCHGEN: Automated synthesis of analog systems.	IEEE Trans. Very Large Scale Integr. Syst.	1995	DBLP DOI BibTeX RDF
37	Binlin Guo, Jiarong Tong	A SC-based novel configurable analog cell.	FPGA	2003	DBLP DOI BibTeX RDF
35	Chandramouli Visweswariah, Rakesh Chadha, Chin-Fu Chen	Model Development and Verification for High Level Analog Blocks.	DAC	1988	DBLP BibTeX RDF
34	Junwei Hou, William H. Kao, Abhijit Chatterjee	A novel concurrent fault simulation method for mixed-signal circuits.	ISCAS (2)	1999	DBLP DOI BibTeX RDF
34	Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk, Kai-Pui Lam	A Hybrid Analog-Digital Routing Network for NoC Dynamic Routing.	NOCS	2007	DBLP DOI BibTeX RDF
33	Alex Doboli, Ranga Vemuri	Behavioral modeling for high-level synthesis of analog and mixed-signal systems from VHDL-AMS.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
32	C. K. Yuen	Negabinary A/D Conversion.	IEEE Trans. Computers	1980	DBLP DOI BibTeX RDF	negabinary analog-digital conversion, Analog-digital conversion
31	G. Mulliken, Farhan Adil, Gert Cauwenberghs, Roman Genov	Delta-sigma algorithmic analog-to-digital conversion.	ISCAS (4)	2002	DBLP DOI BibTeX RDF
30	Resve A. Saleh, Brian A. A. Antao, Jaidip Singh	Multilevel and mixed-domain simulation of analog circuits and systems.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
30	Osamu Nomura, Takashi Morie	Projection-Field-Type VLSI Convolutional Neural Networks Using Merged/Mixed Analog-Digital Approach.	ICONIP (1)	2007	DBLP DOI BibTeX RDF
30	A. William Stoffel	An Agent Based Hybrid Analog-Digital Robotic Sensor Web Meta-system.	WRAC	2005	DBLP DOI BibTeX RDF
30	Mattias Duppils, Christer Svensson	Low power mixed analog-digital signal processing.	ISLPED	2000	DBLP DOI BibTeX RDF
29	Ashkan Olyaei, Roman Genov	Algorithmic Delta-Sigma-modulated FIR filter.	ISCAS	2006	DBLP DOI BibTeX RDF
27	Ying Song, Yu Gong, Sen M. Kuo	A robust hybrid feedback active noise cancellation headset.	IEEE Trans. Speech Audio Process.	2005	DBLP DOI BibTeX RDF
27	Yuzo Hirai	Recent VLSI neural networks in Japan.	J. VLSI Signal Process.	1993	DBLP DOI BibTeX RDF
26	Keisuke Korekado, Takashi Morie, Osamu Nomura, Hiroshi Ando, Teppei Nakano, Masakazu Matsugu, Atsushi Iwata	A Convolutional Neural Network VLSI for Image Recognition Using Merged/Mixed Analog-Digital Architecture.	KES	2003	DBLP DOI BibTeX RDF
25	Eugenio Culurciello, Andreas G. Andreou	An 8-bit, 1mW successive approximation ADC in SOI CMOS.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
25	Gabriella Trucco, Giorgio Boselli, Valentino Liberali	A Study of Crosstalk Through Bonding and Package Parasitics in CMOS Mixed Analog-Digital Circuits.	PATMOS	2004	DBLP DOI BibTeX RDF
25	Cesare Alippi, Marco Stellini	High level accuracy loss estimates for a class of analog/digital systems.	ISCAS (4)	2003	DBLP DOI BibTeX RDF
25	Tetsuya Asai, Masato Koutani, Yoshihito Amemiya	An Analog-Digital Hybrid CMOS Circuit for Two-Dimensional Motion Detection with Correlation Neural Networks.	IJCNN (3)	2000	DBLP DOI BibTeX RDF
25	Johan Verfaillie, Didier Haspeslagh	A general purpose design-for-test methodology at the analog-digital boundary of mixed-signal VLSI.	J. Electron. Test.	1996	DBLP DOI BibTeX RDF	mixed-signal DFT, mixed-signal boundary scan, modular mixed-signal test
25	Paul Chow, P. Glenn Gulak	A Field-Programmable Mixed-Analog-Digital Array.	FPGA	1995	DBLP DOI BibTeX RDF
25	W. E. Mattis	A Hybrid Architecture for Neurocomputing (Abstract).	ACM Conference on Computer Science	1990	DBLP DOI BibTeX RDF
24	Sameer R. Sonkusale, Jan Van der Spiegel, K. Nagaraj	Background digital error correction technique for pipelined analog-digital converters.	ISCAS (1)	2001	DBLP DOI BibTeX RDF
23	Sri Chandra	Driving Analog Mixed Signal Verification through Verilog-AMS.	VLSI Design	2008	DBLP DOI BibTeX RDF
23	Alex Doboli, Ranga Vemuri	A Functional Specification Notation for Co-Design of Mixed Analog-Digital Systems.	DATE	2002	DBLP DOI BibTeX RDF
23	Santina Rocchi, Valerio Vignoli	A chaotic CMOS true-random analog/digital white noise generator.	ISCAS (5)	1999	DBLP DOI BibTeX RDF
22	Yu Liu, Thanyapat Sakunkonchak, Satoshi Komatsu, Masahiro Fujita	System level design language extensions for timed/untimed digital-analog combined system design.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	AMS extension, timed/untimed, synchronization, system level design, mixed-signal
22	Qin Li, Li Cai, Gang Wu	Digital-analog and analog-digital converters based on single-electron and MOS transistors.	ICCA	2010	DBLP DOI BibTeX RDF
22	Carl G. Blanyer, H. Mori	Analog, digital, and combined analog-digital computers for real-time simulation.	IRE-ACM-AIEE Computer Conference (Eastern)	1957	DBLP DOI BibTeX RDF
20	Guillermo Zatorre, Nicolás J. Medrano-Marqués, Santiago Celma, Bonifacio Martín-del-Brío, Antonio Bono-Nuez	Smart Sensing with Adaptive Analog Circuits.	IWANN	2005	DBLP DOI BibTeX RDF
20	Pierluigi Daglio, Carlo Roma	A Fully Qualified Top-Down and Bottom-Up Mixed-Signal Design Flow for Non Volatile Memories Technologies.	DATE	2003	DBLP DOI BibTeX RDF
20	Nabil Ouerhani, Heinz Hügli, Pierre-Yves Burgi, Pierre-François Ruedi	A Real Time Implementation of the Saliency-Based Model of Visual Attention on a SIMD Architecture.	DAGM-Symposium	2002	DBLP DOI BibTeX RDF
20	Timo Koskinen, Peter Y. K. Cheung	Hierarchical tolerance analysis using statistical behavioral models.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
20	Ji-Chien Lee, Bing J. Sheu, Rama Chellappa	A VLSI neuroprocessor for image restoration using analog computing-based systolic architecture.	J. VLSI Signal Process.	1993	DBLP DOI BibTeX RDF
19	Hocheol Shin, Yunmok Son, Young-Seok Park, Yujin Kwon, Yongdae Kim	Sampling Race: Bypassing Timing-Based Analog Active Sensor Spoofing Detection on Analog-Digital Systems.	WOOT	2016	DBLP BibTeX RDF
19	Peter Schwarz	Wiederverwendung von analog-digitalen Schaltungen (Reuse of Mixed Analog-Digital Circuits).	Informationstechnik Tech. Inform.	2002	DBLP DOI BibTeX RDF
19	Hiroshi Sagesaka, Hisashi Irii, Hideki Asai	SPADE : analog/digital mixed signal simulator with analog hardware description language.	ICECS	1998	DBLP DOI BibTeX RDF
19	Dominique Rodriguez	Description et simulation mixte analogique-numérique: analyse de VHDL analogique, réalisation d'un simulateur mixte. (Mixed analog-digital description and simulation: Study of analog VHDL. Implementation of a mixed simulator).		1994	RDF
19	Umakanta Choudhury, Alberto L. Sangiovanni-Vincentelli	Constraint-based channel routing for analog and mixed analog/digital circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
19	Umakanta Choudhury, Alberto L. Sangiovanni-Vincentelli	Constraint-Based Channel Routing for Analog and Mixed Analog/Digital Circuits.	ICCAD	1990	DBLP DOI BibTeX RDF
19	David J. Chen, Ji-Chien Lee, Bing J. Sheu	SLAM: a smart analog module layout generator for mixed analog-digital VLSI design.	ICCD	1989	DBLP DOI BibTeX RDF
18	Hirotsugu Okuno, Tetsuya Yagi	A Robot Vision System for Collision Avoidance Using a Bio-inspired Algorithm.	ICONIP (2)	2007	DBLP DOI BibTeX RDF
18	John A. Nestor, David A. Rich	Integrating Digital, Analog, and Mixed-Signal Design in an Undergraduate ECE Curriculum.	MSE	2003	DBLP DOI BibTeX RDF
18	Tetsuya Yagi, Kazuhiro Shimonomura	Silicon primary visual cortex designed with a mixed analog-digital architecture.	IJCNN	2007	DBLP DOI BibTeX RDF
18	Dietmar Schroeder	Adaptive Low-Power Analog/Digital Converters for Wireless Sensor Networks.	WISES	2005	DBLP DOI BibTeX RDF
18	Alexandre Schmid, D. Bowler, R. Baumgartner, Yusuf Leblebici	A novel analog-digital flash converter architecture based on capacitive threshold gates.	ISCAS (2)	1999	DBLP DOI BibTeX RDF
18	H.-C. Chow, W.-S. Feng, James B. Kuo	An improved analytical short-channel MOSFET model valid in all regions of operating for analog/digital circuit simulation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1992	DBLP DOI BibTeX RDF
16	Ludovic Alvado, Sylvain Saïghi, Jean Tomas, Sylvie Renaud-Le Masson	An Exponential-Decay Synapse Integrated Circuit for Bio-inspired Neural Networks.	IWANN (1)	2003	DBLP DOI BibTeX RDF
16	Fabio Ancona, Giorgio Oddone, Stefano Rovetta, Gianni Uneddu, Rodolfo Zunino	VLSI Architectures for Programmable Sorting of Analog Quantities with Multiple-Chip Support.	Great Lakes Symposium on VLSI	1997	DBLP DOI BibTeX RDF
16	Esa Korhonen, Juha Kostamovaara	Memory Optimized Two-Stimuli INL Test Method for DAC-ADC Pairs.	ETS	2011	DBLP DOI BibTeX RDF	didital-analog conversion, algorithms, testing, histograms, linearity, analog-digital conversion
16	Moshe Mishali, Yonina C. Eldar	Xampling: Analog Data Compression.	DCC	2010	DBLP DOI BibTeX RDF	analog processing circuits, data conversion, sampling methods, analog digital conversion
16	Anirudh Devgan, Bulent Basaran, David Colleran, Mar Hershenson	Accelerated design of analog, mixed-signal circuits in Titan.	ISPD	2009	DBLP DOI BibTeX RDF	analog circuit layout, analog/digital, custom design, layout, physical design, analog circuits, mixed-signal circuits
16	Shalabh Goyal, Abhijit Chatterjee	Linearity Testing of A/D Converters Using Selective Code Measurement.	J. Electron. Test.	2008	DBLP DOI BibTeX RDF	Testing, Non-linearity, Manufacturing test, Analog-digital conversion
16	Lukas Fujcik, Radimir Vrba, Roman Prokop, Jaromir Hubalek, Pavel Steffan, Hana Hornochova	A Microconductometer Utilizing Bipolar Pulse Method for Electro-Chemical Sensors.	ICONS	2008	DBLP DOI BibTeX RDF	mixed analog-digital integrated circuits
16	Samiran Halder, Swapna Banerjee, Arindrajit Ghosh, Ravi Sankar Prasad, Anirban Chatterjee, Sanjoy Kumar Dey	A 10-Bit 80-MSPS 2.5-V 27.65-mW 0.185-mm2 Segmented Current Steering CMOS DAC.	VLSI Design	2005	DBLP DOI BibTeX RDF	MOS Analog Circuits, Digital to Analog Conversion, Mixed Analog -Digital Integrated Circuits, Low Power
16	Luciano Lavagno, Begoña Pino, Leonardo Maria Reyneri, A. Serra	A Simulink(c)-Based Approach to System Level Design and Architecture Selection.	EUROMICRO	2000	DBLP DOI BibTeX RDF	mixed analog/digital, embedded systems, Low-power, system-on-a-chip, Hardware-Software codesign
16	Andrea Boni, Andrea Pierazzi	Yield Enhancement by Multi-level Linear Modeling of Non-Idealities in an Interpolated Flash ADCs.	DFT	1998	DBLP DOI BibTeX RDF	BiCMOS analog integrated circuits, Monte Carlo methods, Yield optimization, Analog-digital conversion
16	Andrzej Materka, Michal Strzelecki	Parametric testing of mixed-signal circuits by ANN processing of transient responses.	J. Electron. Test.	1996	DBLP DOI BibTeX RDF	mixed analog-digital integrated circuits, transient power, supply current, neural networks, integrated circuit testing
16	Mehdi Ehsanian, Bozena Kaminska, Karim Arabi	A new digital test approach for analog-to-digital converter testing.	VTS	1996	DBLP DOI BibTeX RDF	digital test approach, analog/digital converter testing, BIST circuitry, offset error, gain error, DNL, INL, area overhead reduction, medium resolution ADC, high resolution pipelined ADC, A/D converter testing, differential nonlinearity, integral nonlinearity, 1.5 micron, VLSI, built-in self test, built-in self-test, integrated circuit testing, CMOS integrated circuits, CMOS technology, analogue-digital conversion
16	Roger L. Boyell	Real-time simulation of mapping radar.	Commun. ACM	1962	DBLP DOI BibTeX RDF	radar simulation, real-time analog/digital computing, real-time simulation at megacycle rates, hybrid computers, terrain mapping
16	Scott Melvin, Manmeet S. Goldy, Jacek Ilow	Antenna Load Mismatch Effects in EER-Based Transmitters for Digital Audio Broadcasting.	CNSR	2007	DBLP DOI BibTeX RDF
16	Zeynep Toprak Deniz, Yusuf Leblebici	Design and realization of a modular 200 MSample/s 12-bit pipelined A/D converter block using deep-submicron digital CMOS technology.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
16	Jan Craninckx, Stéphane Donnay	4G terminals: how are we going to design them?	DAC	2003	DBLP DOI BibTeX RDF	4th generation, radio front-end, telecommunication, wireless systems
16	Ingemar J. Cox, Joe Kilian, Frank Thomson Leighton, Talal Shamoon	Secure spread spectrum watermarking for multimedia.	IEEE Trans. Image Process.	1997	DBLP DOI BibTeX RDF
16	Robert M. Gray, Richard A. Olshen, D. Ikeda, Pamela C. Cosman, Sharon M. Perlmutter, Cheryl L. Nash, Keren Perlmutter	Evaluating quality and utility in digital mammography.	ICIP	1995	DBLP DOI BibTeX RDF	digital mammography utility, digital mammography quality evaluation, scientists, insurance companies, lawyers, computer-aided diagnostic methodology, clinical experiments, data compression, image enhancement, medical image processing, engineers, regulators, reviews, quality control, protocols design, administrators, medical diagnostic imaging, lossy compression, diagnostic radiography, patients, analogue-digital conversion, analog-to-digital conversion
15	Alireza Morsali, Benoît Champagne 0001	Achieving Fully-Digital Performance by Hybrid Analog/Digital Beamforming in Wide-Band Massive-Mimo Systems.	ICASSP	2020	DBLP DOI BibTeX RDF
15	Wenjing Deng, Wei Zhou, Xiangming Sun, Chaosong Gao, Di Guo, Guangming Huang	A high-precision coarse-fine time-to-digital converter with the analog-digital hybrid interpolation.	IEICE Electron. Express	2019	DBLP DOI BibTeX RDF
15	Ang Li 0003, Christos Masouros	Energy-Efficient SWIPT: From Fully Digital to Hybrid Analog-Digital Beamforming.	IEEE Trans. Veh. Technol.	2018	DBLP DOI BibTeX RDF
15	Seok Min Jung, Janet Meiling Roveda	A low jitter digital phase-locked loop with a hybrid analog/digital PI control.	NEWCAS	2015	DBLP DOI BibTeX RDF
15	Tomohiro Taniguchi, Toshihito Fujiwara, Hidekazu Shimizu, Ryota Shiina, Toshiaki Shitaba, Yasunobu Kasahara, Hisao Yoshinaga, Tomoki Sugawa	Digital baseband signal broadcasting of ultra-high definition video over analog/digital hybrid network.	APSITT	2015	DBLP DOI BibTeX RDF
15	Tadilo Endeshaw Bogale, Long Bao Le	Beamforming for multiuser massive MIMO systems: Digital versus hybrid analog-digital.	GLOBECOM	2014	DBLP DOI BibTeX RDF
15	Jaeha Kim, Sigang Ryu, Byoung-Joo Yoo, Hanseok Kim, Yunju Choi, Deog-Kyoon Jeong	A model-first design and verification flow for analog-digital convergence systems: A high-speed receiver example in digital TVs.	ISCAS	2012	DBLP DOI BibTeX RDF
15	Michael H. Perrott, Yunteng Huang, Rex T. Baird, Bruno W. Garlepp, Douglas Pastorello, Eric T. King, Qicheng Yu, Dan B. Kasha, Philip Steiner, Ligang Zhang, Jerrell P. Hein, Bruce Del Signore	A 2.5-Gb/s Multi-Rate 0.25-$\mu$m CMOS Clock and Data Recovery Circuit Utilizing a Hybrid Analog/Digital Loop Filter and All-Digital Referenceless Frequency Acquisition.	IEEE J. Solid State Circuits	2006	DBLP DOI BibTeX RDF
15	Per Löwenborg, Håkan Johansson, Lars Wanhammar	Two-channel digital and hybrid analog/digital multirate filter banks with very low-complexity analysis or synthesis filters.	IEEE Trans. Circuits Syst. II Express Briefs	2003	DBLP DOI BibTeX RDF
15	R. T. Lara Sáez, Maher Kayal, Michel J. Declercq, M. C. Schneider	Digital circuit techniques for mixed analog/digital circuits applications.	ICECS	1996	DBLP DOI BibTeX RDF
15	Donald Thelen, John MacDonald	Simulating mixed analog-digital circuits on a digital simulator.	ICCAD	1988	DBLP DOI BibTeX RDF
14	Peng Wang, Xun Zhang, Dongming Jin	A Novel Multiplier for Achieving the Programmability of Cellular Neural Network.	ICONIP (3)	2006	DBLP DOI BibTeX RDF
14	Gabriella Trucco, Giorgio Boselli, Valentino Liberali	An approach to computer simulation of bonding and package crosstalk in mixed-signal CMOS ICs.	SBCCI	2004	DBLP DOI BibTeX RDF	crosstalk, mixed-signal ICs
14	Sule Ozev, Ismet Bayraktaroglu, Alex Orailoglu	Test Synthesis for Mixed-Signal SOC Paths.	DATE	2000	DBLP DOI BibTeX RDF
14	Alex Yoondong Park, Jim-Shih Liaw, Theodore W. Berger, Bing J. Sheu	Compact VLSI Neural Network Circuit with High-Capacity Dynamic Synapses.	IJCNN (4)	2000	DBLP DOI BibTeX RDF
14	Takeshi Kamio, Shinichiro Tanaka, Mititada Morisue	Backpropagation Algorithm for Logic Oriented Neural Networks.	IJCNN (2)	2000	DBLP DOI BibTeX RDF
14	Tadashi Shibata	Right brain computing hardware: a psychological brain model on silicon.	KES (3)	1998	DBLP DOI BibTeX RDF
14	Stephen P. DeWeerth, Girish N. Patel, Mario F. Simoni, David E. Schimmel, Ronald L. Calabrese	A VLSI Architecture for Modeling Intersegmental Coordination.	ARVLSI	1997	DBLP DOI BibTeX RDF
13	R. Xue, Q. Xu, Ka-Fai Chang, Kam-Weng Tam	A new method of an IF I/Q demodulator for narrowband signals.	ISCAS (4)	2005	DBLP DOI BibTeX RDF
12	Adel Daouzli, Sylvain Saïghi, Michelle Rudolph, Alain Destexhe, Sylvie Renaud	Convergence in an Adaptive Neural Network: The Influence of Noise Inputs Correlation.	IWANN (1)	2009	DBLP DOI BibTeX RDF	Neuromorphic Engineering, Silicon Neurons, Hodgkin-Huxley Model, STDP
12	Giacomo Indiveri, Elisabetta Chicca, Rodney J. Douglas	A VLSI array of low-power spiking neurons and bistable synapses with spike-timing dependent plasticity.	IEEE Trans. Neural Networks	2006	DBLP DOI BibTeX RDF
12	Yukitoshi Sanada, Masaaki Ikehara	Decorrelating compensation scheme for coefficient errors of a filter bank parallel A/D converter.	IEEE Trans. Wirel. Commun.	2004	DBLP DOI BibTeX RDF
12	Yoshihiko Horio, Takahide Okuno, Koji Mori	Switched-Capacitor Large-Scale Chaotic Neuro-Computer Prototype and Chaotic Search Dynamics.	KES	2004	DBLP DOI BibTeX RDF
12	Vincent Douence, Sylvie Renaud-Le Masson, Sylvain Saïghi, Gwendal Le Masson	A Field-Programmable Conductance Array IC for Biological Neurons Modeling.	IWANN (2)	2001	DBLP DOI BibTeX RDF
11	Yi-Feng Ye, Yi-Tong Wang, Jia-Hao Feng, Lin-Sheng Wu, Liang-Feng Qiu, Junfa Mao	A Compact Ka-Band Hybrid Analog/Digital Phase Shifter With GaAs Technology.	IEEE Trans. Circuits Syst. II Express Briefs	2024	DBLP DOI BibTeX RDF