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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 2 occurrences of 2 keywords
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Results
Found 21 publication records. Showing 21 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
27 | Rabiul Islam, Adam Brand, Dave Lippincott |
Low power SRAM techniques for handheld products. |
ISLPED |
2005 |
DBLP DOI BibTeX RDF |
back-bias, bitcell, memory, leakage |
17 | Adrian Kneip, David Bol |
A 7T-NDR Dual-Supply 28-nm FD-SOI Ultra-Low Power SRAM With 0.23-nW/kB Sleep Retention and 0.8 pJ/32b Access at 64 MHz With Forward Back Bias. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2023 |
DBLP DOI BibTeX RDF |
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17 | Maxime Schramme, David Bol |
UFBBR: A Unified Frequency and Back-Bias Regulation Unit for Ultralow-Power Microcontrollers in 28-nm FDSOI. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2023 |
DBLP DOI BibTeX RDF |
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17 | N. Bhattacharjee, Maximilian Reuter, Klaus Hofmann, Thomas Mikolajick, Jens Trommer |
Single Transistor Analog Building Blocks: Exploiting Back-Bias Reconfigurable Devices. |
NEWCAS |
2023 |
DBLP DOI BibTeX RDF |
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17 | Xinze Li, Yuxuan Wu, Qiao Teng, Ying Sun, Xiao Gong, Guillaume Besnard, Christophe Maleville, Olivier Weber, Rui Zhang, Bing Chen, Dawei Gao, Ran Cheng |
Investigation of Random Telegraph Noise in Advanced Silicon-On-Insulator N-FETs: The Impact of Back Bias, Strain, and Hot Carrier Stress. |
ICICDT |
2023 |
DBLP DOI BibTeX RDF |
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17 | Maxime Schramme, Léopold Van Brandt, Denis Flandre, David Bol |
Comprehensive Analytical Comparison of Ring Oscillators in FDSOI Technology: Current Starving Versus Back-Bias Control. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2022 |
DBLP DOI BibTeX RDF |
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17 | Rémi Dekimpe, Maxime Schramme, Martin Lefebvre 0002, Adrian Kneip, Roghayeh Saeidi, Mathieu Xhonneux, Ludovic Moreau, Marco Gonzalez, Thibault Pirson, David Bol |
SleepRider: a 5.5μW/MHz Cortex-M4 MCU in 28nm FD-SOI with ULP SRAM, Biomedical AFE and Fully-Integrated Power, Clock and Back-Bias Management. |
VLSI Circuits |
2021 |
DBLP DOI BibTeX RDF |
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17 | Ming-Yu Chang, Po-Yu Chao, Meng-Hsueh Chiang |
Back-Bias Modulated UTBB SOI for System-on-Chip I/O Cells. |
ISQED |
2021 |
DBLP DOI BibTeX RDF |
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17 | Luca Pirro, Alban Zaka, Olaf Zimmerhackl, T. Hermann, Michael Otto, E. M. Bazizi, Jan Hoentschel, X. Li, R. Taylor |
Low-Frequency Noise Reduction in 22FDX®: Impact of Device Geometry and Back Bias. |
IRPS |
2019 |
DBLP DOI BibTeX RDF |
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17 | Somayeh Hossein Zadeh, Trond Ytterdal, Snorre Aunet |
Exploring optimal back bias voltages for ultra low voltage CMOS digital Circuits in 22 nm FDSOI Technology. |
NORCAS |
2019 |
DBLP DOI BibTeX RDF |
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17 | David Bol, Maxime Schramme, Ludovic Moreau, Thomas Haine, Pengcheng Xu 0002, Charlotte Frenkel, Remi Dekimpe, François Stas, Denis Flandre |
A 40-to-80MHz Sub-4μW/MHz ULV Cortex-M0 MCU SoC in 28nm FDSOI With Dual-Loop Adaptive Back-Bias Generator for 20μs Wake-Up From Deep Fully Retentive Sleep Mode. |
ISSCC |
2019 |
DBLP DOI BibTeX RDF |
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17 | Arif Siddiqi, Navneet Jain, Mahbub Rashed |
Back-bias generator for post-fabrication threshold voltage tuning applications in 22nm FD-SOI process. |
ISQED |
2018 |
DBLP DOI BibTeX RDF |
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17 | Daniele Jahier Pagliari, Yves Durand, David Coriat, Anca Molnos, Edith Beigné, Enrico Macii, Massimo Poncino |
A methodology for the design of dynamic accuracy operators by runtime back bias. |
DATE |
2017 |
DBLP DOI BibTeX RDF |
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17 | Thomas Haine, Quoc-Khoi Nguyen, François Stas, Ludovic Moreau, Denis Flandre, David Bol |
An 80-MHz 0.4V ULV SRAM macro in 28nm FDSOI achieving 28-fJ/bit access energy with a ULP bitcell and on-chip adaptive back bias generation. |
ESSCIRC |
2017 |
DBLP DOI BibTeX RDF |
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17 | Sebastien Bernard, Marc Belleville, Alexandre Valentian, Jean-Didier Legat, David Bol |
Experimental analysis of flip-flops minimum operating voltage in 28nm FDSOI and the impact of back bias and temperature. |
PATMOS |
2014 |
DBLP DOI BibTeX RDF |
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17 | Michael Ortner, Michael Seger, Marcelo Ribeiro, Armin Satz |
Signal Analysis in Back Bias Speed Sensor Systems. |
EMS |
2013 |
DBLP DOI BibTeX RDF |
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17 | Guillaume Moritz, Bastien Giraud, Jean-Philippe Noel, David Turgis, Anuj Grover |
Optimization of a voltage sense amplifier operating in ultra wide voltage range with back bias design techniques in 28nm UTBB FD-SOI technology. |
ICICDT |
2013 |
DBLP DOI BibTeX RDF |
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17 | Yasuhiko Tsukikawa, Takeshi Kajimoto, Yasuhiko Okasaka, Yoshikazu Morooka, Kiyohiro Furutani, Hiroshi Miyamoto, Hideyuki Ozaki |
An efficient back-bias generator with hybrid pumping circuit for 1.5-V DRAMs. |
IEEE J. Solid State Circuits |
1994 |
DBLP DOI BibTeX RDF |
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9 | Shuichi Kunie, Takefumi Hiraga, Tatsuya Tokue, Sunao Torii, Taku Ohsawa |
Low power architecture and design techniques for mobile handset LSI MedityTM M2. |
ASP-DAC |
2008 |
DBLP DOI BibTeX RDF |
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9 | Arnaud Turier, Lotfi Ben Ammar, Amara Amara |
Static power consumption management in CMOS memories. |
ISCAS (4) |
2001 |
DBLP DOI BibTeX RDF |
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9 | Vjekoslav Svilan, Masataka Matsui, James B. Burr |
Energy-efficient 32 × 32-bit multiplier in tunable near-zero threshold CMOS. |
ISLPED |
2000 |
DBLP DOI BibTeX RDF |
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Displaying result #1 - #21 of 21 (100 per page; Change: )
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