Search results for "bundled-data"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
56	Sunan Tugsinavisut, Suwicha Jirayucharoensak, Peter A. Beerel	An asynchronous pipeline comparisons with application to DCT matrix-vector multiplication.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
50	Sunan Tugsinavisut, Youpyo Hong, Daewook Kim, Kyeounsoo Kim, Peter A. Beerel	Efficient asynchronous bundled-data pipelines for DCT matrix-vector multiplication.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
49	Masashi Imai, Takashi Nanya	A Novel Design Method for Asynchronous Bundled-data Transfer Circuits Considering Characteristics of Delay Variations.	ASYNC	2006	DBLP DOI BibTeX RDF
37	David A. Kearney, Neil W. Bergmann	Bundled Data Asynchronous Multipliers with Data Dependent Computation Times.	ASYNC	1997	DBLP DOI BibTeX RDF	asynchronous logic data dependent performance multiplier
36	Takao Konishi, Naohiro Hamada, Hiroshi Saito	A Control Circuit Synthesis Method for Asynchronous Circuits in Bundled-Data Implementation.	CIT	2007	DBLP DOI BibTeX RDF
35	Hiroshi Saito, Nattha Jindapetch, Tomohiro Yoneda, Chris J. Myers, Takashi Nanya	ILP-based Scheduling for Asynchronous Circuits in Bundled-Data Implementation.	CIT	2006	DBLP DOI BibTeX RDF
31	Mohamed Kawokgy, C. André T. Salama	Low-power asynchronous viterbi decoder for wireless applications.	ISLPED	2004	DBLP DOI BibTeX RDF	bundled-data, four-phase, low-power, synchronous, wireless, VHDL, digital signal processing, asynchronous, register transfer level, viterbi algorithm, speed-independent, handshaking protocol
29	Yinghua Li, Alex Kondratyev, Robert K. Brayton	Gaining Predictability and Noise Immunity in Global Interconnects.	ACSD	2005	DBLP DOI BibTeX RDF
28	D. J. Kinniment, Alexandre Yakovlev, Fei Xia, B. Gao	Towards Asynchronous A-D Conversion.	ASYNC	1998	DBLP DOI BibTeX RDF	analogue to digital conversion, synchronisers, asynchronous circuits, arbitration, signal transition graphs, metastability
23	Norman Kluge, Ralf Wollowski	Data path optimisation and delay matching for asynchronous bundled-data balsa circuits.	ICCAD	2017	DBLP DOI BibTeX RDF
21	Senri Yoshikawa, Shuji Sannomiya, Makoto Iwata, Akira Sato, Hiroaki Nishikawa	EDA-oriented FPGA Circuit Design Method for Four-phase Bundled-data Circular Self-timed Pipeline.	J. Inf. Process.	2023	DBLP DOI BibTeX RDF
21	Carsten Nielsen, Zhe Su, Giacomo Indiveri	Yak: An Asynchronous Bundled Data Pipeline Description Language.	CoRR	2023	DBLP DOI BibTeX RDF
21	Carsten Nielsen, Zhe Su, Giacomo Indiveri	Yak: An Asynchronous Bundled Data Pipeline Description Language.	ASYNC	2023	DBLP DOI BibTeX RDF
21	Pallavi Srivastava, Edwin Chung	An Asynchronous Bundled-Data Barrel Shifter Design That Incorporates a Deterministic Completion Detection Technique.	IEEE Trans. Circuits Syst. II Express Briefs	2022	DBLP DOI BibTeX RDF
21	Yuhao Huang, Shanlin Xiao, Zhiyu Li, Zhiyi Yu	An Asynchronous Bundled-Data Template With Current Sensing Completion Detection Technique.	IEEE Trans. Circuits Syst. II Express Briefs	2022	DBLP DOI BibTeX RDF
21	Ruimin Zhu, Zeyang Xu, Yuhao Huang, Shanlin Xiao, Zhiyi Yu	DFT Architecture for Click-Based Bundled-Data Asynchronous Circuits.	ICTA	2022	DBLP DOI BibTeX RDF
21	Sai Aparna Aketi, Smriti Gupta, Huimei Cheng, Joycee Mekie, Peter A. Beerel	SERAD: Soft Error Resilient Asynchronous Design using a Bundled Data Protocol.	CoRR	2020	DBLP BibTeX RDF
21	Sai Aparna Aketi, Smriti Gupta, Huimei Cheng, Joycee Mekie, Peter A. Beerel	SERAD: Soft Error Resilient Asynchronous Design Using a Bundled Data Protocol.	IEEE Trans. Circuits Syst. I Fundam. Theory Appl.	2020	DBLP DOI BibTeX RDF
21	Felipe A. Kuentzer, Milos Krstic	Soft Error Detection and Correction Architecture for Asynchronous Bundled Data Designs.	IEEE Trans. Circuits Syst.	2020	DBLP DOI BibTeX RDF
21	Yoan Decoudu, Jean Simatic, Katell Morin-Allory, Laurent Fesquet	From High-Level Synthesis to Bundled-Data Circuits.	SAMOS	2020	DBLP DOI BibTeX RDF
21	Ricardo Aquino Guazzelli, Laurent Fesquet	At-speed DfT Architecture for Bundled-data Design.	ITC	2020	DBLP DOI BibTeX RDF
21	Yang Zhang 0014, Ji Li 0006, Huimei Cheng, Haipeng Zha, Jeffrey Draper, Peter A. Beerel	Yield modelling and analysis of bundled data and ring-oscillator based designs.	IET Comput. Digit. Tech.	2019	DBLP DOI BibTeX RDF
21	Grégoire Gimenez, Jean Simatic, Laurent Fesquet	From Signal Transition Graphs to Timing Closure: Application to Bundled-Data Circuits.	ASYNC	2019	DBLP DOI BibTeX RDF
21	Kshitij Bhardwaj, Paolo Mantovani, Luca P. Carloni, Steven M. Nowick	Towards a Complete Methodology for Synthesizing Bundled-Data Asynchronous Circuits on FPGAs.	ISLPED	2019	DBLP DOI BibTeX RDF
21	Maryem Benyoussef, Claude Thibeault, Yvon Savaria	A Prediction Model for Implementing DVS in Single-Rail Bundled-Data Handshake-Free Asynchronous Circuits.	ISCAS	2019	DBLP DOI BibTeX RDF
21	Masashi Imai, Shinichiro Akasaka, Tomohiro Yoneda	Novel Delay Elements for Bundled-Data Transfer Circuits Based on Two-Phase Handshaking Protocols.	ASYNC	2018	DBLP DOI BibTeX RDF
21	Gregoire Gimenez, Abdelkarim Cherkaoui, Guillaume Cogniard, Laurent Fesquet	Static Timing Analysis of Asynchronous Bundled-Data Circuits.	ASYNC	2018	DBLP DOI BibTeX RDF
21	Yang Zhang 0014, Huimei Cheng, Dake Chen, Huayu Fu, Shikhanshu Agarwal, Mark Lin, Peter A. Beerel	Challenges in Building an Open-Source Flow from RTL to Bundled-Data Design.	ASYNC	2018	DBLP DOI BibTeX RDF
21	Anping He, Guangbo Feng, Jilin Zhang, Pengfei Li, Yong Hei, Hong Chen 0002	Click-Based Asynchronous Mesh Network with Bounded Bundled Data.	ICPP	2018	DBLP DOI BibTeX RDF
21	Patrick Russell, Jens Döge, Christoph Hoppe, Thomas B. Preußer, Peter Reichel, Peter Schneider	Implementation of an asynchronous bundled-data router for a GALS NoC in the context of a VSoC.	DDECS	2017	DBLP DOI BibTeX RDF
21	Yang Zhang 0014, Haipeng Zha, Vaishnavi Sahir, Huimei Cheng, Peter A. Beerel	Test Margin and Yield in Bundled Data and Ring-Oscillator Based Designs.	ASYNC	2017	DBLP DOI BibTeX RDF
21	Gabriele Miorandi, Marco Balboni, Steven M. Nowick, Davide Bertozzi	Accurate Assessment of Bundled-Data Asynchronous NoCs Enabled by a Predictable and Efficient Hierarchical Synthesis Flow.	ASYNC	2017	DBLP DOI BibTeX RDF
21	Jukiya Furushima, Masamitsu Nakajima, Hiroshi Saito	Design of an Asynchronous Processor with Bundled-data Implementation on a Commercial Field Programmable Gate Array.	Informatica (Slovenia)	2016	DBLP BibTeX RDF
21	Ajay Singhvi, Matheus T. Moreira, Ramy N. Tadros, Ney Laert Vilar Calazans, Peter A. Beerel	A Fine-Grain, Uniform, Energy-Efficient Delay Element for 2-Phase Bundled-Data Circuits.	ACM J. Emerg. Technol. Comput. Syst.	2016	DBLP DOI BibTeX RDF
21	Gabriele Miorandi, Alberto Celin, Michele Favalli, Davide Bertozzi	A built-in self-testing framework for asynchronous bundled-data NoC switches resilient to delay variations.	NOCS	2016	DBLP DOI BibTeX RDF
21	Dylan Hand, Austin Katrin, William Koven	Adding Conditionality to Resilient Bundled-Data Designs.	ASYNC	2016	DBLP DOI BibTeX RDF
21	Norman Kluge, Ralf Wollowski	Optimising Bundled-Data Balsa Circuits.	ASYNC	2016	DBLP DOI BibTeX RDF
21	Jean Simatic, Abdelkarim Cherkaoui, Rodrigo Possamai Bastos, Laurent Fesquet	New asynchronous protocols for enhancing area and throughput in bundled-data pipelines.	SBCCI	2016	DBLP DOI BibTeX RDF
21	Shuichi Sato, Satoshi Ohtake	A Delay Measurement Mechanism for Asynchronous Circuits of Bundled-Data Model.	DDECS	2015	DBLP DOI BibTeX RDF
21	Matheus Gibiluka, Matheus Trevisan Moreira, Ney Laert Vilar Calazans	A Bundled-Data Asynchronous Circuit Synthesis Flow Using a Commercial EDA Framework.	DSD	2015	DBLP DOI BibTeX RDF
21	Peter A. Beerel, Ney Laert Vilar Calazans	A path towards average-case silicon via asynchronous resilient bundled-data design.	ECCTD	2015	DBLP DOI BibTeX RDF
21	Matheus Gibiluka, Matheus Trevisan Moreira, Fernando Gehm Moraes, Ney Laert Vilar Calazans	BAT-Hermes: A transition-signaling bundled-data NoC router.	LASCAS	2015	DBLP DOI BibTeX RDF
21	Guilherme Heck, Leandro S. Heck, Ajay Singhvi, Matheus T. Moreira, Peter A. Beerel, Ney Laert Vilar Calazans	Analysis and Optimization of Programmable Delay Elements for 2-Phase Bundled-Data Circuits.	VLSID	2015	DBLP DOI BibTeX RDF
21	Arash Saifhashemi, Dylan Hand, Peter A. Beerel, William Koven, Hong Wang	Performance and Area Optimization of a Bundled-Data Intel Processor through Resynthesis.	ASYNC	2014	DBLP DOI BibTeX RDF
21	Keitaro Takizawa, Shunya Hosaka, Hiroshi Saito	A design support tool set for asynchronous circuits with bundled-data implementation on FPGAs.	FPL	2014	DBLP DOI BibTeX RDF
21	Minoru Iizuka, Naohiro Hamada, Hiroshi Saito	An ASIC Design Support Tool Set for Non-pipelined Asynchronous Circuits with Bundled-Data Implementation.	IEICE Trans. Electron.	2013	DBLP DOI BibTeX RDF
21	Alberto Ghiribaldi, Davide Bertozzi, Steven M. Nowick	A transition-signaling bundled data NoC switch architecture for cost-effective GALS multicore systems.	DATE	2013	DBLP DOI BibTeX RDF
21	Jian Liu, Steven M. Nowick, Mingoo Seok	Soft MOUSETRAP: A Bundled-Data Asynchronous Pipeline Scheme Tolerant to Random Variations at Ultra-Low Supply Voltages.	ASYNC	2013	DBLP DOI BibTeX RDF
21	Minoru Iizuka, Hiroshi Saito	A floorplan method for ASIC designs of asynchronous circuits with bundled-data implementation.	NEWCAS	2013	DBLP DOI BibTeX RDF
21	Naohiro Hamada, Hiroshi Saito	Integration of Behavioral Synthesis and Floorplanning for Asynchronous Circuits with Bundled-Data Implementation.	IEICE Trans. Electron.	2012	DBLP DOI BibTeX RDF
21	Soodeh Aghli Moghaddam, Siamak Mohammadi, Parviz Jabehdar Maralani	Modified bundled-data as a new protocol for NoC asynchronous links.	Microelectron. J.	2011	DBLP DOI BibTeX RDF
21	Minoru Iizuka, Naohiro Hamada, Hiroshi Saito, Ryoichi Yamaguchi, Minoru Yoshinaga	A tool set for the design of asynchronous circuits with bundled-data implementation.	ICCD	2011	DBLP DOI BibTeX RDF
21	Naohiro Hamada, Hiroshi Saito	Integration of behavioral synthesis and floorplanning for asynchronous circuits with bundled-data implementation.	ACM Great Lakes Symposium on VLSI	2011	DBLP DOI BibTeX RDF
21	Hiroshi Saito, Naohiro Hamada, Tomohiro Yoneda, Takashi Nanya	A floorplan method for asynchronous circuits with bundled-data implementation on FPGAs.	ISCAS	2010	DBLP DOI BibTeX RDF
21	Steffen Zeidler 0001, Alexandre V. Bystrov, Milos Krstic, Rolf Kraemer	On-line testing of bundled-data asynchronous handshake protocols.	IOLTS	2010	DBLP DOI BibTeX RDF
21	Naohiro Hamada, Yuki Shiga, Takao Konishi, Hiroshi Saito, Tomohiro Yoneda, Chris J. Myers, Takashi Nanya	A Behavioral Synthesis System for Asynchronous Circuits with Bundled-data Implementation.	IPSJ Trans. Syst. LSI Des. Methodol.	2009	DBLP DOI BibTeX RDF
21	Naohiro Hamada, Yuki Shiga, Hiroshi Saito, Tomohiro Yoneda, Chris J. Myers, Takashi Nanya	A behavioral synthesis method for asynchronous circuits with bundled-data implementation (Tool paper).	ACSD	2008	DBLP DOI BibTeX RDF
21	Hiroshi Saito, Naohiro Hamada, Nattha Jindapetch, Tomohiro Yoneda, Chris J. Myers, Takashi Nanya	Scheduling Methods for Asynchronous Circuits with Bundled-Data Implementations Based on the Approximation of Start Times.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2007	DBLP DOI BibTeX RDF
21	Masakazu Shimizu, Kôki Abe	A Cost-Effective Handshake Protocol and Its Implementation for Bundled-Data Asynchronous Circuits.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2006	DBLP DOI BibTeX RDF
21	Sunan Tugsinavisut, Peter A. Beerel	Control Circuit Templates for Asynchronous Bundled-Data Pipelines.	DATE	2002	DBLP DOI BibTeX RDF
21	Volker Schöber, Thomas Kiel	An Asynchronous Scan Path Concept for Micropipelines using the Bundled Data Convention.	ITC	1996	DBLP DOI BibTeX RDF
21	Per Torstein Røine	Building fast bundled data circuits with a specialized standard cell library.	ASYNC	1994	DBLP DOI BibTeX RDF
15	Charles E. Molnar, Ian W. Jones, William S. Coates, Jon K. Lexau	A FIFO Ring Performance Experiment.	ASYNC	1997	DBLP DOI BibTeX RDF	FIFO ring performance experiment, high-speed FIFO circuit, asynchronous FIFO, clocked shift register, pulse-like protocol, two-phase clocked design, MOSIS, internal FIFO stages, 3.3 V, 1.67 to 4.8 V, 0.6 micron, pipeline, SPICE, data path, hSpice, circuit delays
14	Abdel Ejnioui	FPGA Prototyping of a Two-Phase Self-Oscillating Micropipeline.	ISVLSI	2007	DBLP DOI BibTeX RDF
14	Morteza Gholipour, Hamid Shojaee, Ali Afzali-Kusha, Ahmad Khademzadeh, Mehrdad Nourani	An efficient model for performance analysis of asynchronous pipeline design methods.	ISCAS (5)	2005	DBLP DOI BibTeX RDF
14	Tobias Bjerregaard, Shankar Mahadevan, Jens Sparsø	A Channel Library for Asynchronous Circuit Design Supporting Mixed-Mode Modeling.	PATMOS	2004	DBLP DOI BibTeX RDF
14	Marcos Ferretti, Peter A. Beerel	Single-Track Asynchronous Pipeline Templates Using 1-of-N Encoding.	DATE	2002	DBLP DOI BibTeX RDF
14	Gianluca Cornetta, Jordi Cortadella	A Multi-Radix Approach to Asynchronous Division.	ASYNC	2001	DBLP DOI BibTeX RDF
14	Amitava Mitra, William F. McLaughlin, Steven M. Nowick	Efficient Asynchronous Protocol Converters for Two-Phase Delay-Insensitive Global Communication.	ASYNC	2007	DBLP DOI BibTeX RDF
14	Feng Shi 0010, Yiorgos Makris	Testing delay faults in asynchronous handshake circuits.	ICCAD	2006	DBLP DOI BibTeX RDF	test generation, asynchronous circuits, delay faults, handshake circuits
14	Robert B. Reese, Mitchell A. Thornton, Cherrice Traver	A Coarse-Grain Phased Logic CPU.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	asynchronous, pipelined processor, Automatic synthesis, self-timed, micropipelines
14	Ilya Obridko, Ran Ginosar	Low energy asynchronous architectures.	ISCAS (5)	2005	DBLP DOI BibTeX RDF
14	Masashi Imai, Metehan Özcan, Takashi Nanya	Evaluation of Delay Variation in Asynchronous Circuits Based on the Scalable-Delay-Insensitive Model.	ASYNC	2004	DBLP DOI BibTeX RDF