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Found 73 publication records. Showing 73 according to the selection in the facets
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Authors |
Title |
Venue |
Year |
Link |
Author keywords |
56 | Sunan Tugsinavisut, Suwicha Jirayucharoensak, Peter A. Beerel |
An asynchronous pipeline comparisons with application to DCT matrix-vector multiplication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 361-364, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
50 | Sunan Tugsinavisut, Youpyo Hong, Daewook Kim, Kyeounsoo Kim, Peter A. Beerel |
Efficient asynchronous bundled-data pipelines for DCT matrix-vector multiplication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 13(4), pp. 448-461, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
49 | Masashi Imai, Takashi Nanya |
A Novel Design Method for Asynchronous Bundled-data Transfer Circuits Considering Characteristics of Delay Variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2006), 13-15 March 2006, Grenoble, France, pp. 68-77, 2006, IEEE Computer Society, 0-7695-2498-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
37 | David A. Kearney, Neil W. Bergmann |
Bundled Data Asynchronous Multipliers with Data Dependent Computation Times. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 3rd International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '97), 7-10 April 1997, Eindhoven, The Netherlands, pp. 186-197, 1997, IEEE Computer Society, 0-8186-7922-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
asynchronous logic data dependent performance multiplier |
36 | Takao Konishi, Naohiro Hamada, Hiroshi Saito |
A Control Circuit Synthesis Method for Asynchronous Circuits in Bundled-Data Implementation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CIT ![In: Seventh International Conference on Computer and Information Technology (CIT 2007), October 16-19, 2007, University of Aizu, Fukushima, Japan, pp. 847-852, 2007, IEEE Computer Society, 978-0-7695-2983-7. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
35 | Hiroshi Saito, Nattha Jindapetch, Tomohiro Yoneda, Chris J. Myers, Takashi Nanya |
ILP-based Scheduling for Asynchronous Circuits in Bundled-Data Implementation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CIT ![In: Sixth International Conference on Computer and Information Technology (CIT 2006), 20-22 September 2006, Seoul, Korea, pp. 172, 2006, IEEE Computer Society, 0-7695-2687-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
31 | Mohamed Kawokgy, C. André T. Salama |
Low-power asynchronous viterbi decoder for wireless applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004, Newport Beach, California, USA, August 9-11, 2004, pp. 286-289, 2004, ACM. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
bundled-data, four-phase, low-power, synchronous, wireless, VHDL, digital signal processing, asynchronous, register transfer level, viterbi algorithm, speed-independent, handshaking protocol |
29 | Yinghua Li, Alex Kondratyev, Robert K. Brayton |
Gaining Predictability and Noise Immunity in Global Interconnects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACSD ![In: Fifth International Conference on Application of Concurrency to System Design (ACSD 2005), 6-9 June 2005, St. Malo, France, pp. 176-185, 2005, IEEE Computer Society, 0-7695-2363-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
28 | D. J. Kinniment, Alexandre Yakovlev, Fei Xia, B. Gao |
Towards Asynchronous A-D Conversion. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '98), 30 March - 2 April 1998, San Diego, CA, USA, pp. 206-215, 1998, IEEE Computer Society, 0-8186-8392-9. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
analogue to digital conversion, synchronisers, asynchronous circuits, arbitration, signal transition graphs, metastability |
23 | Norman Kluge, Ralf Wollowski |
Data path optimisation and delay matching for asynchronous bundled-data balsa circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2017 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2017, Irvine, CA, USA, November 13-16, 2017, pp. 408-415, 2017, IEEE, 978-1-5386-3093-8. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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21 | Senri Yoshikawa, Shuji Sannomiya, Makoto Iwata, Akira Sato, Hiroaki Nishikawa |
EDA-oriented FPGA Circuit Design Method for Four-phase Bundled-data Circular Self-timed Pipeline. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Inf. Process. ![In: J. Inf. Process. 31, pp. 495-508, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
21 | Carsten Nielsen, Zhe Su, Giacomo Indiveri |
Yak: An Asynchronous Bundled Data Pipeline Description Language. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2308.04189, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
21 | Carsten Nielsen, Zhe Su, Giacomo Indiveri |
Yak: An Asynchronous Bundled Data Pipeline Description Language. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 28th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2023, Beijing, China, July 16-19, 2023, pp. 34-41, 2023, IEEE, 979-8-3503-0576-0. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
21 | Pallavi Srivastava, Edwin Chung |
An Asynchronous Bundled-Data Barrel Shifter Design That Incorporates a Deterministic Completion Detection Technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 69(3), pp. 1667-1671, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
21 | Yuhao Huang, Shanlin Xiao, Zhiyu Li, Zhiyi Yu |
An Asynchronous Bundled-Data Template With Current Sensing Completion Detection Technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 69(9), pp. 3904-3908, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
21 | Ruimin Zhu, Zeyang Xu, Yuhao Huang, Shanlin Xiao, Zhiyi Yu |
DFT Architecture for Click-Based Bundled-Data Asynchronous Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICTA ![In: 2022 IEEE International Conference on Integrated Circuits, Technologies and Applications, ICTA 2022, Xi'an, China, October 28-30, 2022, pp. 88-89, 2022, IEEE, 978-1-6654-9269-0. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
21 | Sai Aparna Aketi, Smriti Gupta, Huimei Cheng, Joycee Mekie, Peter A. Beerel |
SERAD: Soft Error Resilient Asynchronous Design using a Bundled Data Protocol. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2001.04039, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP BibTeX RDF |
|
21 | Sai Aparna Aketi, Smriti Gupta, Huimei Cheng, Joycee Mekie, Peter A. Beerel |
SERAD: Soft Error Resilient Asynchronous Design Using a Bundled Data Protocol. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Fundam. Theory Appl. ![In: IEEE Trans. Circuits Syst. I Fundam. Theory Appl. 67-I(5), pp. 1667-1677, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
21 | Felipe A. Kuentzer, Milos Krstic |
Soft Error Detection and Correction Architecture for Asynchronous Bundled Data Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. ![In: IEEE Trans. Circuits Syst. 67-I(12), pp. 4883-4894, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
21 | Yoan Decoudu, Jean Simatic, Katell Morin-Allory, Laurent Fesquet |
From High-Level Synthesis to Bundled-Data Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAMOS ![In: Embedded Computer Systems: Architectures, Modeling, and Simulation - 20th International Conference, SAMOS 2020, Samos, Greece, July 5-9, 2020, Proceedings, pp. 200-212, 2020, Springer, 978-3-030-60938-2. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
21 | Ricardo Aquino Guazzelli, Laurent Fesquet |
At-speed DfT Architecture for Bundled-data Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: IEEE International Test Conference, ITC 2020, Washington, DC, USA, November 1-6, 2020, pp. 1-9, 2020, IEEE, 978-1-7281-9113-3. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
21 | Yang Zhang 0014, Ji Li 0006, Huimei Cheng, Haipeng Zha, Jeffrey Draper, Peter A. Beerel |
Yield modelling and analysis of bundled data and ring-oscillator based designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IET Comput. Digit. Tech. ![In: IET Comput. Digit. Tech. 13(3), pp. 262-272, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
21 | Grégoire Gimenez, Jean Simatic, Laurent Fesquet |
From Signal Transition Graphs to Timing Closure: Application to Bundled-Data Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 25th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2019, Hirosaki, Japan, May 12-15, 2019, pp. 86-95, 2019, IEEE, 978-1-5386-4747-9. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
21 | Kshitij Bhardwaj, Paolo Mantovani, Luca P. Carloni, Steven M. Nowick |
Towards a Complete Methodology for Synthesizing Bundled-Data Asynchronous Circuits on FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2019, Lausanne, Switzerland, July 29-31, 2019, pp. 1-6, 2019, IEEE, 978-1-7281-2954-9. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
21 | Maryem Benyoussef, Claude Thibeault, Yvon Savaria |
A Prediction Model for Implementing DVS in Single-Rail Bundled-Data Handshake-Free Asynchronous Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2019, Sapporo, Japan, May 26-29, 2019, pp. 1-5, 2019, IEEE, 978-1-7281-0397-6. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
21 | Masashi Imai, Shinichiro Akasaka, Tomohiro Yoneda |
Novel Delay Elements for Bundled-Data Transfer Circuits Based on Two-Phase Handshaking Protocols. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 24th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2018, Vienna, Austria, May 13-16, 2018, pp. 1-8, 2018, IEEE Computer Society, 978-1-5386-5883-3. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
21 | Gregoire Gimenez, Abdelkarim Cherkaoui, Guillaume Cogniard, Laurent Fesquet |
Static Timing Analysis of Asynchronous Bundled-Data Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 24th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2018, Vienna, Austria, May 13-16, 2018, pp. 110-118, 2018, IEEE Computer Society, 978-1-5386-5883-3. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
21 | Yang Zhang 0014, Huimei Cheng, Dake Chen, Huayu Fu, Shikhanshu Agarwal, Mark Lin, Peter A. Beerel |
Challenges in Building an Open-Source Flow from RTL to Bundled-Data Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 24th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2018, Vienna, Austria, May 13-16, 2018, pp. 26-27, 2018, IEEE Computer Society, 978-1-5386-5883-3. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
21 | Anping He, Guangbo Feng, Jilin Zhang, Pengfei Li, Yong Hei, Hong Chen 0002 |
Click-Based Asynchronous Mesh Network with Bounded Bundled Data. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPP ![In: Proceedings of the 47th International Conference on Parallel Processing, ICPP 2018, Eugene, OR, USA, August 13-16, 2018, pp. 43:1-43:8, 2018, ACM. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
21 | Patrick Russell, Jens Döge, Christoph Hoppe, Thomas B. Preußer, Peter Reichel, Peter Schneider |
Implementation of an asynchronous bundled-data router for a GALS NoC in the context of a VSoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 20th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2017, Dresden, Germany, April 19-21, 2017, pp. 195-200, 2017, IEEE, 978-1-5386-0472-4. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
21 | Yang Zhang 0014, Haipeng Zha, Vaishnavi Sahir, Huimei Cheng, Peter A. Beerel |
Test Margin and Yield in Bundled Data and Ring-Oscillator Based Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 23rd IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2017, San Diego, CA, USA, May 21-24, 2017, pp. 85-93, 2017, IEEE Computer Society, 978-1-5386-2749-5. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
21 | Gabriele Miorandi, Marco Balboni, Steven M. Nowick, Davide Bertozzi |
Accurate Assessment of Bundled-Data Asynchronous NoCs Enabled by a Predictable and Efficient Hierarchical Synthesis Flow. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 23rd IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2017, San Diego, CA, USA, May 21-24, 2017, pp. 10-17, 2017, IEEE Computer Society, 978-1-5386-2749-5. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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21 | Jukiya Furushima, Masamitsu Nakajima, Hiroshi Saito |
Design of an Asynchronous Processor with Bundled-data Implementation on a Commercial Field Programmable Gate Array. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Informatica (Slovenia) ![In: Informatica (Slovenia) 40(4), 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP BibTeX RDF |
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21 | Ajay Singhvi, Matheus T. Moreira, Ramy N. Tadros, Ney Laert Vilar Calazans, Peter A. Beerel |
A Fine-Grain, Uniform, Energy-Efficient Delay Element for 2-Phase Bundled-Data Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM J. Emerg. Technol. Comput. Syst. ![In: ACM J. Emerg. Technol. Comput. Syst. 13(2), pp. 15:1-15:23, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
21 | Gabriele Miorandi, Alberto Celin, Michele Favalli, Davide Bertozzi |
A built-in self-testing framework for asynchronous bundled-data NoC switches resilient to delay variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NOCS ![In: Tenth IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2016, Nara, Japan, August 31 - September 2, 2016, pp. 1-8, 2016, IEEE, 978-1-4673-9030-9. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
21 | Dylan Hand, Austin Katrin, William Koven |
Adding Conditionality to Resilient Bundled-Data Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 22nd IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2016, Porto Alegre, Brazil, May 8-11, 2016, pp. 43-44, 2016, IEEE Computer Society, 978-1-4673-9007-1. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
21 | Norman Kluge, Ralf Wollowski |
Optimising Bundled-Data Balsa Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 22nd IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2016, Porto Alegre, Brazil, May 8-11, 2016, pp. 99-106, 2016, IEEE Computer Society, 978-1-4673-9007-1. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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21 | Jean Simatic, Abdelkarim Cherkaoui, Rodrigo Possamai Bastos, Laurent Fesquet |
New asynchronous protocols for enhancing area and throughput in bundled-data pipelines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: 29th Symposium on Integrated Circuits and Systems Design, SBCCI 2016, Belo Horizonte, Brazil, August 29 - September 3, 2016, pp. 1-6, 2016, IEEE, 978-1-5090-2736-1. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
21 | Shuichi Sato, Satoshi Ohtake |
A Delay Measurement Mechanism for Asynchronous Circuits of Bundled-Data Model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2015, Belgrade, Serbia, April 22-24, 2015, pp. 243-248, 2015, IEEE Computer Society, 978-1-4799-6779-7. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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21 | Matheus Gibiluka, Matheus Trevisan Moreira, Ney Laert Vilar Calazans |
A Bundled-Data Asynchronous Circuit Synthesis Flow Using a Commercial EDA Framework. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 2015 Euromicro Conference on Digital System Design, DSD 2015, Madeira, Portugal, August 26-28, 2015, pp. 79-86, 2015, IEEE Computer Society, 978-1-4673-8035-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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21 | Peter A. Beerel, Ney Laert Vilar Calazans |
A path towards average-case silicon via asynchronous resilient bundled-data design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ECCTD ![In: European Conference on Circuit Theory and Design, ECCTD 2015, Trondheim, Norway, August 24-26, 2015, pp. 1-4, 2015, IEEE, 978-1-4799-9877-7. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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21 | Matheus Gibiluka, Matheus Trevisan Moreira, Fernando Gehm Moraes, Ney Laert Vilar Calazans |
BAT-Hermes: A transition-signaling bundled-data NoC router. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LASCAS ![In: IEEE 6th Latin American Symposium on Circuits & Systems, LASCAS 2015, Montevideo, Uruguay, February 24-27, 2015, pp. 1-4, 2015, IEEE, 978-1-4799-8332-2. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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21 | Guilherme Heck, Leandro S. Heck, Ajay Singhvi, Matheus T. Moreira, Peter A. Beerel, Ney Laert Vilar Calazans |
Analysis and Optimization of Programmable Delay Elements for 2-Phase Bundled-Data Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSID ![In: 28th International Conference on VLSI Design, VLSID 2015, Bangalore, India, January 3-7, 2015, pp. 321-326, 2015, IEEE Computer Society, 978-1-4799-6658-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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21 | Arash Saifhashemi, Dylan Hand, Peter A. Beerel, William Koven, Hong Wang |
Performance and Area Optimization of a Bundled-Data Intel Processor through Resynthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 20th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2014, Potsdam, Germany, May 12-14, 2014, pp. 110-111, 2014, IEEE Computer Society, 978-1-4799-3789-9. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
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21 | Keitaro Takizawa, Shunya Hosaka, Hiroshi Saito |
A design support tool set for asynchronous circuits with bundled-data implementation on FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 24th International Conference on Field Programmable Logic and Applications, FPL 2014, Munich, Germany, 2-4 September, 2014, pp. 1-4, 2014, IEEE. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
21 | Minoru Iizuka, Naohiro Hamada, Hiroshi Saito |
An ASIC Design Support Tool Set for Non-pipelined Asynchronous Circuits with Bundled-Data Implementation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Electron. ![In: IEICE Trans. Electron. 96-C(4), pp. 482-491, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
21 | Alberto Ghiribaldi, Davide Bertozzi, Steven M. Nowick |
A transition-signaling bundled data NoC switch architecture for cost-effective GALS multicore systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 13, Grenoble, France, March 18-22, 2013, pp. 332-337, 2013, EDA Consortium San Jose, CA, USA / ACM DL, 978-1-4503-2153-2. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
21 | Jian Liu, Steven M. Nowick, Mingoo Seok |
Soft MOUSETRAP: A Bundled-Data Asynchronous Pipeline Scheme Tolerant to Random Variations at Ultra-Low Supply Voltages. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 19th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2013, Santa Monica, CA, USA, May 19-22, 2013, pp. 1-7, 2013, IEEE Computer Society, 978-1-4673-5956-6. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
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21 | Minoru Iizuka, Hiroshi Saito |
A floorplan method for ASIC designs of asynchronous circuits with bundled-data implementation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NEWCAS ![In: IEEE 11th International New Circuits and Systems Conference, NEWCAS 2013, Paris, France, June 16-19, 2013, pp. 1-4, 2013, IEEE, 978-1-4799-0618-5. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
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21 | Naohiro Hamada, Hiroshi Saito |
Integration of Behavioral Synthesis and Floorplanning for Asynchronous Circuits with Bundled-Data Implementation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Electron. ![In: IEICE Trans. Electron. 95-C(4), pp. 506-515, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
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21 | Soodeh Aghli Moghaddam, Siamak Mohammadi, Parviz Jabehdar Maralani |
Modified bundled-data as a new protocol for NoC asynchronous links. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 42(5), pp. 638-647, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
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21 | Minoru Iizuka, Naohiro Hamada, Hiroshi Saito, Ryoichi Yamaguchi, Minoru Yoshinaga |
A tool set for the design of asynchronous circuits with bundled-data implementation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: IEEE 29th International Conference on Computer Design, ICCD 2011, Amherst, MA, USA, October 9-12, 2011, pp. 78-83, 2011, IEEE Computer Society, 978-1-4577-1953-0. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
21 | Naohiro Hamada, Hiroshi Saito |
Integration of behavioral synthesis and floorplanning for asynchronous circuits with bundled-data implementation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, Lausanne, Switzerland, May 2-6, 2011, pp. 157-162, 2011, ACM, 978-1-4503-0667-6. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
21 | Hiroshi Saito, Naohiro Hamada, Tomohiro Yoneda, Takashi Nanya |
A floorplan method for asynchronous circuits with bundled-data implementation on FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2010), May 30 - June 2, 2010, Paris, France, pp. 925-928, 2010, IEEE, 978-1-4244-5308-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
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21 | Steffen Zeidler 0001, Alexandre V. Bystrov, Milos Krstic, Rolf Kraemer |
On-line testing of bundled-data asynchronous handshake protocols. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 16th IEEE International On-Line Testing Symposium (IOLTS 2010), 5-7 July, 2010, Corfu, Greece, pp. 261-267, 2010, IEEE Computer Society, 978-1-4244-7724-1. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
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21 | Naohiro Hamada, Yuki Shiga, Takao Konishi, Hiroshi Saito, Tomohiro Yoneda, Chris J. Myers, Takashi Nanya |
A Behavioral Synthesis System for Asynchronous Circuits with Bundled-data Implementation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPSJ Trans. Syst. LSI Des. Methodol. ![In: IPSJ Trans. Syst. LSI Des. Methodol. 2, pp. 64-79, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
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21 | Naohiro Hamada, Yuki Shiga, Hiroshi Saito, Tomohiro Yoneda, Chris J. Myers, Takashi Nanya |
A behavioral synthesis method for asynchronous circuits with bundled-data implementation (Tool paper). ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACSD ![In: 8th International Conference on Application of Concurrency to System Design (ACSD 2008), Xi'an, China, June 23-27, 2008, pp. 50-55, 2008, IEEE, 978-1-4244-1838-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
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21 | Hiroshi Saito, Naohiro Hamada, Nattha Jindapetch, Tomohiro Yoneda, Chris J. Myers, Takashi Nanya |
Scheduling Methods for Asynchronous Circuits with Bundled-Data Implementations Based on the Approximation of Start Times. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. ![In: IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 90-A(12), pp. 2790-2799, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
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21 | Masakazu Shimizu, Kôki Abe |
A Cost-Effective Handshake Protocol and Its Implementation for Bundled-Data Asynchronous Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. ![In: IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(1), pp. 280-287, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
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21 | Sunan Tugsinavisut, Peter A. Beerel |
Control Circuit Templates for Asynchronous Bundled-Data Pipelines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2002 Design, Automation and Test in Europe Conference and Exposition (DATE 2002), 4-8 March 2002, Paris, France, pp. 1098, 2002, IEEE Computer Society, 0-7695-1471-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
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21 | Volker Schöber, Thomas Kiel |
An Asynchronous Scan Path Concept for Micropipelines using the Bundled Data Convention. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 1996, Test and Design Validity, Washington, DC, USA, October 20-25, 1996, pp. 225-231, 1996, IEEE Computer Society, 0-7803-3541-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
21 | Per Torstein Røine |
Building fast bundled data circuits with a specialized standard cell library. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: Proceedings of the International Symposium on Advanced Research in Asynchronous Circuits and Systems, ASYNC 1994, Salt Lake City, UT, USA, November 3-5, 1994, pp. 134-143, 1994, IEEE, 0-8186-6210-7. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
15 | Charles E. Molnar, Ian W. Jones, William S. Coates, Jon K. Lexau |
A FIFO Ring Performance Experiment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 3rd International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '97), 7-10 April 1997, Eindhoven, The Netherlands, pp. 279-289, 1997, IEEE Computer Society, 0-8186-7922-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
FIFO ring performance experiment, high-speed FIFO circuit, asynchronous FIFO, clocked shift register, pulse-like protocol, two-phase clocked design, MOSIS, internal FIFO stages, 3.3 V, 1.67 to 4.8 V, 0.6 micron, pipeline, SPICE, data path, hSpice, circuit delays |
14 | Abdel Ejnioui |
FPGA Prototyping of a Two-Phase Self-Oscillating Micropipeline. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), May 9-11, 2007, Porto Alegre, Brazil, pp. 437-438, 2007, IEEE Computer Society, 0-7695-2896-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
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14 | Morteza Gholipour, Hamid Shojaee, Ali Afzali-Kusha, Ahmad Khademzadeh, Mehrdad Nourani |
An efficient model for performance analysis of asynchronous pipeline design methods. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 5234-5237, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
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14 | Tobias Bjerregaard, Shankar Mahadevan, Jens Sparsø |
A Channel Library for Asynchronous Circuit Design Supporting Mixed-Mode Modeling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation; 14th International Workshop, PATMOS 2004, Santorini, Greece, September 15-17, 2004, Proceedings, pp. 301-310, 2004, Springer, 3-540-23095-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
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14 | Marcos Ferretti, Peter A. Beerel |
Single-Track Asynchronous Pipeline Templates Using 1-of-N Encoding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2002 Design, Automation and Test in Europe Conference and Exposition (DATE 2002), 4-8 March 2002, Paris, France, pp. 1008-1015, 2002, IEEE Computer Society, 0-7695-1471-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
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14 | Gianluca Cornetta, Jordi Cortadella |
A Multi-Radix Approach to Asynchronous Division. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 7th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2001), 11-14 March 2001, Salt Lake City, UT, USA, pp. 25-, 2001, IEEE Computer Society, 0-7695-1034-5. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
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14 | Amitava Mitra, William F. McLaughlin, Steven M. Nowick |
Efficient Asynchronous Protocol Converters for Two-Phase Delay-Insensitive Global Communication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2007), 12-14 March 2006, Berkeley, California, USA, pp. 186-195, 2007, IEEE Computer Society, 978-0-7695-2771-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
14 | Feng Shi 0010, Yiorgos Makris |
Testing delay faults in asynchronous handshake circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2006 International Conference on Computer-Aided Design, ICCAD 2006, San Jose, CA, USA, November 5-9, 2006, pp. 193-197, 2006, ACM, 1-59593-389-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
test generation, asynchronous circuits, delay faults, handshake circuits |
14 | Robert B. Reese, Mitchell A. Thornton, Cherrice Traver |
A Coarse-Grain Phased Logic CPU. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 54(7), pp. 788-799, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
asynchronous, pipelined processor, Automatic synthesis, self-timed, micropipelines |
14 | Ilya Obridko, Ran Ginosar |
Low energy asynchronous architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 5238-5241, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
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14 | Masashi Imai, Metehan Özcan, Takashi Nanya |
Evaluation of Delay Variation in Asynchronous Circuits Based on the Scalable-Delay-Insensitive Model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 10th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2004), 19-23 April 2004, Crete, Greece, pp. 62-71, 2004, IEEE Computer Society, 0-7695-2133-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
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