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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 1178 occurrences of 716 keywords
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Results
Found 1407 publication records. Showing 1407 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
107 | Susumu Matsumae, Nobuki Tokura |
Simulating a Mesh with Separable Buses by a Mesh with Partitioned Buses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPAN ![In: 1999 International Symposium on Parallel Architectures, Algorithms and Networks (ISPAN '99), 23-25 June 1999, Fremantle, Australia, pp. 198-203, 1999, IEEE Computer Society, 0-7695-0231-8. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
two-dimensional mesh-connected computer, mesh with separable buses, mesh with partitioned buses, broadcasting, propagation delay, simulation algorithm |
89 | Susumu Matsumae |
Optimal Simulation of Meshes with Dynamically Separable Buses by Meshes with Statically Partitioned Buses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPAN ![In: 7th International Symposium on Parallel Architectures, Algorithms, and Networks (I-SPAN 2004), 10-12 May 2004, Hong Kong, SAR, China, pp. 475-481, 2004, IEEE Computer Society, 0-7695-2135-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
89 | Susumu Matsumae |
Simulation of Meshes with Separable Buses by Meshes with Multiple Partitioned Buses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 22-26 April 2003, Nice, France, CD-ROM/Abstracts Proceedings, pp. 163, 2003, IEEE Computer Society, 0-7695-1926-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
84 | Jeffrey A. Floyd, Matt Perry |
Real-time on-board bus testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 13th IEEE VLSI Test Symposium (VTS'95), April 30 - May 3, 1995, Princeton, New Jersey, USA, pp. 140-151, 1995, IEEE Computer Society, 0-8186-7000-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
on-board bus testing, wide buses, computer buses, board layout, full-fault testing, multiple speeds, pseudo-random pattern generation, characteristic equations, IEEE JTAG protocol, real-time systems, protocols, logic testing, automatic testing, system buses, operating environments, multiple seed, clock speeds |
82 | Kazuo Iwama, Eiji Miyano |
Oblivious Routing Algorithms on the Mesh of Buses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPPS ![In: 11th International Parallel Processing Symposium (IPPS '97), 1-5 April 1997, Geneva, Switzerland, Proceedings, pp. 721-727, 1997, IEEE Computer Society, 0-8186-7792-9. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
66 | Mounir Hamdi, J. Tong, C. W. Kin |
Fast sorting algorithms on reconfigurable array of processors with optical buses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPADS ![In: 1996 International Conference on Parallel and Distributed Systems (ICPADS '96), June 3-6, 1996, Tokyo, Japan, Proceedings, pp. 183-188, 1996, IEEE Computer Society, 0-8186-7267-6. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
reconfigurable array of processors, optical buses, parallel algorithms, parallel architectures, sorting, reconfigurable architectures, optical interconnections, system buses, sorting algorithms, reconfigurable array, reconfigurable arrays, parallel sorting algorithm |
66 | Qingli Zhang, Jinxiang Wang 0001, Yizheng Ye |
An energy-efficient temporal encoding circuit technique for on-chip high performance buses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30 - May 1, 2006, pp. 422-427, 2006, ACM, 1-59593-347-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
on-chip buses, energy-efficient, encoding, repeaters |
66 | Yi Pan 0001, Si-Qing Zheng, Keqin Li 0001, Hong Shen 0001 |
Semigroup and Prefix Computations on Improved Generalized Mesh-Connected Computers with Multiple Buses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: Proceedings of the 14th International Parallel & Distributed Processing Symposium (IPDPS'00), Cancun, Mexico, May 1-5, 2000, pp. 251-256, 2000, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
mesh-connected computer with multiple buses, parallel algorithm, parallel computing, parallel architecture, processor array, bus, mesh-connected computer |
65 | Nihar R. Mahapatra, Jiangjiang Liu 0002, Krishnan Sundaresan |
Hardware-Only Compression of Underutilized Address Buses: Design and Performance, Power, and Cost Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 21st International Conference on Computer Design (ICCD 2003),VLSI in Computers and Processors, 13-15 October 2003, San Jose, CA, USA, Proceedings, pp. 234-239, 2003, IEEE Computer Society, 0-7695-2025-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
58 | Jill H. Y. Law, Evangeline F. Y. Young |
Multi-bend bus driven floorplanning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2005 International Symposium on Physical Design, ISPD 2005, San Francisco, California, USA, April 3-6, 2005, pp. 113-120, 2005, ACM, 1-59593-021-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
bus planning, floorplanning, VLSI CAD |
57 | Dinesh C. Suresh, Banit Agrawal, Jun Yang 0002, Walid A. Najjar |
Energy-efficient encoding techniques for off-chip data buses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Embed. Comput. Syst. ![In: ACM Trans. Embed. Comput. Syst. 8(2), pp. 9:1-9:23, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Low-power data buses, bus switching, internal capacitances, encoding |
57 | Rahul M. Rao, Kanak Agarwal, Dennis Sylvester, Richard B. Brown, Kevin J. Nowka, Sani R. Nassif |
Approaches to run-time and standby mode leakage reduction in global buses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004, Newport Beach, California, USA, August 9-11, 2004, pp. 188-193, 2004, ACM. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
pulsed buses, leakage, repeaters, MTCMOS |
57 | Jihong Ren, Mark R. Greenstreet |
Synthesizing optimal filters for crosstalk-cancellation for high-speed buses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 40th Design Automation Conference, DAC 2003, Anaheim, CA, USA, June 2-6, 2003, pp. 592-597, 2003, ACM, 1-58113-688-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
equalizing filters, optimal synthesis, crosstalk, buses |
57 | Biing-Feng Wang, Stephan Olariu |
On the Power of the Mesh with Hybrid Buses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPAN ![In: 1997 International Symposium on Parallel Architectures, Algorithms and Networks (ISPAN '97), 18-20 December 1997, Taipei, Taiwan, pp. 172-178, 1997, IEEE Computer Society, 0-8186-8259-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
Mesh with Hybrid Buses, Mesh with Multiple Broadcasting, simulation, parallel algorithms, PRAM, reconfigurable mesh |
57 | Zicheng Guo, Rami G. Melhem |
Embedding Binary X-Trees and Pyramids in Processor Arrays with Spanning Buses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 5(6), pp. 664-672, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
binaryX-trees, spanning buses, 2-D arrayarchitectures, routing step, parallel architectures, multiprocessor interconnection networks, embedding, network routing, binary trees, processor arrays, pyramids, network embeddings |
57 | Mauricio J. Serrano, Behrooz Parhami |
Optimal Architectures and Algorithms for Mesh-Connected Parallel Computers with Separable Row/Column Buses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 4(10), pp. 1073-1080, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
mesh-connected, separable row and column buses, parallel algorithms, computational complexity, parallel computers, parallel architectures, time complexity, processing elements, data routing, two-dimensional mesh, prefix computation, semigroup computation |
50 | Jong Hyuk Choi, Bong Wan Kim, Kyu Ho Park, Kwang-Il Park |
A Bandwidth-Efficient Implementation of Mesh with Multiple Broadcasting. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPP ![In: Proceedings of the International Conference on Parallel Processing 1999, ICPP 1999, Wakamatsu, Japan, September 21-24, 1999, pp. 434-443, 1999, IEEE Computer Society, 0-7695-0350-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
Mesh with Buses, Parallel Computing, Multicast, Interconnection Network, Broadcast, Collective Communication |
50 | Jongmin Lee, Eujoon Byun, Hanmook Park, Jongmoo Choi, Donghee Lee 0001, Sam H. Noh |
CPS-SIM: configurable and accurate clock precision solid state drive simulator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAC ![In: Proceedings of the 2009 ACM Symposium on Applied Computing (SAC), Honolulu, Hawaii, USA, March 9-12, 2009, pp. 318-325, 2009, ACM, 978-1-60558-166-8. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
SSD (solid state drive), clock precision SSD simulator, configurability, NAND flash memory, FTL (flash translation layer) |
50 | Hua Xiang 0001, Liang Deng, Li-Da Huang, Martin D. F. Wong |
OPC-Friendly Bus Driven Floorplanning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 8th International Symposium on Quality of Electronic Design (ISQED 2007), 26-28 March 2007, San Jose, CA, USA, pp. 847-852, 2007, IEEE Computer Society, 978-0-7695-2795-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
50 | Marcello Coppola |
Trends and Trade-offs in Designing Highly Robust Throughput on Chip Communication Network. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 10-12 July 2006, Como, Italy, pp. 80, 2006, IEEE Computer Society, 0-7695-2620-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
50 | Chia-Chun Tsai, Jan-Ou Wu, Trong-Yen Lee, Rong-Shue Hsiao |
Propagation Delay Minimization on RLC-Based Bus with Repeater Insertion. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems 2006, APCCAS 2006, Singapore, 4-7 December 2006, pp. 1285-1288, 2006, IEEE, 1-4244-0387-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
50 | Sotirios G. Ziavras |
Performance Analysis for an Important Class of Parallel-Processing Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPAN ![In: 1996 International Symposium on Parallel Architectures, Algorithms and Networks (ISPAN '96), June 12-14, 1996, Beijing, China, pp. 500-506, 1996, IEEE Computer Society, 0-8186-7460-1. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
complexity of algorithms, parallel algorithms, broadcasting, cost analysis, mesh architecture |
50 | Cauligi S. Raghavendra |
HMESH: A VLSI Architecture for Parallel Processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CONPAR ![In: CONPAR 86: Conference on Algorithms and Hardware for Parallel Processing, Aachen, Germany, September 17-19, 1986, Proceedings, pp. 76-83, 1986, Springer, 3-540-16811-7. The full citation details ...](Pics/full.jpeg) |
1986 |
DBLP DOI BibTeX RDF |
|
50 | Sanguthevar Rajasekaran |
Mesh Connected Computers with Fixed and Reconfigurable Buses: Packet Routing and Sorting. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 45(5), pp. 529-539, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
mesh with reconfigurable buses, mesh with fixed buses, k?k routing, k?k sorting, parallel computing, randomized algorithms, sorting, mesh, packet routing, Reconfigurable networks |
50 | Kuo-Liang Chung, Yu-Chih Lin |
A Parametric Algorithm for Semigroup Computation on Mesh with Buses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Computing ![In: Computing 57(3), pp. 245-254, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
mesh-connected computers with segmented buses, reconfigurable buses, parametric parallel algorithm, broadcasting, Semigroup computation |
49 | Jun Yang 0002, Rajiv Gupta 0001, Chuanjun Zhang |
Frequent value encoding for low power data buses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 9(3), pp. 354-384, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
I/O pin capacitance, Low power data buses, internal capacitance, encoding, switching |
49 | Maged Ghoneima, Yehea I. Ismail |
Optimum positioning of interleaved repeaters In bidirectional buses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 40th Design Automation Conference, DAC 2003, Anaheim, CA, USA, June 2-6, 2003, pp. 586-591, 2003, ACM, 1-58113-688-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
delay, interconnect, noise, repeaters, buses |
49 | Yan Zhang 0028, John C. Lach, Kevin Skadron, Mircea R. Stan |
Odd/even bus invert with two-phase transfer for buses with coupling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002, Monterey, California, USA, August 12-14, 2002, pp. 80-83, 2002, ACM, 1-58113-475-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
bus invert, buses with coupling, coding for low-power I/O |
49 | Yi Pan 0001, Si-Qing Zheng, Keqin Li 0001, Hong Shen 0001 |
An Improved Generalization of Mesh-Connected Computers with Multiple Buses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 12(3), pp. 293-305, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
mesh-connected computer with multiple buses, parallel algorithm, parallel computing, parallel architecture, processor array, Bus, mesh-connected computer |
49 | Rong Lin, Stephan Olariu, James L. Schwing, Biing-Feng Wang |
The Mesh with Hybrid Buses: An Efficient Parallel Architecture for Digital Geometry. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 10(3), pp. 266-280, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
mesh with hybrid buses, cost-optimal algorithms, pattern recognition, image processing, broadcasting, VLSI architectures, digital geometry, cellular systems |
49 | Sharath Jayaprakash, Nihar R. Mahapatra |
Partitioned Hybrid Encoding to Minimize On-Chip Energy Dissipation ofWide Microprocessor Buses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 20th International Conference on VLSI Design (VLSI Design 2007), Sixth International Conference on Embedded Systems (ICES 2007), 6-10 January 2007, Bangalore, India, pp. 127-134, 2007, IEEE Computer Society, 0-7695-2762-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
49 | Himanshu Kaul, Dennis Sylvester, Mark A. Anders 0001, Ram Krishnamurthy 0001 |
Design and analysis of spatial encoding circuits for peak power reduction in on-chip buses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 13(11), pp. 1225-1238, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
49 | Krishnan Sundaresan, Nihar R. Mahapatra |
An Accurate Energy and Thermal Model for Global Signal Buses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 18th International Conference on VLSI Design (VLSI Design 2005), with the 4th International Conference on Embedded Systems Design, 3-7 January 2005, Kolkata, India, pp. 685-690, 2005, IEEE Computer Society, 0-7695-2264-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
49 | Claudia Kretzschmar, André K. Nieuwland, Dietmar Müller 0001 |
Why Transition Coding for Power Minimization of On-Chip Buses Does Not Work. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France, pp. 512-517, 2004, IEEE Computer Society, 0-7695-2085-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
49 | Himanshu Kaul, Dennis Sylvester, Mark A. Anders 0001, Ram Krishnamurthy 0001 |
Spatial encoding circuit techniques for peak power reduction of on-chip high-performance buses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004, Newport Beach, California, USA, August 9-11, 2004, pp. 194-199, 2004, ACM. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
49 | Tiehan Lv, Jörg Henkel, Haris Lekatsas, Wayne H. Wolf |
A dictionary-based en/decoding scheme for low-power data buses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 11(5), pp. 943-951, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
49 | Amos Beimel, Shlomi Dolev |
Buses for Anonymous Message Delivery. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Cryptol. ![In: J. Cryptol. 16(1), pp. 25-39, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Privacy, Traffic analysis, Anonymous communication |
49 | William Fornaciari, M. Polentarutti, Donatella Sciuto, Cristina Silvano |
Power optimization of system-level address buses based on software profiling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES ![In: Proceedings of the Eighth International Workshop on Hardware/Software Codesign, CODES 2000, San Diego, California, USA, 2000, pp. 29-33, 2000, ACM, 1-58113-268-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
49 | Ming-Dou Ker, Hun-Hsien Chang, Tung-Yang Chen |
ESD buses for whole-chip ESD protection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30 - June 2, 1999, pp. 545-548, 1999, IEEE, 0-7803-5471-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
49 | Sanguthevar Rajasekaran |
Mesh Connected Computers with Fixed and Reconfigurable Buses: Packet Routing, Sorting, and Selection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESA ![In: Algorithms - ESA '93, First Annual European Symposium, Bad Honnef, Germany, September 30 - October 2, 1993, Proceedings, pp. 309-320, 1993, Springer, 3-540-57273-2. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
42 | Seong Yong Ohm, Fadi J. Kurdahi, Nikil D. Dutt, Min Xu |
A comprehensive estimation technique for high-level synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSS ![In: Proceedings of the 8th International Symposium on System Synthesis (ISSS 1995), September 13-15, 1995, Cannes, France, pp. 122-127, 1995, ACM, 0-89791-771-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
HLS benchmarks, RT level components, RTL datapaths, estimation technique, delays, high level synthesis, high-level synthesis, timing, design space exploration, granularity, hardware description languages, data flow graphs, registers, system buses, timing model, buses, behavioral description, layout area |
42 | Mircea R. Stan, Wayne P. Burleson |
Coding a terminated bus for low power. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 5th Great Lakes Symposium on VLSI (GLS-VLSI '95), March 16-18, 1995, The State University of New York at Buffalo, USA, pp. 70-73, 1995, IEEE Computer Society, 0-8186-7035-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
pull-up terminators, bus liner, limited-weight codes, parallel terminated buses, Rambus, perfect k/2-limited weight code, nonperfect 3-limited weight code, error correction codes, encoding, decoding, power dissipation, random-access storage, system buses |
41 | Anu G. Bourgeois, Jerry L. Trahan |
Relating Two-Dimensional Reconfigurable Meshes with Optically Pipelined Buses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: Proceedings of the 14th International Parallel & Distributed Processing Symposium (IPDPS'00), Cancun, Mexico, May 1-5, 2000, pp. 747-752, 2000, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Reconfigurable models, optical buses, complexity, model simulations |
41 | Sandy Pavel, Selim G. Akl |
Efficient Algorithms for the Hough Transform on Arrays with Reconfigurable Optical Buses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPPS ![In: Proceedings of IPPS '96, The 10th International Parallel Processing Symposium, April 15-19, 1996, Honolulu, Hawaii, USA, pp. 697-701, 1996, IEEE Computer Society, 0-8186-7255-2. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
arrays with reconfigurable optical buses, Hough transform |
41 | Mounir Hamdi, Yi Pan 0001 |
Communication-efficient algorithms on reconfigurable array of processors with spanning optical buses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPAN ![In: 1996 International Symposium on Parallel Architectures, Algorithms and Networks (ISPAN '96), June 12-14, 1996, Beijing, China, pp. 440-446, 1996, IEEE Computer Society, 0-8186-7460-1. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
reconfigurable array of processors, spanning optical buses, optical signal transmissions, RASOB, semi-group computations, parallel algorithms, parallel architectures, reconfiguration, reconfigurable architectures, optical interconnections, Gaussian eliminations |
41 | Jop F. Sibeyn, Michael Kaufmann 0001, Rajeev Raman |
Randomized Routing on Meshes with Buses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESA ![In: Algorithms - ESA '93, First Annual European Symposium, Bad Honnef, Germany, September 30 - October 2, 1993, Proceedings, pp. 333-344, 1993, Springer, 3-540-57273-2. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
algorithms, parallel computation, lower bounds, meshes, randomization, coloring, packet routing, buses |
40 | Madhu Mutyam, Melvin Eze, Narayanan Vijaykrishnan, Yuan Xie 0001 |
Delay and Energy Efficient Data Transmission for On-Chip Buses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2-3 March 2006, Karlsruhe, Germany, pp. 355-360, 2006, IEEE Computer Society, 0-7695-2533-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
40 | Krishnan Sundaresan, Nihar R. Mahapatra |
Value-based bit ordering for energy optimization of on-chip global signal buses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006, pp. 624-625, 2006, European Design and Automation Association, Leuven, Belgium, 3-9810801-1-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
40 | Boon-Chong Seet, Chiew Tong Lau, Wen-Jing Hsu, Bu-Sung Lee |
A Mobile System of Super-Peers Using City Buses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PerCom Workshops ![In: 3rd IEEE Conference on Pervasive Computing and Communications Workshops (PerCom 2005 Workshops), 8-12 March 2005, Kauai Island, HI, USA, pp. 80-85, 2005, IEEE Computer Society, 0-7695-2300-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
40 | Liang Zhang 0038, John M. Wilson 0002, Rizwan Bashirullah, Lei Luo 0006, Jian Xu, Paul D. Franzon |
Driver pre-emphasis techniques for on-chip global buses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005, San Diego, California, USA, August 8-10, 2005, pp. 186-191, 2005, ACM, 1-59593-137-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
current sensing, peak current, pre-emphasis, low-power, crosstalk, differential, on-chip bus |
40 | Dinesh C. Suresh, Banit Agrawal, Jun Yang 0002, Walid A. Najjar |
A tunable bus encoder for off-chip data buses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005, San Diego, California, USA, August 8-10, 2005, pp. 319-322, 2005, ACM, 1-59593-137-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
TUBE, data bus, data bus encoding, tunable bus encoder |
40 | Yi Zhao, Sujit Dey, Li Chen |
Double sampling data checking technique: an online testing solution for multisource noise-induced errors on on-chip interconnects and buses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 12(7), pp. 746-755, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
40 | Peter Caputa, Henrik Fredriksson, Martin Hansson, Stefan Back Andersson, Atila Alvandpour, Christer Svensson |
An Extended Transition Energy Cost Model for Buses in Deep Submicron Technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation; 14th International Workshop, PATMOS 2004, Santorini, Greece, September 15-17, 2004, Proceedings, pp. 849-858, 2004, Springer, 3-540-23095-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
40 | Jiangjiang Liu 0002, Nihar R. Mahapatra, Krishnan Sundaresan |
Hardware-Only Compression to Reduce Cost and Improve Utilization of Address Buses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2003 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2003), New Trends and Technologies for VLSI Systems Design, 20-21 February 2003, Tampa, FL, USA, pp. 220-221, 2003, IEEE Computer Society, 0-7695-1904-0. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
40 | Dinesh C. Suresh, Jun Yang 0002, Chuanjun Zhang, Banit Agrawal, Walid A. Najjar |
FV-MSB: A Scheme for Reducing Transition Activity on Data Buses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HiPC ![In: High Performance Computing - HiPC 2003, 10th International Conference, Hyderabad, India, December 17-20, 2003, Proceedings, pp. 44-54, 2003, Springer, 3-540-20626-4. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
40 | Susumu Matsumae |
An Efficient Scaling-Simulation Algorithm of Reconfigurable Meshes by Meshes with Partitioned Buses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 22-26 April 2003, Nice, France, CD-ROM/Abstracts Proceedings, pp. 183, 2003, IEEE Computer Society, 0-7695-1926-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
40 | Dinesh C. Suresh, Banit Agrawal, Jun Yang 0002, Walid A. Najjar, Laxmi N. Bhuyan |
Power efficient encoding techniques for off-chip data buses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES 2003, San Jose, California, USA, October 30 - November 1, 2003, pp. 267-275, 2003, ACM, 1-58113-676-5. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
FV, FV-MSB-LSB, data bus, low power, bus encoding |
40 | Abhijit Chatterjee, Peeter Ellervee, Vincent John Mooney III, Jun-Cheol Park, Kyu-won Choi, Kiran Puttaswamy |
System Level Power-Performance Trade-Offs in Embedded Systems Using Voltage and Frequency Scaling of Off-Chip Buses and Memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSS ![In: Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), October 2-4, 2002, Kyoto, Japan, pp. 225-230, 2002, ACM / IEEE Computer Society, 1-58113-576-9. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
voltage/frequency scaling, embedded systems, design space, power-performance trade-offs |
40 | Yi Zhao, Li Chen, Sujit Dey |
On-Line Testing of Multi-Source Noise-Induced Errors on the Interconnects and Buses of System-on-Chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 2002, Baltimore, MD, USA, October 7-10, 2002, pp. 491-499, 2002, IEEE Computer Society, 0-7803-7543-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
40 | Wei-Cheng Lai, Jing-Reng Huang, Kwang-Ting (Tim) Cheng |
Embedded-Software-Based Approach to Testing Crosstalk-Induced Faults at On-Chip Buses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April - 3 May 2001, Marina Del Rey, CA, USA, pp. 204-209, 2001, IEEE Computer Society, 0-7695-1122-8. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
40 | Kazuo Iwama, Eiji Miyano, Satoshi Tajima, Hisao Tamaki |
Efficient Randomized Routing Algorithms on the Two-Dimensional Mesh of Buses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
COCOON ![In: Computing and Combinatorics, 4th Annual International Conference, COCOON '98, Taipei, Taiwan, R.o.C., August 12-14, 1998, Proceedings, pp. 229-240, 1998, Springer, 3-540-64824-0. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
40 | Ville Leppänen |
Embedding and Emulation Results for Static Multichannel Mesh of Optical Buses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Euro-Par ![In: Euro-Par '97 Parallel Processing, Third International Euro-Par Conference, Passau, Germany, August 26-29, 1997, Proceedings, pp. 246-249, 1997, Springer, 3-540-63440-1. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
40 | Kuo-Liang Chung |
Prefix Computations on a Generalized Mesh-Connected Computer with Multiple Buses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 6(2), pp. 196-199, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
40 | Harish Kriplani, Farid N. Najm, Ibrahim N. Hajj |
Pattern independent maximum current estimation in power and ground buses of CMOS VLSI circuits: Algorithms, signal correlations, and their resolution. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(8), pp. 998-1012, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
40 | Kazuo Iwama, Eiji Miyano |
Routing Problems on the Mesh of Buses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISAAC ![In: Algorithms and Computation, Third International Symposium, ISAAC '92, Nagoya, Japan, December 16-18, 1992, Proceedings, pp. 155-164, 1992, Springer, 3-540-56279-6. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
34 | Andrew Tjang, Michael Pagliorola, Hiral Patel, Xiaoyan Li, Richard P. Martin |
Active Tapes: Bus-Based Sensor Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCN ![In: 29th Annual IEEE Conference on Local Computer Networks (LCN 2004), 16-18 November 2004, Tampa, FL, USA, Proceedings, pp. 565-566, 2004, IEEE Computer Society, 0-7695-2260-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Power buses, Data buses, Sensor networks |
34 | Russ Miller, Quentin F. Stout |
Simulating Essential Pyramids. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 37(12), pp. 1642-1648, 1988. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
essential pyramids, pyramid algorithms, mesh with row and column buses, mesh with reconfigurable buses, pyramid computer, simulation, image processing, parallel processing, virtual machines, hypercube, mesh, computerised picture processing, optimal algorithms, PRAM, mesh-of-trees |
34 | Masaru Takesue |
Psi-Cubes: Recursive Bused Fat-Hypercubes for Multilevel Snoopy Caches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPAN ![In: 1999 International Symposium on Parallel Architectures, Algorithms and Networks (ISPAN '99), 23-25 June 1999, Fremantle, Australia, pp. 62-67, 1999, IEEE Computer Society, 0-7695-0231-8. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
Bused networks, recursive networks, trees of buses, multilevel caches, coherence directories, clustering, Hamming codes |
33 | Tilen Ma, Evangeline F. Y. Young |
TCG-based multi-bend bus driven floorplanning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 13th Asia South Pacific Design Automation Conference, ASP-DAC 2008, Seoul, Korea, January 21-24, 2008, pp. 192-197, 2008, IEEE, 978-1-4244-1921-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
33 | Xiaolan Zhang 0003, Jim Kurose, Brian Neil Levine, Donald F. Towsley, Honggang Zhang 0003 |
Study of a bus-based disruption-tolerant network: mobility modeling and impact on routing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MobiCom ![In: Proceedings of the 13th Annual International Conference on Mobile Computing and Networking, MOBICOM 2007, Montréal, Québec, Canada, September 9-14, 2007, pp. 195-206, 2007, ACM, 978-1-59593-681-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
mobility trace modeling, DTN, epidemic routing |
33 | Edwin Naroska, Shanq-Jang Ruan, Uwe Schwiegelshohn |
Simultaneously optimizing crosstalk and power for instruction bus coupling capacitance using wire pairing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 14(4), pp. 421-425, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
33 | Sujan Pandey, Manfred Glesner |
Statistical on-chip communication bus synthesis and voltage scaling under timing yield constraint. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006, pp. 663-668, 2006, ACM, 1-59593-381-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
communication bus synthesis, voltage scaling |
33 | Shanq-Jang Ruan, Edwin Naroska, Uwe Schwiegelshohn |
Simultaneous Wire Permutation, Inversion, and Spacing with Genetic Algorithm for Energy-Efficient Bus Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), CD-ROM / Abstracts Proceedings, 4-8 April 2005, Denver, CO, USA, 2005, IEEE Computer Society, 0-7695-2312-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
33 | Mahesh Mamidipaka, Daniel S. Hirschberg, Nikil D. Dutt |
Adaptive low-power address encoding techniques using self-organizing lists. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 11(5), pp. 827-834, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
33 | Makoto Sugihara, Hiroto Yasuura |
Optimization of Test Accesses with a Combined BIST and External Test Scheme. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC/VLSI Design ![In: Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), and the 15th International Conference on VLSI Design (VLSI Design 2002), Bangalore, India, January 7-11, 2002, pp. 683-688, 2002, IEEE Computer Society, 0-7695-1299-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
external test, CBET, test access, external pins, BIST, test scheduling, test time, test bus |
33 | Chittaranjan A. Mandal, R. M. Zimmer |
A Genetic Algorithm for the Synthesis of Structured Data Paths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 13th International Conference on VLSI Design (VLSI Design 2000), 4-7 January 2000, Calcutta, India, pp. 206-211, 2000, IEEE Computer Society, 0-7695-0487-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Data Path Synthesis (DPS), Scheduling, High-Level Synthesis (HLS), Allocation |
33 | Friedhelm Meyer auf der Heide, Harald Räcke, Matthias Westermann |
Data management in hierarchical bus networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SPAA ![In: Proceedings of the Twelfth annual ACM Symposium on Parallel Algorithms and Architectures, SPAA 2000, Bar Harbor, Maine, USA, July 9-13, 2000, pp. 109-118, 2000, ACM, 1-58113-185-2. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
33 | Aurobindo Dasgupta, Ramesh Karri |
High-reliability, low-energy microarchitecture synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(12), pp. 1273-1280, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
33 | Scott T. Leutenegger, Mary K. Vernon |
A Mean-Value Performance Analysis of a New Multiprocessor Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGMETRICS ![In: Proceedings of the 1988 ACM SIGMETRICS conference on Measurement and modeling of computer systems, Santa Fe, New Mexico, USA, May 24-27, 1988, pp. 167-176, 1988, ACM, 0-89791-254-3. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
|
33 | Kimish Patel, Wonbok Lee, Massoud Pedram |
In-order pulsed charge recycling in off-chip data buses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, Orlando, Florida, USA, May 4-6, 2008, pp. 371-374, 2008, ACM, 978-1-59593-999-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
data buses, power, charge recycling |
33 | Maged Ghoneima, Yehea I. Ismail |
Delayed line bus scheme: a low-power bus scheme for coupled on-chip buses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004, Newport Beach, California, USA, August 9-11, 2004, pp. 66-69, 2004, ACM. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
low power, interconnects, buses, coupling capacitance |
33 | Michel Dubois 0001 |
Throughput Analysis of Cache-Based Multiprocessors with Multiple Buses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 37(1), pp. 58-70, 1988. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
shared interleaved memory, cache-based multiprocessors, general-purpose computing, dynamic instruction mix statistics, performance evaluation, performance, throughput, multiprocessing systems, buffer storage, multitasking, private cache, multiple buses |
32 | Antoine Courtay, Johann Laurent, Olivier Sentieys, Nathalie Julien |
Novel Cross-Transition Elimination Technique Improving Delay and Power Consumption for On-Chip Buses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 18th International Workshop, PATMOS 2008, Lisbon, Portugal, September 10-12, 2008. Revised Selected Papers, pp. 359-368, 2008, Springer, 978-3-540-95947-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
32 | Tomoya Kitani, Takashi Shinkawa, Naoki Shibata, Keiichi Yasumoto, Minoru Ito, Teruo Higashino |
Efficient VANET-Based Traffic Information Sharing using Buses on Regular Routes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTC Spring ![In: Proceedings of the 67th IEEE Vehicular Technology Conference, VTC Spring 2008, 11-14 May 2008, Singapore, pp. 3031-3036, 2008, IEEE. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
32 | Michel Sede, Xu Li 0009, Da Li, Min-You Wu, Minglu Li 0001, Wei Shu |
Routing in Large-Scale Buses Ad Hoc Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WCNC ![In: WCNC 2008, IEEE Wireless Communications & Networking Conference, March 31 2008 - April 3 2008, Las Vegas, Nevada, USA, Conference Proceedings, pp. 2711-2716, 2008, IEEE, 978-1-4244-1997-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
32 | Dirk Koch, Christian Haubelt, Jürgen Teich |
Efficient Reconfigurable On-Chip Buses for FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 16th IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2008, 14-15 April 2008, Stanford, Palo Alto, California, USA, pp. 287-290, 2008, IEEE Computer Society, 978-0-7695-3307-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
32 | Karthik Duraisami, Enrico Macii, Massimo Poncino |
Energy efficiency bounds of pulse-encoded buses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, Orlando, Florida, USA, May 4-6, 2008, pp. 183-188, 2008, ACM, 978-1-59593-999-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
power reduction., pulse wave transmission, high-speed interconnect, transition activity |
32 | Krishnan Sundaresan, Nihar R. Mahapatra |
Interconnect Signaling and Layout Optimization to Manage Thermal Effects Due to Self Heating in On-Chip Signal Buses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 9th International Symposium on Quality of Electronic Design (ISQED 2008), 17-19 March 2008, San Jose, CA, USA, pp. 118-122, 2008, IEEE Computer Society, 978-0-7695-3117-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Bus Energy, Self Heating, Wire Permutation, Optimization, Interconnect, Layout, Temperature, On-Chip Bus |
32 | David C. Keezer, Dany Minier, Patrice Ducharme |
Source-Synchronous Testing of Multilane PCI Express and HyperTransport Buses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 23(1), pp. 46-57, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
control structure reliability, multi-gigahertz testing, picosecond timing accuracy, jitter-tolerance testing, jitter injection, fault tolerance, testing |
32 | Jin Guo 0001, Antonis Papanikolaou, Pol Marchal, Francky Catthoor |
Physical design implementation of segmented buses to reduce communication energy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, Yokohama, Japan, January 24-27, 2006, pp. 42-47, 2006, IEEE, 0-7803-9451-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
32 | Yeow Meng Chee, Charles J. Colbourn, Alan C. H. Ling |
Optimal memoryless encoding for low power off-chip data buses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2006 International Conference on Computer-Aided Design, ICCAD 2006, San Jose, CA, USA, November 5-9, 2006, pp. 369-374, 2006, ACM, 1-59593-389-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
32 | Chunjie Duan, Kanupriya Gulati, Sunil P. Khatri |
Memory-based crosstalk canceling CODECs for on-chip buses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
32 | Jiangjiang Liu 0002, Krishnan Sundaresan, Nihar R. Mahapatra |
Efficient encoding for address buses with temporal redundancy for simultaneous area and energy reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30 - May 1, 2006, pp. 111-114, 2006, ACM, 1-59593-347-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
address bus, low power, encoding, energy dissipation |
32 | Yi-Le Huang, Chun-Yao Wang, Richard Yeh, Shih-Chieh Chang, Yung-Chih Chen |
Language-Based High Level Transaction Extraction on On-chip Buses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 7th International Symposium on Quality of Electronic Design (ISQED 2006), 27-29 March 2006, San Jose, CA, USA, pp. 231-236, 2006, IEEE Computer Society, 0-7695-2523-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
32 | Qingli Zhang, Jinxiang Wang 0001, Yizheng Ye |
Low-Power Crosstalk Avoidance Encoding for On-Chip Data Buses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems 2006, APCCAS 2006, Singapore, 4-7 December 2006, pp. 1611-1614, 2006, IEEE, 1-4244-0387-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
32 | Maged Ghoneima, Yehea I. Ismail |
Optimum positioning of interleaved repeaters in bidirectional buses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(3), pp. 461-469, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
32 | Masanori Muroyama, Kosuke Tarumi, Koji Makiyama, Hiroto Yasuura |
A variation-aware low-power coding methodology for tightly coupled buses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005, pp. 557-560, 2005, ACM Press, 0-7803-8737-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
32 | Teck Meng Lim, Boon-Chong Seet, Bu-Sung Lee, Chai Kiat Yeo, Andreas Kassler |
Pervasive Communication for Commuters in Public Buses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PerCom Workshops ![In: 3rd IEEE Conference on Pervasive Computing and Communications Workshops (PerCom 2005 Workshops), 8-12 March 2005, Kauai Island, HI, USA, pp. 75-79, 2005, IEEE Computer Society, 0-7695-2300-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
32 | Dinesh C. Suresh, Banit Agrawal, Walid A. Najjar, Jun Yang 0002 |
VALVE: Variable Length Value Encoder for Off-Chip Data Buses.. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 23rd International Conference on Computer Design (ICCD 2005), 2-5 October 2005, San Jose, CA, USA, pp. 631-633, 2005, IEEE Computer Society, 0-7695-2451-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
32 | Maged Ghoneima, Yehea I. Ismail |
Accurate decoupling of capacitively coupled buses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 4146-4149, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
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