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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 342 occurrences of 250 keywords
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Results
Found 362 publication records. Showing 362 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
79 | Vijay K. Jain, L. Lin |
High-speed double precision computation of nonlinear functions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 12th Symposium on Computer Arithmetic (ARITH-12 '95), July 19-21, 1995, Bath, England, UK, pp. 107-114, 1995, IEEE Computer Society, 0-8186-7089-4. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
high-speed double precision computation, interpolative approach, third degree polynomial, image processing, interpolation, interpolation, scientific computing, digital arithmetic, multiplications, coprocessors, coprocessors, real-time image processing, nonlinear functions, silicon area |
69 | Domingo Benitez |
A Quantitative Understanding of the Performance of Reconfigurable Coprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, Reconfigurable Computing Is Going Mainstream, 12th International Conference, FPL 2002, Montpellier, France, September 2-4, 2002, Proceedings, pp. 976-986, 2002, Springer, 3-540-44108-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
67 | Bradly K. Fawcett, J. Watson |
Reconfigurable Processing With Field Programmable Gate Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 1996 International Conference on Application-Specific Systems, Architectures, and Processors (ASAP '96), August 19-23, 1996, Chicago, IL , USA, pp. 293-302, 1996, IEEE Computer Society, 0-8186-7542-X. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
reconfigurable processing, internal architecture, computationally-intensive tasks, programmable solution, XC6200 FPGA architecture, SRAM control store, on-chip memory capability, field programmable gate arrays, interconnections, reconfigurable architectures, processors, coprocessors, coprocessors, SRAM chips, SRAM-based field programmable gate arrays |
66 | Chen Huang 0005, Frank Vahid |
Transmuting coprocessors: dynamic loading of FPGA coprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 46th Design Automation Conference, DAC 2009, San Francisco, CA, USA, July 26-31, 2009, pp. 848-851, 2009, ACM, 978-1-60558-497-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
coprocessing, FPGAs, online algorithms, dynamic optimization, acceleration, runtime configuration |
60 | Fei Sun, Srivaths Ravi 0001, Anand Raghunathan, Niraj K. Jha |
A Synthesis Methodology for Hybrid Custom Instruction and Coprocessor Generation for Extensible Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(11), pp. 2035-2045, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
57 | Miljan Vuletic, Laura Pozzi, Paolo Ienne |
Dynamic Prefetching in the Virtual Memory Window of Portable Reconfigurable Coprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field Programmable Logic and Application, 14th International Conference , FPL 2004, Leuven, Belgium, August 30-September 1, 2004, Proceedings, pp. 596-605, 2004, Springer, 3-540-22989-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
48 | Chen Huang 0005, Frank Vahid |
Server-side coprocessor updating for mobile devices with FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, FPGA 2010, Monterey, California, USA, February 21-23, 2010, pp. 125-134, 2010, ACM, 978-1-60558-911-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
coprocessing, fpgas, dynamic optimization, acceleration |
48 | David W. Kravitz, Kim-Ee Yeoh, Nicol So |
Secure Open Systems for Protecting Privacy and Digital Services. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Digital Rights Management Workshop ![In: Security and Privacy in Digital Rights Management, ACM CCS-8 Workshop DRM 2001, Philadelphia, PA, USA, November 5, 2001, Revised Papers, pp. 106-125, 2001, Springer, 3-540-43677-4. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
46 | Klaus E. Schauser, Chris J. Scheiman, J. Mitchell Ferguson, Paul Z. Kolano |
Exploiting the Capabilities of Communications Co-Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPPS ![In: Proceedings of IPPS '96, The 10th International Parallel Processing Symposium, April 15-19, 1996, Honolulu, Hawaii, USA, pp. 109-115, 1996, IEEE Computer Society, 0-8186-7255-2. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
inter-computer links, communications coprocessor architecture, dedicated hardware support, user-level message handlers, Split-C, message handling code, Meiko CS-2 platform, synchronization, parallel architectures, local area networks, synchronisation, flexibility, coprocessors, computational power, massively parallel processors, workstation networks, active messages, electronic messaging |
45 | Bishwaranjan Bhattacharjee, Naoki Abe, Kenneth A. Goldman, Bianca Zadrozny, Vamsavardhana R. Chillakuru, Marysabel del Carpio, Chidanand Apté |
Using secure coprocessors for privacy preserving collaborative data mining and analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DaMoN ![In: Workshop on Data Management on New Hardware, DaMoN 2006, Chicago, Illinois, USA, June 25, 2006, pp. 1, 2006, ACM, 1-59593-466-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
data mining, privacy, collaboration, federation |
45 | Miljan Vuletic, Ludovic Righetti, Laura Pozzi, Paolo Ienne |
Operating System Support for Interface Virtualisation of Reconfigurable Coprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France, pp. 748, 2004, IEEE Computer Society, 0-7695-2085-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
45 | Domingo Benitez |
Performance of Remote FPGA-Based Coprocessors for Image-Processing Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 2002 Euromicro Symposium on Digital Systems Design (DSD 2002), Systems-on-Chip, 4-6 September 2002, Dortmund, Germany, pp. 268-275, 2002, IEEE Computer Society, 0-7695-1790-0. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
42 | Sean W. Smith |
Outbound authentication for programmable secure coprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Inf. Sec. ![In: Int. J. Inf. Sec. 3(1), pp. 28-41, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Secure coprocessors, Authentication, Trust, Attestation |
42 | Miljan Vuletic, Laura Pozzi, Paolo Ienne |
Virtual memory window for application-specific reconfigurable coprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004, pp. 948-953, 2004, ACM, 1-58113-828-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
reconfigurable computing, codesign, coprocessors, OS |
42 | Naren Narasimhan, Vinoo Srinivasan, Madhavi Vootukuru, Jeffrey Walrath, Sriram Govindarajan, Ranga Vemuri |
Rapid Prototyping of Reconfigurable Coprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 1996 International Conference on Application-Specific Systems, Architectures, and Processors (ASAP '96), August 19-23, 1996, Chicago, IL , USA, pp. 303-312, 1996, IEEE Computer Society, 0-8186-7542-X. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
Prototyping, High-level Synthesis, JPEG, Coprocessors, Hardware-Software Co-design, Software Profiling |
36 | Yi-Neng Lin, Ying-Dar Lin, Kuo-Kun Tseng, Yuan-Cheng Lai |
Modeling and analysis of core-centric network processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Embed. Comput. Syst. ![In: ACM Trans. Embed. Comput. Syst. 8(2), pp. 13:1-13:15, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
core-centric, simulation, modeling, embedded system, Network processor |
36 | Yi-Neng Lin, Ying-Dar Lin, Yuan-Cheng Lai, Kuo-Kun Tseng |
Modeling and analysis of core-centric network processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Embed. Comput. Syst. ![In: ACM Trans. Embed. Comput. Syst. 7(4), pp. 41:1-41:15, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
core-centric, simulation, modeling, embedded system, Network processor |
36 | Lance Saldanha, Roman L. Lysecky |
Hardware/software partitioning of floating point software applications to fixed-pointed coprocessor circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 6th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2008, Atlanta, GA, USA, October 19-24, 2008, pp. 49-54, 2008, ACM, 978-1-60558-470-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
floating point to fixed conversion, floating point, fixed point, hardware/software partitioning |
36 | Jason Cong, Karthik Gururaj, Guoling Han, Adam Kaplan, Mishali Naik, Glenn Reinman |
MC-Sim: an efficient simulation tool for MPSoC designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2008 International Conference on Computer-Aided Design, ICCAD 2008, San Jose, CA, USA, November 10-13, 2008, pp. 364-371, 2008, IEEE Computer Society, 978-1-4244-2820-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
36 | Pranav Vaidya, Jaehwan John Lee |
Simulation of hybrid computer architectures: simulators, methodologies and recommendations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: IFIP VLSI-SoC 2007, IFIP WG 10.5 International Conference on Very Large Scale Integration of System-on-Chip, Atlanta, GA, USA, 15-17 October 2007, pp. 157-162, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
36 | Martijn J. Rutten, Jos T. J. van Eijndhoven, Evert-Jan D. Pol |
Design of multi-tasking coprocessor control for Eclipse. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES ![In: Proceedings of the Tenth International Symposium on Hardware/Software Codesign, CODES 2002, Estes Park, Colorado, USA, May 6-8, 2002, pp. 139-144, 2002, ACM, 1-58113-542-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
33 | Frédéric Amiel, Benoit Feix, Karine Villegas |
Power Analysis for Secret Recovering and Reverse Engineering of Public Key Algorithms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Selected Areas in Cryptography ![In: Selected Areas in Cryptography, 14th International Workshop, SAC 2007, Ottawa, Canada, August 16-17, 2007, Revised Selected Papers, pp. 110-125, 2007, Springer, 978-3-540-77359-7. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
arithmetic coprocessors, reverse engineering, Public key cryptography, side-channel analysis, exponentiation |
33 | Richard S. Wallace, Michael D. Howard |
HBA Vision Architecture: Built and Benchmarked. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Pattern Anal. Mach. Intell. ![In: IEEE Trans. Pattern Anal. Mach. Intell. 11(3), pp. 227-232, 1989. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
vision architecture, hierarchical bus architecture, algorithmic benchmarks, local neighborhood operations, Apply, image-to-image transformations, floating-point coprocessors, computer vision, computer vision, parallel processing, parallel architectures, software tools, programming environment, programming environments, computerised picture processing, programming model, looping, boundary conditions |
33 | Xu Guo 0001, Zhimin Chen 0002, Patrick Schaumont |
Energy and Performance Evaluation of an FPGA-Based SoC Platform with AES and PRESENT Coprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAMOS ![In: Embedded Computer Systems: Architectures, Modeling, and Simulation, 8th International Workshop, SAMOS 2008, Samos, Greece, July 21-24, 2008. Proceedings, pp. 106-115, 2008, Springer, 978-3-540-70549-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
33 | Jin Ho Ha, Jin Soo Kim, Myung Hoon Sunwoo |
AN ASIP Approach for H.264/AVC Implementation Having Novel Coprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SiPS ![In: Proceedings of the IEEE Workshop on Signal Processing Systems, SiPS 2007, Proceedings, October 17-19, 2007, Eton Hotel, Shanghai, China, pp. 499-504, 2007, IEEE, 1-4244-1222-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
33 | Miljan Vuletic, Laura Pozzi, Paolo Ienne |
Virtual memory window for application-specific reconfigurable coprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 14(8), pp. 910-915, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
33 | Patrick Schaumont, Doris Ching, Ingrid Verbauwhede |
An interactive codesign environment for domain-specific coprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 11(1), pp. 70-87, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
hardware description language, hardware-software codesign, Cosimulation |
33 | Carsten Albrecht, Andreas C. Döring, Frank Penczek, Torben Schneider, Hannes Schulz |
Impact of Coprocessors on a Multithreaded Processor Design Using Prioritized Threads. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PDP ![In: 14th Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP 2006), 15-17 February 2006, Montbeliard-Sochaux, France, pp. 109-115, 2006, IEEE Computer Society, 0-7695-2513-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
33 | Björn Griese, Boris Kettelhoit, Mario Porrmann |
Evaluation of On-Chip Interfaces for Dynamically Reconfigurable Coprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PARELEC ![In: Fifth International Conference on Parallel Computing in Electrical Engineering (PARELEC 2006), 13-17 September 2006, Bialystok, Poland, pp. 214-219, 2006, IEEE Computer Society, 0-7695-2554-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
33 | Thomas J. Wollinger, Guido Bertoni, Luca Breveglieri, Christof Paar |
Performance of HECC Coprocessors Using Inversion-Free Formulae. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCSA (3) ![In: Computational Science and Its Applications - ICCSA 2006, International Conference, Glasgow, UK, May 8-11, 2006, Proceedings, Part III, pp. 1004-1012, 2006, Springer, 3-540-34075-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
33 | Haidong Xia, Jayashree Kanchana, José Carlos Brustoloni |
Using Secure Coprocessors to Protect Access to Enterprise Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NETWORKING ![In: NETWORKING 2005: Networking Technologies, Services, and Protocols; Performance of Computer and Communication Networks; Mobile and Wireless Communication Systems, 4th International IFIP-TC6 Networking Conference, Waterloo, Canada, May 2-6, 2005, Proceedings, pp. 154-165, 2005, Springer, 3-540-25809-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
33 | MinYong Jeon, Hyunil Byun, JooHo Ha, KiTaek Lee, JooHyoung Kim, JiYoung Seo, KyungWoo Lee, SeungHo Lee |
A system-on-chip featuring variable bus architecture and enhanced video coprocessors for MPEG-4 multimedia applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (2) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 780-783, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
33 | Martijn J. Rutten, Jos T. J. van Eijndhoven, Evert-Jan D. Pol |
Robust Media Processing in a Flexible and Cost-Effective Network of Multi-Tasking Coprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ECRTS ![In: 14th Euromicro Conference on Real-Time Systems (ECRTS 2002), 19-21 June 2002, Vienna, Austria, Proceedings, pp. 223-230, 2002, IEEE Computer Society, 0-7695-1665-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
33 | Stephen Charlwood, Jonathan Mangnall, Steven F. Quigley |
System-Level Modelling for Performance Estimation of Reconfigurable Coprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, Reconfigurable Computing Is Going Mainstream, 12th International Conference, FPL 2002, Montpellier, France, September 2-4, 2002, Proceedings, pp. 567-576, 2002, Springer, 3-540-44108-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
33 | Juan Carlos López 0001, Fernando Rincón, Francisco Moya, José Manuel Moya |
Improving Embedded System Design by Means of HW-SW Compilation on Reconfigurable Coprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSS ![In: Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), October 2-4, 2002, Kyoto, Japan, pp. 255-260, 2002, ACM / IEEE Computer Society, 1-58113-576-9. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
reconfigurable datapaths, hardware-software codesign |
33 | Takashi Miyamori, Kunle Olukotun |
A Quantitative Analysis of Reconfigurable Coprocessors for Multimedia Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 6th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '98), 15-17 April 1998, Napa Valley, CA, USA, pp. 2-11, 1998, IEEE Computer Society, 0-8186-8900-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
33 | Martin C. Herbordt, Owais Kidwai, Charles C. Weems |
Preprototyping SIMD Coprocessors Using Virtual Machine Emulation and Trace Compilation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGMETRICS ![In: Proceedings of the 1997 ACM SIGMETRICS international conference on Measurement and modeling of computer systems, Seattle, Washington, USA, June 15-18, 1997, pp. 88-99, 1997, ACM, 0-89791-909-2. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
24 | John H. Kelm, Isaac Gelado, Mark J. Murphy, Nacho Navarro, Steven S. Lumetta, Wen-mei W. Hwu |
CIGAR: Application Partitioning for a CPU/Coprocessor Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PACT ![In: 16th International Conference on Parallel Architectures and Compilation Techniques (PACT 2007), Brasov, Romania, September 15-19, 2007, pp. 317-326, 2007, IEEE Computer Society, 0-7695-2944-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
24 | Christopher Claus, Johannes Zeppenfeld, Florian Helmut Müller, Walter Stechele |
Using partial-run-time reconfigurable hardware to accelerate video processing in driver assistance system. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2007 Design, Automation and Test in Europe Conference and Exposition, DATE 2007, Nice, France, April 16-20, 2007, pp. 498-503, 2007, EDA Consortium, San Jose, CA, USA, 978-3-9810801-2-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
24 | Giovanni Agosta, Luca Breveglieri, Gerardo Pelosi, Martino Sykora |
Programming Highly Parallel Reconfigurable Architectures for Public-Key Cryptographic Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITNG ![In: Fourth International Conference on Information Technology: New Generations (ITNG 2007), 2-4 April 2007, Las Vegas, Nevada, USA, pp. 3-10, 2007, IEEE Computer Society, 978-0-7695-2776-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
24 | Henrik Svensson, Thomas Lenart, Viktor Öwall |
Accelerating Vector Operations by Utilizing Reconfigurable Coprocessor Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 3972-3975, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
24 | Dong-Ho Lee, Jong-Soo Oh |
Multi-segment GF(2m) multiplication and its application to elliptic curve cryptography. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, Stresa, Lago Maggiore, Italy, March 11-13, 2007, pp. 546-551, 2007, ACM, 978-1-59593-605-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
elliptic curve scalar multiplication, FPGA, elliptic curve cryptography (ECC), coprocessor, finite field multiplication |
24 | David Sheldon, Rakesh Kumar 0002, Frank Vahid, Dean M. Tullsen, Roman L. Lysecky |
Conjoining soft-core FPGA processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2006 International Conference on Computer-Aided Design, ICCAD 2006, San Jose, CA, USA, November 5-9, 2006, pp. 694-701, 2006, ACM, 1-59593-389-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
conjoined processors, parameterized platforms, soft-core processors, FPGAs, customization, tuning |
24 | Ivan Augé, Frédéric Pétrot, François Donnet, Pascal Gomez |
Platform-based design from parallel C specifications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(12), pp. 1811-1826, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
24 | Seng Lin Shee, Sri Parameswaran, Newton Cheung |
Novel architecture for loop acceleration: a case study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2005, Jersey City, NJ, USA, September 19-21, 2005, pp. 297-302, 2005, ACM, 1-59593-161-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
tightly coupled, architecture, ASIP, hardware/software partitioning, coprocessor, loop optimization, latency hiding, loop pipelining, loop acceleration |
24 | Martin Seysen |
Using an RSA Accelerator for Modular Inversion. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHES ![In: Cryptographic Hardware and Embedded Systems - CHES 2005, 7th International Workshop, Edinburgh, UK, August 29 - September 1, 2005, Proceedings, pp. 226-236, 2005, Springer, 3-540-28474-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Smart card coprocessor, Euclidean algorithm, modular inversion |
24 | Howon Kim 0001, Mun-Kyu Lee, Dong Kyue Kim, Sang-Kyoon Chung, Kyoil Chung |
Design and Implementation of Crypto Co-processor and Its Application to Security Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CIS (2) ![In: Computational Intelligence and Security, International Conference, CIS 2005, Xi'an, China, December 15-19, 2005, Proceedings, Part II, pp. 1104-1109, 2005, Springer, 3-540-30819-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Crypto Algorithm, Power Consumption, Crypto Coprocessor |
24 | Andrew Morton, Wayne M. Loucks |
A hardware/software kernel for system on chip designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAC ![In: Proceedings of the 2004 ACM Symposium on Applied Computing (SAC), Nicosia, Cyprus, March 14-17, 2004, pp. 869-875, 2004, ACM, 1-58113-812-1. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
operating systems, SoC, hardware/software codesign |
24 | Leandro Möller, Ney Laert Vilar Calazans, Fernando Gehm Moraes, Eduardo Wenzel Brião, Ewerson Carvalho, Daniel Camozzato |
FiPRe: An Implementation Model to Enable Self-Reconfigurable Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field Programmable Logic and Application, 14th International Conference , FPL 2004, Leuven, Belgium, August 30-September 1, 2004, Proceedings, pp. 1042-1046, 2004, Springer, 3-540-22989-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
24 | Miljan Vuletic, Laura Pozzi, Paolo Ienne |
Virtual Memory Window for a Portable Reconfigurable Cryptography Coprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 12th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2004), 20-23 April 2004, Napa, CA, USA, Proceedings, pp. 24-33, 2004, IEEE Computer Society, 0-7695-2230-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
24 | Newton Cheung, Jörg Henkel, Sri Parameswaran |
Rapid Configuration and Instruction Selection for an ASIP: A Case Study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2003 Design, Automation and Test in Europe Conference and Exposition (DATE 2003), 3-7 March 2003, Munich, Germany, pp. 10802-10809, 2003, IEEE Computer Society, 0-7695-1870-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
24 | Matthias Dyer, Christian Plessl, Marco Platzner |
Partially Reconfigurable Cores for Xilinx Virtex. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, Reconfigurable Computing Is Going Mainstream, 12th International Conference, FPL 2002, Montpellier, France, September 2-4, 2002, Proceedings, pp. 292-301, 2002, Springer, 3-540-44108-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
24 | Anatoly E. Voevudko |
Steps Toward Next Generation Computer Based Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ECBS ![In: 6th Symposium on Engineering of Computer-Based Systems (ECBS '99), 7-12 March 1999, Nashville, TN, USA. IEEE Computer Society, 1999, pp. 270-276, 1999, IEEE Computer Society, 0-7695-0028-5. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
Processor based architecture, unified linguistic and access support, scripting and programming languages, distributed systems, integration, operating systems, software, hardware, portability, Web-based systems |
24 | Rolf Ernst, Kees A. Vissers, Pieter van der Wolf, Gert-Jan van Rootselaar |
System level design and debug of high-performance embedded media systems (tutorial). ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999, San Jose, California, USA, November 7-11, 1999, pp. 461, 1999, IEEE Computer Society, 0-7803-5832-5. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP BibTeX RDF |
|
24 | Timothy J. Callahan, John Wawrzynek |
Instruction-Level Parallelism for Reconfigurable Computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, From FPGAs to Computing Paradigm, 8th International Workshop, FPL'98, Tallinn, Estonia, August 31 - September 3, 1998, Proceedings, pp. 248-257, 1998, Springer, 3-540-64948-4. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
24 | Peter Steenkiste |
Analyzing Communication Latency Using the Nectar Communication Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGCOMM ![In: Proceedings of the Conference on Communications Architecture & Protocols, SIGCOMM 1992, Baltimore, Maryland, USA, August 17-20, 1992, pp. 199-209, 1992, ACM, 0-89791-525-9. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
SPARC |
21 | Tony M. Brewer |
Instruction Set Innovations for the Convey HC-1 Computer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Micro ![In: IEEE Micro 30(2), pp. 70-79, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
hybrid-core computing, FPGAs, reconfigurable computing, heterogeneous computing, accelerators, coprocessors, instruction set design |
21 | Liang Ma, Caijun Zhen, Bin Zhao, Jingwei Ma, Gang Wang 0001, Xiaoguang Liu 0001 |
Towards Fast De-duplication Using Low Energy Coprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NAS ![In: Fifth International Conference on Networking, Architecture, and Storage, NAS 2010, Macau, China, July 15-17, 2010, pp. 395-402, 2010, IEEE Computer Society, 978-0-7695-4134-1. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
De-duplication, Commodity coprocessors, Computing complexity, Low energy |
21 | Atabak Mahram, Martin C. Herbordt |
Fast and accurate NCBI BLASTP: acceleration with multiphase FPGA-based prefiltering. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICS ![In: Proceedings of the 24th International Conference on Supercomputing, 2010, Tsukuba, Ibaraki, Japan, June 2-4, 2010, pp. 73-82, 2010, ACM, 978-1-4503-0018-6. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
FPGA-based coprocessors, high performance reconfigurable computing, bioinformatics, biological sequence alignment |
21 | Paul E. Marks, Cameron D. Patterson |
Data streaming and simd support for the microblaze architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, FPGA 2009, Monterey, California, USA, February 22-24, 2009, pp. 277, 2009, ACM, 978-1-60558-410-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
streaming coprocessors, vector units, reconfigurability |
21 | Masayuki Yoshino, Katsuyuki Okeya, Camille Vuillaume |
Recursive Double-Size Modular Multiplications without Extra Cost for Their Quotients. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CT-RSA ![In: Topics in Cryptology - CT-RSA 2009, The Cryptographers' Track at the RSA Conference 2009, San Francisco, CA, USA, April 20-24, 2009. Proceedings, pp. 340-356, 2009, Springer, 978-3-642-00861-0. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
low-end device, double-size technique, RSA, modular multiplication, efficient implementation, crypto-coprocessors, arithmetic unit |
21 | Partha Biswas, Nikil D. Dutt |
Code Size Reduction in Heterogeneous-Connectivity-Based DSPs Using Instruction Set Extensions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 54(10), pp. 1216-1226, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
DSP, VLIW, ASIP, Coprocessors, instruction set extensions, code size reduction |
21 | Partha Biswas, Vinay Choudhary, Kubilay Atasu, Laura Pozzi, Paolo Ienne, Nikil D. Dutt |
Introduction of local memory elements in instruction set extensions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004, pp. 729-734, 2004, ACM, 1-58113-828-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
ad-hoc functional units, genetic algorithm, ASIPs, coprocessors, instruction set extensions, customizable processors |
21 | S. Ramanathan, S. K. Nandy 0001, V. Visvanathan |
Reconfigurable Filter Coprocessor Architecture for DSP Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 26(3), pp. 333-359, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
reconfigurable coprocessors, filter coprocessor architecture, systolic architectures and digital signal processing, pipelined architectures, low-power architectures |
21 | Nalini K. Ratha, Anil K. Jain 0001, Diane T. Rover |
FPGA-Based Coprocessor for Text String Extraction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAMP ![In: Fifth International Workshop on Computer Architectures for Machine Perception (CAMP 2000), September 11-13, 2000, Padova, Italy, pp. 217-221, 2000, IEEE Computer Society, 0-7695-0740-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
FPGA-based coprocessor, text string extraction, image morphology based algorithms, high-performance coprocessor, Splash 2, Sun hosts, VHDL behavioral modeling, SPARC station 20, design patterns, coprocessors, document understanding, visual effects |
21 | Chi-Min Lin, Tien-Fu Chen |
Dynamic memory management for real-time embedded Java chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RTCSA ![In: 7th International Workshop on Real-Time Computing and Applications Symposium (RTCSA 2000), 12-14 December 2000, Cheju Island, South Korea, pp. 49-56, 2000, IEEE Computer Society, 0-7695-0930-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
storage management chips, dynamic runtime memory management, real-time embedded Java chips, CPU design, hardware-assisted scheme, dynamic garbage collection mechanism, predictable memory allocation time, data transition events, circular heap, simulation, Java, embedded systems, response time, memory architecture, memory architecture, storage allocation, coprocessors, resource constraints, real-time constraints, co-processor |
21 | Jean-Luis Dufour |
Safety computations in integrated circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 14th IEEE VLSI Test Symposium (VTS'96), April 28 - May 1, 1996, Princeton, NJ, USA, pp. 169-173, 1996, IEEE Computer Society, 0-8186-7304-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
safety computations, software-based railway control systems, MATRA TRANSPORT, signature checking, coded processor, reliability, fault tolerant computing, logic testing, redundancy, integrated circuit testing, error correction codes, automatic testing, application specific integrated circuits, ASICs, integrated circuits, coprocessors, arithmetic coding, integrated circuit reliability |
21 | Michael S. Allen, W. Kurt Lewchuk, J. D. Coddington |
A high performance bus and cache controller for PowerPC multiprocessing systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1995 International Conference on Computer Design (ICCD '95), VLSI in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings, pp. 204-211, 1995, IEEE Computer Society, 0-8186-7165-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
high performance bus, cache controller, PowerPC 620 microprocessor, system bus interface, ECC protected, server-class systems, physical address bus, data bus, address transfer rates, address snoop response, direct cache-to-cache data transfers, 2 GByte/s, 133 MHz, 128 MB, performance evaluation, pipelining, multiprocessing systems, multiprocessing systems, pipeline processing, cache storage, microprocessor chips, coprocessors, cache coherency protocol, data transfer, PowerPC, system buses, co-processor |
21 | Michael J. Schulte, Earl E. Swartzlander Jr. |
A coprocessor for accurate and reliable numerical computations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1995 International Conference on Computer Design (ICCD '95), VLSI in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings, pp. 686-691, 1995, IEEE Computer Society, 0-8186-7165-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
reliable numerical computations, direct hardware support, logic design, digital arithmetic, interval arithmetic, hardware design, coprocessors, coprocessor, numerical computations |
21 | Ali Skaf, Alain Guyot |
SAGA: the first general-purpose on-line arithmetic co-processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 146-149, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
general-purpose co-processor, online arithmetic coprocessor, VLSI realisation, BKM algorithm, complex logarithm function, complex exponential function, VLSI, arithmetic, coprocessors, CMOS digital integrated circuits, redundant number systems, CMOS IC, SAGA |
21 | Leonardo Campanale, Mario De Blasi, Anna Gentile, F. Greco |
Topologies for the parallel backtracking Prolog engine. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 23rd Annual Workshop and Symposium on Microprogramming and Microarchitecture, 1990, Orlando, Florida, USA, November 27-29, 1990, pp. 237-242, 1990, ACM/IEEE, 0-89791-413-9. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP BibTeX RDF |
Prolog machines, backup or-parallelism, distributed systems, topologies, coprocessors, transputers, Occam, multicomputer networks |
21 | CMS Collaboration |
Portable acceleration of CMS computing workflows with coprocessors as a service. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2402.15366, 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
21 | Dhiman Chakraborty 0001, Michael Schwarz 0001, Sven Bugiel |
TALUS: Reinforcing TEE Confidentiality with Cryptographic Coprocessors (Technical Report). ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2306.03643, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
21 | Dhiman Chakraborty 0001, Michael Schwarz 0001, Sven Bugiel |
TALUS: Reinforcing TEE Confidentiality with Cryptographic Coprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FC (1) ![In: Financial Cryptography and Data Security - 27th International Conference, FC 2023, Bol, Brač, Croatia, May 1-5, 2023, Revised Selected Papers, Part I, pp. 147-165, 2023, Springer, 978-3-031-47753-9. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
21 | Balazs Udvarhelyi, François-Xavier Standaert |
Leveraging Coprocessors as Noise Engines in Off-the-Shelf Microcontrollers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CARDIS ![In: Smart Card Research and Advanced Applications - 22nd International Conference, CARDIS 2023, Amsterdam, The Netherlands, November 14-16, 2023, Revised Selected Papers, pp. 148-165, 2023, Springer, 978-3-031-54408-8. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
21 | Jong-Yeon Park, Yong-Hyuk Moon, Won-Il Lee, Sung-Hyun Kim, Kouichi Sakurai |
A Survey of Polynomial Multiplication With RSA-ECC Coprocessors and Implementations of NIST PQC Round3 KEM Algorithms in Exynos2100. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 10, pp. 2546-2563, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
21 | Ferruccio Damiani, Luca Paolini, Luca Roversi |
Programming the Interaction with Quantum Coprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ERCIM News ![In: ERCIM News 2022(128), 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP BibTeX RDF |
|
21 | Jorge Reis, Jarbas Silveira, César A. M. Marcon |
Impact of failures in a MPSoC with shared coprocessors to extend the RISC-V ISA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LADC ![In: Proceedings of the 11th Latin-American Symposium on Dependable Computing, LADC 2022, Fortaleza/CE, Brazil, November 21-24, 2022, pp. 29-34, 2022, ACM, 978-1-4503-9737-7. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
21 | Yaroslav Nykolaychuk, Volodymyr Hryha, Natalia Vozna, Artur Voronych, Andriy Segin, Petro Humennyi |
High-performance Coprocessors for Arithmetic and Logic Operations of Multi-Bit Cores for Vector and Scalar Supercomputers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACIT ![In: 12th International Conference on Advanced Computer Information Technologies, ACIT 2022, Ruzomberok, Slovakia, September 26-28, 2022, pp. 410-414, 2022, IEEE, 978-1-6654-1049-6. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
21 | Tim Fritzmann |
Towards Secure Coprocessors and Instruction Set Extensions for Acceleration of Post-Quantum Cryptography. ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2022 |
RDF |
|
21 | Abdallah Cheikh, Stefano Sordillo, Antonio Mastrandrea, Francesco Menichelli, Giuseppe Scotti, Mauro Olivieri |
Klessydra-T: Designing Vector Coprocessors for Multithreaded Edge-Computing Cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Micro ![In: IEEE Micro 41(2), pp. 64-71, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
21 | Anirban Sengupta, Rahul Chaurasia, Tarun Reddy |
Contact-Less Palmprint Biometric for Securing DSP Coprocessors Used in CE Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Consumer Electron. ![In: IEEE Trans. Consumer Electron. 67(3), pp. 202-213, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
21 | Olivier Bronchain, Charles Momin, Thomas Peters, François-Xavier Standaert |
Improved Leakage-Resistant Authenticated Encryption based on Hardware AES Coprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IACR Trans. Cryptogr. Hardw. Embed. Syst. ![In: IACR Trans. Cryptogr. Hardw. Embed. Syst. 2021(3), pp. 641-676, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
21 | Jeffrey D. Krupa, Kelvin Lin, Maria Acosta Flechas, Jack Dinsmore, Javier M. Duarte, Philip C. Harris, Scott Hauck, Burt Holzman, Shih-Chieh Hsu, Thomas Klijnsma, Mia Liu, Kevin Pedro, Dylan S. Rankin, Natchanon Suaysom, Matt Trahms, Nhan Tran |
GPU coprocessors as a service for deep learning inference in high energy physics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Mach. Learn. Sci. Technol. ![In: Mach. Learn. Sci. Technol. 2(3), pp. 35005, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
21 | Alexander Antonov |
Inferring Custom Synthesizable Kernel for Generation of Coprocessors with Out-of-Order Execution. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MECO ![In: 10th Mediterranean Conference on Embedded Computing, MECO 2021, Budva, Montenegro, June 7-10, 2021, pp. 1-4, 2021, IEEE, 978-1-6654-3912-1. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
21 | Jeffrey D. Krupa, Kelvin Lin, Maria Acosta Flechas, Jack Dinsmore, Javier M. Duarte, Philip C. Harris, Scott Hauck, Burt Holzman, Shih-Chieh Hsu, Thomas Klijnsma, Mia Liu, Kevin Pedro, Natchanon Suaysom, Matt Trahms, Nhan Tran |
GPU coprocessors as a service for deep learning inference in high energy physics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2007.10359, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP BibTeX RDF |
|
21 | Abdallah Cheikh, Stefano Sordillo, Antonio Mastrandrea, Francesco Menichelli, Giuseppe Scotti, Mauro Olivieri |
Klessydra-T: Designing Vector Coprocessors for Multi-Threaded Edge-Computing Cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2007.09109, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP BibTeX RDF |
|
21 | Sebastian Baunsgaard, Sebastian Benjamin Wrede, Pinar Tözün |
Training for Speech Recognition on Coprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2003.12366, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP BibTeX RDF |
|
21 | Nouredine Melab, Jan Gmys, Mohand Mezmaz, Daniel Tuyttens |
Many-Core Branch-and-Bound for GPU Accelerators and MIC Coprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
High-Performance Simulation-Based Optimization ![In: High-Performance Simulation-Based Optimization, pp. 275-291, 2020, Springer, 978-3-030-18763-7. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
21 | Sebastian Baunsgaard, Sebastian Benjamin Wrede, Pinar Tözün |
Training for Speech Recognition on Coprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ADMS@VLDB ![In: International Workshop on Accelerating Analytics and Data Management Systems Using Modern Processor and Storage Architectures, ADMS@VLDB 2020, Tokyo, Japan, August 31, 2020., pp. 1-10, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP BibTeX RDF |
|
21 | Bryan Pearson, Cliff C. Zou, Yue Zhang 0025, Zhen Ling, Xinwen Fu |
SIC2: Securing Microcontroller Based IoT Devices with Low-cost Crypto Coprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPADS ![In: 26th IEEE International Conference on Parallel and Distributed Systems, ICPADS 2020, Hong Kong, December 2-4, 2020, pp. 372-381, 2020, IEEE, 978-1-7281-9074-7. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
21 | Pedro Lima, Caio Vieira, Jorge Reis, Alexandre Almeida, Jarbas Silveira, Roger C. Goerl, César A. M. Marcon |
Optimizing RISC-V ISA Usage by Sharing Coprocessors on MPSoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATS ![In: IEEE Latin-American Test Symposium, LATS 2020, Maceio, Brazil, March 30 - April 2, 2020, pp. 1-5, 2020, IEEE, 978-1-7281-8731-0. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
21 | Valerii Hlukhov |
Comparison of Homogeneous and Heterogeneous Digital Quantum Coprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CSIT (2) ![In: IEEE 15th International Conference on Computer Sciences and Information Technologies, CSIT 2020, Zbarazh, Ukraine, September 23-26, 2020 - Volume 2, pp. 70-73, 2020, IEEE, 978-1-7281-7443-3. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
21 | Putt Sakdhnagool, Amit Sabne, Rudolf Eigenmann |
Comparative analysis of coprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Concurr. Comput. Pract. Exp. ![In: Concurr. Comput. Pract. Exp. 31(1), 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
21 | J. L. Campon, Luis Landesa |
Fast solution of electromagnetic scattering problems using Xeon Phi coprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Supercomput. ![In: J. Supercomput. 75(1), pp. 370-383, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
21 | Niels Pirotte, Jo Vliegen, Lejla Batina, Nele Mentens |
Balancing elliptic curve coprocessors from bottom to top. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microprocess. Microsystems ![In: Microprocess. Microsystems 71, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
21 | Daniel Etiemble |
Coprocessors: failures and successes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1907.06948, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP BibTeX RDF |
|
21 | Wenpeng Ma, Wu Yuan 0002, Xiaodong Hu |
Implementation and Optimization of a CFD Solver Using Overlapped Meshes on Multiple MIC Coprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Sci. Program. ![In: Sci. Program. 2019, pp. 4254676:1-4254676:12, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
21 | Jason Staggs, Sujeet Shenoi |
Securing Wireless Coprocessors from Attacks in the Internet of Things. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Critical Infrastructure Protection ![In: Critical Infrastructure Protection XIII - 13th IFIP WG 11.10 International Conference, ICCIP 2019, Arlington, VA, USA, March 11-12, 2019, Revised Selected Papers, pp. 159-178, 2019, Springer, 978-3-030-34646-1. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
21 | Christopher P. Stone, Andrew T. Alferman, Kyle E. Niemeyer |
Accelerating finite-rate chemical kinetics with coprocessors: Comparing vectorization methods on GPUs, MICs, and CPUs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Comput. Phys. Commun. ![In: Comput. Phys. Commun. 226, pp. 18-29, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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