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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 72 occurrences of 59 keywords
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Results
Found 65 publication records. Showing 65 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
161 | R. Miller, Hal Carter, K. Davis, Satish Venkatesan |
Hardware/software cosynthesis: multiple constraint satisfaction and component retrieval. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECCS ![In: 2nd IEEE International Conference on Engineering of Complex Computer Systems (ICECCS '96), 21-25 October 1996, Montreal, Canada, pp. 383-390, 1996, IEEE Computer Society, 0-8186-7614-0. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
hardware software cosynthesis, multiple constraint satisfaction, high-level system specification, constraint-driven retrieval, candidate solution evaluation, cosynthesis tool, multiple design constraints, two constraint Fidducia-Matheyses approach, flexible component retrieval, design database, ad hoc querying, systems analysis, hardware description language, design space, component retrieval |
130 | Ilya Issenin, Erik Brockmeyer, Bart Durinck, Nikil D. Dutt |
Data-Reuse-Driven Energy-Aware Cosynthesis of Scratch Pad Memory and Hierarchical Bus-Based Communication Architecture for Multiprocessor Streaming Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(8), pp. 1439-1452, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
130 | Bharat P. Dave, Niraj K. Jha |
COHRA: hardware-software cosynthesis of hierarchical heterogeneous distributed embedded systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(10), pp. 900-919, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
102 | Hyunok Oh, Soonhoi Ha |
Hardware-software cosynthesis of multi-mode multi-task embedded systems with real-time constraints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES ![In: Proceedings of the Tenth International Symposium on Hardware/Software Codesign, CODES 2002, Estes Park, Colorado, USA, May 6-8, 2002, pp. 133-138, 2002, ACM, 1-58113-542-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
hardware-software cosynthesis, multi-task, multi-mode |
95 | Gul N. Khan, Usman Ahmed |
Hardware-Software Cosynthesis of Multiprocessor Embedded Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AINA Workshops (1) ![In: 21st International Conference on Advanced Information Networking and Applications (AINA 2007), Workshops Proceedings, Volume 1, May 21-23, 2007, Niagara Falls, Canada, pp. 804-810, 2007, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
85 | Pao-Ann Hsiung |
CMAPS: a cosynthesis methodology for application-oriented parallel systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 5(1), pp. 51-81, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
application-oriented general-purpose multiprocessors, hardware-software modeling and cosynthesis, requirements analysis |
78 | Chen-Wei Liu, Yao-Wen Chang |
Power/Ground Network and Floorplan Cosynthesis for Fast Design Convergence. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(4), pp. 693-704, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
68 | Minyoung Kim, Sudarshan Banerjee, Nikil D. Dutt, Nalini Venkatasubramanian |
Energy-aware cosynthesis of real-time multimedia applications on MPSoCs using heterogeneous scheduling policies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Embed. Comput. Syst. ![In: ACM Trans. Embed. Comput. Syst. 7(2), pp. 9:1-9:19, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
cosynthesis, energy, Real-time scheduling, MPSoC |
68 | Jörg Henkel, Rolf Ernst |
A path-based technique for estimating hardware runtime in HW/SW-cosynthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSS ![In: Proceedings of the 8th International Symposium on System Synthesis (ISSS 1995), September 13-15, 1995, Cannes, France, pp. 116-121, 1995, ACM, 0-89791-771-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
hardware runtime, hardware software cosynthesis, local estimation techniques, local list scheduling, path-based technique, scheduling, computational complexity, computer architecture, quality, systems analysis, circuit CAD, computation time, optimising compilers, synthesis tools |
61 | Li Shang, Robert P. Dick, Niraj K. Jha |
SLOPES: Hardware-Software Cosynthesis of Low-Power Real-Time Distributed Embedded Systems With Dynamically Reconfigurable FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(3), pp. 508-526, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
61 | Robert P. Dick, Niraj K. Jha |
MOGAC: a multiobjective genetic algorithm for hardware-software cosynthesis of distributed embedded systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(10), pp. 920-935, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
61 | Jörg Wilberg, Raul Camposano, Wolfgang Rosenstiel |
Design flow for hardware/software cosynthesis of a video compression system. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES ![In: Proceedings of the Third International Workshop on Hardware/Software Codesign, CODES 1994, Grenoble, France, September 22-24, 1994, pp. 73-80, 1994, IEEE Computer Society, 0-8186-6315-4. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
51 | Hyunok Oh, Soonhoi Ha |
A hardware-software cosynthesis technique based on heterogeneous multiprocessor scheduling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES ![In: Proceedings of the Seventh International Workshop on Hardware/Software Codesign, CODES 1999, Rome, Italy, 1999, pp. 183-187, 1999, ACM, 1-58113-132-1. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
distributed heterogeneous embedded system, hardware-software cosynthesis, system-on-chip |
51 | Peter Bjørn-Jørgensen, Jan Madsen |
Critical path driven cosynthesis for heterogeneous target architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES ![In: Proceedings of the Fifth International Workshop on Hardware/Software Codesign, CODES/CASHE 1997, March 24-26, 1997, Braunschweig, Germany, pp. 15-19, 1997, IEEE Computer Society, 0-8186-7895-X. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
critical path driven, heterogeneous target architectures, list based scheduling, path driven cosynthesis, single-rate systems, task scheduling, processor scheduling, data dependencies, target architecture |
44 | Hyunuk Jung, Hoeseok Yang, Soonhoi Ha |
Optimized RTL Code Generation from Coarse-Grain Dataflow Specification for Fast HW/SW Cosynthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Signal Process. Syst. ![In: J. Signal Process. Syst. 52(1), pp. 13-34, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
VHDL, system level design, RTL, dataflow graph (DFG), HW/SW codesign |
44 | Sudeep Pasricha, Nikil D. Dutt |
A Framework for Cosynthesis of Memory and Communication Architectures for MPSoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(3), pp. 408-420, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
44 | Robert P. Dick, Niraj K. Jha |
COWLS: hardware-software cosynthesis of wireless low-power distributed embedded client-server systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(1), pp. 2-16, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
44 | Yuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki |
A cosynthesis algorithm for application specific processors with heterogeneous datapaths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, Yokohama, Japan, January 27-30, 2004, pp. 250-255, 2004, IEEE Computer Society, 0-7803-8175-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
44 | Hyunuk Jung, Soonhoi Ha |
Hardware synthesis from coarse-grained dataflow specification for fast HW/SW cosynthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2004, Stockholm, Sweden, September 8-10, 2004, pp. 24-29, 2004, ACM, 1-58113-937-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
automatic hardware synthesis, VHDL, system level design, dataflow graph(DFG), HW/SW codesign |
44 | Shampa Chakraverty |
Cosynthesis of multiprocessor architectures with high availability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 17th International Conference on VLSI Design (VLSI Design 2004), with the 3rd International Conference on Embedded Systems Design, 5-9 January 2004, Mumbai, India, pp. 927-932, 2004, IEEE Computer Society, 0-7695-2072-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
44 | Shampa Chakraverty, C. P. Ravikumar, D. Roy Choudhuri |
An Evolutionary Scheme for Cosynthesis of Real-Time Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC/VLSI Design ![In: Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), and the 15th International Conference on VLSI Design (VLSI Design 2002), Bangalore, India, January 7-11, 2002, pp. 251-, 2002, IEEE Computer Society, 0-7695-1299-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
stochastic task scheduling, hierarchical genetic algorithm, multiprocessor architectures, embedded real-time systems, Hardware software co-synthesis |
44 | Wayne H. Wolf |
Object-oriented cosynthesis of distributed embedded systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 1(3), pp. 301-314, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
object-oriented co-synthesis, distributed embedded systems, hardware-software co-design |
44 | Rolf Ernst, Jörg Henkel, Thomas Benner |
Hardware-Software Cosynthesis for Microcontrollers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 10(4), pp. 64-75, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
41 | Minyoung Kim, Sudarshan Banerjee, Nikil D. Dutt, Nalini Venkatasubramanian |
Design space exploration of real-time multi-media MPSoCs with heterogeneous scheduling policies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2006, Seoul, Korea, October 22-25, 2006, pp. 16-21, 2006, ACM, 1-59593-370-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
cosynthesis, energy, real-time scheduling, MPSoC |
41 | Rick Miller |
VHDL-based EDA Tool Implementation with Java. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 19-21 February 1998, Lafayette, LA, USA, pp. 440-445, 1998, IEEE Computer Society, 0-8186-8409-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
Hardware/Software CoSynthesis, Java, VHDL |
41 | Adel Baganne, Jean Luc Philippe, Eric Martin 0001 |
Hardware interface design for real time embedded systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 7th Great Lakes Symposium on VLSI (GLS-VLSI '97), 13-15 March 1997, Urbana, IL, USA, pp. 58-63, 1997, IEEE Computer Society, 0-8186-7904-2. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
real time digital signal processing, hardware interface design, codesign approach, storage components, hardware-software components, I/O data modeling style, hardware I/O transfer sequences, high level synthesis tool, GAUT, I/O transfer order, cosynthesis tool, real-time systems, ASICs, timing constraints, generic model, data communication, real time embedded systems, formal technique, interface specification, FFT algorithms, allocation problem |
41 | Ti-Yen Yen, Wayne H. Wolf |
Performance estimation for real-time distributed embedded systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1995 International Conference on Computer Design (ICCD '95), VLSI in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings, pp. 64-71, 1995, IEEE Computer Society, 0-8186-7165-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
real-time distributed embedded systems, efficient analysis algorithm, application task, cosynthesis algorithms, bounding algorithms, performance evaluation, real-time systems, distributed processing, ASICs, data dependencies, execution time, performance estimation, CPUs, tight bounds, communication links |
34 | Yuichiro Miyaoka, Jinku Choi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki |
An algorithm of hardware unit generation for processor core synthesis with packed SIMD type instructions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS (1) ![In: IEEE Asia Pacific Conference on Circuits and Systems 2002, APCCAS 2002, Singapore, 16-18 December 2002, pp. 171-176, 2002, IEEE, 0-7803-7690-0. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
34 | Shampa Chakraverty, C. P. Ravikumar |
A Stochastic Framework for Co-synthesis of Real-Time Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES ![In: Languages, Compilers, and Tools for Embedded Systems, ACM SIGPLAN Workshop LCTES 2000, Vancouver, BC, Canada, June 18, 2000, Proceedings, pp. 96-113, 2000, Springer, 3-540-41781-8. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
27 | Adam Górski, Maciej Ogorzalek |
Genetic Programming based Algorithm for HW/SW Cosynthesis of Distributed Embedded Systems Specified using Conditional Task Graph. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SENSORNETS ![In: Proceedings of the 11th International Conference on Sensor Networks, SENSORNETS 2022, Online Streaming, February 7-8, 2022., pp. 239-243, 2022, SCITEPRESS, 978-989-758-551-7. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
27 | Adam Górski, Maciej Ogorzalek |
Genetic Programming based Iterative Improvement Algorithm for HW/SW Cosynthesis of Distributted Embedded Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SENSORNETS ![In: Proceedings of the 10th International Conference on Sensor Networks, SENSORNETS 2021, Online Streaming, February 9-10, 2021., pp. 120-125, 2021, SCITEPRESS, 978-989-758-489-3. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
27 | Adam Górski, Maciej Ogorzalek |
Genetic Programming based Constructive Algorithm with Penalty Function for Hardware/Software Cosynthesis of Embedded Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICSOFT ![In: Proceedings of the 16th International Conference on Software Technologies, ICSOFT 2021, Online Streaming, July 6-8, 2021., pp. 583-588, 2021, SCITEPRESS, 978-989-758-523-4. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
27 | Debayan Roy, Licong Zhang, Wanli Chang 0001, Sanjoy K. Mitter, Samarjit Chakraborty |
Semantics-Preserving Cosynthesis of Cyber-Physical Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Proc. IEEE ![In: Proc. IEEE 106(1), pp. 171-200, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
27 | Nishit Ashok Kapadia, Sudeep Pasricha |
A System-Level Cosynthesis Framework for Power Delivery and On-Chip Data Networks in Application-Specific 3-D ICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 24(1), pp. 3-16, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
27 | Kunal Arya |
Hierarchical Transactions for Hardware/Software Cosynthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2014 |
RDF |
|
27 | Shampa Chakraverty, Anil Kumar |
Erratum: A rule-based availability-driven cosynthesis scheme. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Des. Autom. Embed. Syst. ![In: Des. Autom. Embed. Syst. 11(4), pp. 313, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
27 | Shampa Chakraverty, Anil Kumar |
A rule-based availability-driven cosynthesis scheme. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Des. Autom. Embed. Syst. ![In: Des. Autom. Embed. Syst. 11(2-3), pp. 193-222, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
27 | Marcus T. Schmitz, Bashir M. Al-Hashimi, Petru Eles |
Cosynthesis of energy-efficient multimode embedded systems with consideration of mode-execution probabilities. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(2), pp. 153-169, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
27 | Nozomu Togawa, Takao Totsuka, Tatsuhiko Wakui, Masao Yanagisawa, Tatsuo Ohtsuki |
A Hardware/Software Cosynthesis System for Processor Cores with Content Addressable Memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. ![In: IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 86-A(5), pp. 1082-1092, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP BibTeX RDF |
|
27 | Salim Ouadjaout, Marie-France Albenge, Dominique Houzet |
VSIA Interface Cosynthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: 1st IEEE International Workshop on Electronic Design, Test and Applications (DELTA 2002), 29-31 January 2002, Christchurch, New Zealand, pp. 43-46, 2002, IEEE Computer Society, 0-7695-1453-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
VSIA, SoC, Co-design, interface synthesis |
27 | Byungil Jeong, Sungjoo Yoo, Sunghyun Lee, Kiyoung Choi |
Hardware-software cosynthesis for run-time incrementally reconfigurable FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of ASP-DAC 2000, Asia and South Pacific Design Automation Conference 2000, Yokohama, Japan, pp. 169-174, 2000, ACM, 0-7803-5974-7. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
27 | Robert P. Dick, Niraj K. Jha |
Corrections to "mogac: a multiobjective genetic algorithm for hardware-software cosynthesis of distributed embedded systems". ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(10), pp. 1527-1527, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
27 | Karsten Lüth, Jürgen Niehaus, Thomas Peikenkamp |
HW/SW Cosynthesis Using Statecharts and Symbolic Timing Diagrams. ![Search on Bibsonomy](Pics/bibsonomy.png) |
International Workshop on Rapid System Prototyping ![In: Proceedings of the Ninth IEEE International Workshop on Rapid System Prototyping (RSP 1998), Leuven, Belgium, June 3-5, 1998, pp. 212-217, 1998, IEEE Computer Society, 0-8186-8479-8. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
27 | Rolf Ernst, Jörg Henkel, Thomas Benner, Wei Ye 0002, Ulrich Holtmann, Dirk Herrmann, Michael Trawny |
The COSYMA environment for hardware/software cosynthesis of small embedded systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microprocess. Microsystems ![In: Microprocess. Microsystems 20(3), pp. 159-166, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
27 | Dang S. Sananikone |
Cosynthesis of embedded systems using coloured interpreted petri nets. ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
1996 |
RDF |
|
27 | Thomas Benner, Rolf Ernst, Achim Österling |
Scalable performance scheduling for hardware-software cosynthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EURO-DAC ![In: Proceedings EURO-DAC'95, European Design Automation Conference with EURO-VHDL, Brighton, England, UK, September 18-22, 1995, pp. 164-169, 1995, IEEE Computer Society, 0-8186-7156-4. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
27 | Thomas Benner, Rolf Ernst, Ingo Könenkamp, P. Schüler, H.-C. Schaub |
A prototyping system for verification and evaluation in hardware-software cosynthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RSP ![In: Sixth IEEE International Workshop on Rapid System Prototyping (RSP '95), Chapel Hill, North Carolina, USA, June 7-9, 1995, pp. 54-61, 1995, IEEE Computer Society, 0-8186-7100-9. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
27 | Kunle Olukotun, Rachid Helaihel, Jeremy R. Levitt, Ricardo Ramírez |
A software-hardware cosynthesis approach to digital system simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Micro ![In: IEEE Micro 14(4), pp. 48-58, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
27 | Thomas Benner, Rolf Ernst, Ingo Könenkamp, Ulrich Holtmann, P. Schüler, H.-C. Schaub, N. Serafimov |
FPGA Based Prototyping for Verification and Evaluation in Hardware-Software Cosynthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic, Architectures, Synthesis and Applications, 4th International Workshop on Field-Programmable Logic and Applications, FPL '94, Prague, Czech Republic, September 7-9, 1994, Proceedings, pp. 251-258, 1994, Springer, 3-540-58419-6. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
27 | Martyn Edwards, John Forrest |
A Development Environment for the Cosynthesis of Embedded Software/Hardware Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EDAC-ETC-EUROASIC ![In: EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28 - March 3, 1994, Paris, France, pp. 469-473, 1994, IEEE Computer Society, 0-8186-5410-4. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
27 | Rajesh K. Gupta 0001, Giovanni De Micheli |
Hardware-Software Cosynthesis for Digital Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 10(3), pp. 29-41, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
24 | Jesper Grode, Peter Voigt Knudsen, Jan Madsen |
Hardware Resource Allocation for Hardware/Software Partitioning in the LYCOS System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1998 Design, Automation and Test in Europe (DATE '98), February 23-26, 1998, Le Palais des Congrès de Paris, Paris, France, pp. 22-27, 1998, IEEE Computer Society, 0-8186-8359-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
Cosynthesis, LYCOS System, Resource Allocation, HW/SW Partitioning |
17 | Francisco Assis Moreira do Nascimento, Marcio F. da S. Oliveira, Flávio Rech Wagner |
MDE approach to the co-synthesis of embedded systems using a MOF-based internal design representation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MOMPES ![In: ICSE 2009 Workshop on Model-Based Methodologies for Pervasive and Embedded Software, MOMPES 2009, May 16, 2009, Vancouver, Canada, pp. 53-60, 2009, IEEE Computer Society, 978-1-4244-3721-4. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
17 | Gul N. Khan, Anika Awwal |
Codesign of Embedded Systems with Process/Module Level Real-Time Deadlines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CSE (2) ![In: Proceedings of the 12th IEEE International Conference on Computational Science and Engineering, CSE 2009, Vancouver, BC, Canada, August 29-31, 2009, pp. 526-531, 2009, IEEE Computer Society, 978-1-4244-5334-4. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
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17 | Soonhoi Ha, Sungchan Kim, Choonseung Lee, Youngmin Yi, Seongnam Kwon, Young-Pyo Joo |
PeaCE: A hardware-software codesign environment for multimedia embedded systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 12(3), pp. 24:1-24:25, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
hardware-software cosimulation, embedded systems, design-space exploration, model-based design, Hardware-software codesign |
17 | Dong Wu, Bashir M. Al-Hashimi, Marcus T. Schmitz, Petru Eles |
Power-Composition Profile Driven Co-Synthesis with Power Management Selection for Dynamic and Leakage Energy Reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August - 3 September 2005, Porto, Portugal, pp. 34-41, 2005, IEEE Computer Society, 0-7695-2433-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
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17 | Amjad Mohsen, Richard Hofmann |
Characterizing Power Consumption and Delay of Functional/Library Components for Hardware/Software Co-Design of Embedded Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE International Workshop on Rapid System Prototyping ![In: 15th IEEE International Workshop on Rapid System Prototyping (RSP 2004), 28-30 June 2004, Geneva, Switzerland, pp. 45-52, 2004, IEEE Computer Society, 0-7695-2159-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
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17 | Keith S. Vallerio, Niraj K. Jha |
Task graph transformation to aid system synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2002 International Symposium on Circuits and Systems, ISCAS 2002, Scottsdale, Arizona, USA, May 26-29, 2002, pp. 695-698, 2002, IEEE, 0-7803-7448-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
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17 | David L. Rhodes, Wayne H. Wolf |
RAGS-real-analysis ALAP-guided synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(8), pp. 931-941, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
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17 | Yuichiro Miyaoka, Yoshiharu Kataoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki |
Area/delay estimation for digital signal processor cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of ASP-DAC 2001, Asia and South Pacific Design Automation Conference 2001, January 30-February 2, 2001, Yokohama, Japan, pp. 156-161, 2001, ACM, 0-7803-6634-4. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
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17 | Yanbing Li, Wayne H. Wolf |
Hardware/software co-synthesis with memory hierarchies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(10), pp. 1405-1417, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
17 | Peter Voigt Knudsen, Jan Madsen |
Integrating communication protocol selection with hardware/software codesign. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(8), pp. 1077-1095, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
17 | Nozomu Togawa, Takashi Sakurai, Masao Yanagisawa, Tatsuo Ohtsuki |
A Hardware/Software Partitioning Algorithm for Processor Cores of Digital Signal Processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 1999 Conference on Asia South Pacific Design Automation, Wanchai, Hong Kong, China, January 18-21, 1999, pp. 335-338, 1999, IEEE Computer Society, 0-7803-5012-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
17 | Rajesh K. Gupta 0001, Giovanni De Micheli |
Specification and analysis of timing constraints for embedded systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(3), pp. 240-256, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
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17 | Stefano Antoniazzi, Alessandro Balboni, William Fornaciari, Donatella Sciuto |
A methodology for control-dominated systems codesign. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES ![In: Proceedings of the Third International Workshop on Hardware/Software Codesign, CODES 1994, Grenoble, France, September 22-24, 1994, pp. 2-9, 1994, IEEE Computer Society, 0-8186-6315-4. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
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