Search results for "coupling-noise"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
66	Debjit Sinha, Hai Zhou 0001, Chris C. N. Chu	Optimal gate sizing for coupling-noise reduction.	ISPD	2004	DBLP DOI BibTeX RDF	coupling-noise, gate-sizing, lattice theory, fixpoint
53	Jingye Xu, Pervez Khaled, Masud H. Chowdhury	Fast bus waveform estimation at the presence of coupling noise.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	coupling noise, global interconnect
47	Kathirgamar Aingaran, Fabian Klass, Chin-Man Kim, Chaim Amir, Joydeep Mitra, Eileen You, Jamil Mohd, Sai-keung Dong	Coupling Noise Analysis for VLIS and ULSI Circuits.	ISQED	2000	DBLP DOI BibTeX RDF	Crosstalk Analysis, Crosstalk Modeling, Noise
43	Rajeshwary Tayade, Vijay Kiran Kalyanam, Sani R. Nassif, Michael Orshansky, Jacob A. Abraham	Estimating path delay distribution considering coupling noise.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	dynamic delay variation, coupling, crosstalk
42	Debjit Sinha, Hai Zhou 0001	Yield driven gate sizing for coupling-noise reduction under uncertainty.	ASP-DAC	2005	DBLP DOI BibTeX RDF
40	Martin Saint-Laurent	A Model for Interlevel Coupling Noise in Multilevel Interconnect Structures.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
39	Kanak Agarwal, Dennis Sylvester, David T. Blaauw	Modeling and analysis of crosstalk noise in coupled RLC interconnects.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
37	Takashi Sato, Yu Cao 0001, Kanak Agarwal, Dennis Sylvester, Chenming Hu	Bidirectional closed-form transformation between on-chip coupling noise waveforms and interconnect delay-change curves.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
35	Ajoy Kumar Palit, Volker Meyer, Walter Anheier, Jürgen Schlöffel	ABCD Modeling of Crosstalk Coupling Noise to Analyze the Signal Integrity Losses on the Victim Interconnect in DSM Chips.	VLSI Design	2005	DBLP DOI BibTeX RDF
35	Masaru Takahashi, Boon-Keat Tan, Hiroshi Iwamura, Toshimasa Matsuoka, Kenji Taniguchi 0001	A study of robustness and coupling-noise immunity on simultaneous data transfer CDMA bus interface.	ISCAS (4)	2002	DBLP DOI BibTeX RDF
35	Debjit Sinha, Hai Zhou 0001	Gate-size optimization under timing constraints for coupling-noise reduction.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
35	Weize Xu, Eby G. Friedman	A substrate noise circuit for accurately testing mixed-signal ICs.	ISCAS (1)	2002	DBLP DOI BibTeX RDF
34	Rajeshwary Tayade, Jacob A. Abraham	Critical Path Selection for Delay Test Considering Coupling Noise.	ETS	2008	DBLP DOI BibTeX RDF	Coupling noise, weighted partial max sat, critical path selection, delay test
33	Masanori Hashimoto, Yuji Yamada, Hidetoshi Onodera	Capturing crosstalk-induced waveform for accurate static timing analysis.	ISPD	2003	DBLP DOI BibTeX RDF	capacitive coupling noise, delay calculation, slope propagation, static timing analysis, crosstalk noise
32	Baohua Wang, Pinaki Mazumder	EM Wave Coupling Noise Modeling Based on Chebyshev Approximation and Exact Moment Formulation.	DATE	2005	DBLP DOI BibTeX RDF
32	Chih-Liang Huang, Aurobindo Dasgupta	An Improved method for Fast Noise Estimation based on Net Segmentation.	ICCD	2003	DBLP DOI BibTeX RDF
32	Martin Kuhlmann, Sachin S. Sapatnekar	Exact and efficient crosstalk estimation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
32	Martin Kuhlmann, Sachin S. Sapatnekar, Keshab K. Parhi	Efficient Crosstalk Estimation.	ICCD	1999	DBLP DOI BibTeX RDF
29	Chung-Kuan Tsai, Malgorzata Marek-Sadowska	Modeling Crosstalk Induced Delay.	ISQED	2003	DBLP DOI BibTeX RDF
29	Andrew B. Kahng, Sudhakar Muddu, Niranjan Pol, Devendra Vidhani	Noise Model for Multiple Segmented Coupled RC Interconnects.	ISQED	2001	DBLP DOI BibTeX RDF
28	Toshinari Takayanagi, Jinuk Luke Shin, Bruce Petrick, Jeffrey Y. Su, Ana Sonia Leon	A dual-core 64b ultraSPARC microprocessor for dense server applications.	DAC	2004	DBLP DOI BibTeX RDF	L2, UltraSPARC, coupling noise, deep submicron technology, dense server, dual-core, throughput computing, cache, multiprocessor, leakage, NBTI, negative bias temperature instability
27	Gin Yee, Tyler Thorp, Ron Christopherson, Ban P. Wang, Carl Sechen	An Automated Shielding Algorithm and Tool For Dynamic Circuits.	ISQED	2000	DBLP DOI BibTeX RDF
25	Ajoy Kumar Palit, Lei Wu, Kishore K. Duganapalli, Walter Anheier, Jürgen Schlöffel	A New, Flexible and Very Accurate Crosstalk Fault Model to Analyze the Effects of Coupling Noise between the Interconnects on Signal Integrity Losses in Deep Submicron Chips.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF	crosstalk model, aggressor-victim, ABCD-model, crosstalk-hazards, signal integrity
24	Ravishankar Arunachalam, Emrah Acar, Sani R. Nassif	Optimal shielding/spacing metrics for low power design.	ISVLSI	2003	DBLP DOI BibTeX RDF
24	Kanak Agarwal, Mridul Agarwal, Dennis Sylvester, David T. Blaauw	Statistical interconnect metrics for physical-design optimization.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
24	Kanak Agarwal, Dennis Sylvester, David T. Blaauw	A simplified transmission-line based crosstalk noise model for on-chip RLC wiring.	ASP-DAC	2004	DBLP DOI BibTeX RDF
24	David T. Blaauw, Supamas Sirichotiyakul, Chanhee Oh	Driver modeling and alignment for worst-case delay noise.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
22	Liang Deng, Martin D. F. Wong	Optimal Algorithm for Minimizing the Number of Twists in an On-Chip Bus.	DATE	2004	DBLP DOI BibTeX RDF
21	Chandramouli Visweswariah, Ruud A. Haring, Andrew R. Conn	Noise considerations in circuit optimization.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
21	Masanori Hashimoto, Masao Takahashi, Hidetoshi Onodera	Crosstalk noise optimization by post-layout transistor sizing.	ISPD	2002	DBLP DOI BibTeX RDF	capacitive coupling noise, post-layout optimization, gate sizing, transistor sizing, crosstalk noise
20	Medha Kulkarni, Tom Chen 0001	A sensitivity-based approach to analyzing signal delay uncertainty of coupled interconnects.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
20	Medha Kulkarni, Tom Chen 0001	A Sensitivity Based Approach to Analyzing Signal Delay Uncertainty of Coupled Interconnects.	ISQED	2004	DBLP DOI BibTeX RDF
19	Murat R. Becer, David T. Blaauw, Supamas Sirichotiyakul, Chanhee Oh, Vladimir Zolotov, Jingyan Zuo, Rafi Levy, Ibrahim N. Hajj	A Global Driver Sizing Tool for Functional Crosstalk Noise Avoidance.	ISQED	2001	DBLP DOI BibTeX RDF
19	Kevin T. Tang, Eby G. Friedman	Peak noise prediction in loosely coupled interconnect [VLSI circuits].	ISCAS (1)	1999	DBLP DOI BibTeX RDF
17	Lauren Hui Chen, Malgorzata Marek-Sadowska	Aggressor alignment for worst-case crosstalk noise.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
17	Kenneth L. Shepard, Vinod Narayanan, Peter C. Elmendorf, Gutuan Zheng	Global harmony: coupled noise analysis for full-chip RC interconnect networks.	ICCAD	1997	DBLP DOI BibTeX RDF	interconnect, noise, static timing analysis
15	Loreto Pescosolido, Sergio Barbarossa	Distributed decision in sensor networks based on local coupling through Pulse Position Modulated signals.	ICASSP	2008	DBLP DOI BibTeX RDF
15	Christoph Albrecht, Andrew B. Kahng, Bao Liu 0001, Ion I. Mandoiu, Alexander Zelikovsky	On the skew-bounded minimum-buffer routing tree problem.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
15	Charles J. Alpert, Andrew B. Kahng, Bao Liu 0001, Ion I. Mandoiu, Alexander Zelikovsky	Minimum buffered routing with bounded capacitive load for slew rate and reliability control.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
15	Sarvesh Bhardwaj, Sarma B. K. Vrudhula, David T. Blaauw	Estimation of signal arrival times in the presence of delay noise.	ICCAD	2002	DBLP DOI BibTeX RDF
14	Renatas Jakushokas, Eby G. Friedman	Simultaneous shield and repeater insertion.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	delay, interconnects, noise, power, area
14	Husni M. Habal, Kartikeya Mayaram, Terri S. Fiez	Accurate and efficient simulation of synchronous digital switching noise in systems on a chip.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
13	Feng Qian 0005, Haowei Hua, Yuhang Wen, Jingjing Zong, Gulan Zhang, Guangmin Hu	Unsupervised Intense VSP Coupling Noise Suppression With Iterative Robust Deep Learning.	IEEE Trans. Geosci. Remote. Sens.	2024	DBLP DOI BibTeX RDF
13	Zahra Aminzare, Vaibhav Srivastava	Stochastic synchronization in nonlinear network systems driven by intrinsic and coupling noise.	Biol. Cybern.	2022	DBLP DOI BibTeX RDF
13	Selahattin Sayil, Subed Lamichhane, Kutay Sayil	Coupling Noise Mitigation using a Pass Transistor.	ISVLSI	2020	DBLP DOI BibTeX RDF
13	Makoto Yabuuchi, Yasumasa Tsukamoto, Hidehiro Fujiwara, Miki Tanaka, Shinji Tanaka, Koji Nii	A 28-nm 1R1W Two-Port 8T SRAM Macro With Screening Circuitry Against Read Disturbance and Wordline Coupling Noise Failures.	IEEE Trans. Very Large Scale Integr. Syst.	2018	DBLP DOI BibTeX RDF
13	Jose L. Silva-Perales, Daniel Garcia-Garcia, Carlos J. Franco-Tinoco	Impedance vs coupling noise analysis and tradeoff on power delivery filters based on package layout interconnections.	LASCAS	2018	DBLP DOI BibTeX RDF
13	Yongsheng Wang, Min Wang, Huaixin Xian, Yunfei Du, Bei Cao, Xiaowei Liu	Influence of substrate coupling noise to clock and data recovery.	ASICON	2015	DBLP DOI BibTeX RDF
13	Vasileios Gerakis, Alkis A. Hatzopoulos	Substrate coupling noise considerations for frequencies up to 100GHz.	MIXDES	2014	DBLP DOI BibTeX RDF
13	Yahia Hassan, Raphael T. L. Rolny, Armin Wittneben	MIMO relaying with compact antenna arrays: Coupling, noise correlation and superdirectivity.	PIMRC	2013	DBLP DOI BibTeX RDF
13	Yuan-Ying Chang, Yoshi Shih-Chieh Huang, Vijaykrishnan Narayanan, Chung-Ta King	ShieldUS: A novel design of dynamic shielding for eliminating 3D TSV crosstalk coupling noise.	ASP-DAC	2013	DBLP DOI BibTeX RDF
13	Yongsheng Wang, Fang Li, Hualing Yang, Yonglai Zhang, Yanhui Ren	3D hybrid modeling of substrate coupling noise in lightly doped mixed-signal ICs.	ASICON	2013	DBLP DOI BibTeX RDF
13	Victoria Vishnyakov, Eby G. Friedman, Avinoam Kolodny	Multi-aggressor capacitive and inductive coupling noise modeling and mitigation.	Microelectron. J.	2012	DBLP DOI BibTeX RDF
13	Debjit Sinha, Alex Rubin, Chandu Visweswariah, Frank Borkam, Gregory Schaeffer, Soroush Abbaspour	Feasible Aggressor-Set Identification Under Constraints for Maximum Coupling Noise.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2009	DBLP DOI BibTeX RDF
13	Rajeshwary Tayade, Jacob A. Abraham	Critical Path Selection for Delay Testing Considering Coupling Noise.	J. Electron. Test.	2009	DBLP DOI BibTeX RDF
13	Rajeshwary Tayade, Jacob A. Abraham	Critical Path Selection for Delay Test Considering Coupling Noise.	ETS	2009	DBLP DOI BibTeX RDF
13	Rajendran Panda, Vladimir Zolotov, Murat R. Becer	Coupling Noise.	Handbook of Algorithms for Physical Design Automation	2008	DBLP DOI BibTeX RDF
13	Yasuhiro Ogasahara, Masanori Hashimoto, Takao Onoye	Measurement and Analysis of Inductive Coupling Noise in 90 nm Global Interconnects.	IEEE J. Solid State Circuits	2008	DBLP DOI BibTeX RDF
13	Debjit Sinha, Gregory Schaeffer, Soroush Abbaspour, Alex Rubin, Frank Borkam	Constrained aggressor set selection for maximum coupling noise.	ICCAD	2008	DBLP DOI BibTeX RDF
13	Jingye Xu, Masud H. Chowdhury	Accurate Delay Estimation in the Presence of Coupling Noise using Complete Waveform Accuracy.	ICECS	2007	DBLP DOI BibTeX RDF
13	Jeong-Yeol Kim, Ho-Soon Shin, Jong-Bae Lee, Moon-Hyun Yoo, Jeong-Taek Kong	SilcVerify: An Efficient Substrate Coupling Noise Simulation Tool for High-Speed & Nano-Scaled Memory Design.	ISQED	2007	DBLP DOI BibTeX RDF
13	Weize Xu, Eby G. Friedman	On-chip test circuit for measuring substrate and line-to-line coupling noise.	IEEE J. Solid State Circuits	2006	DBLP DOI BibTeX RDF
13	Payam Heydari, Massoud Pedram	Capacitive coupling noise in high-speed VLSI circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
13	Masud H. Chowdhury, Yehea I. Ismail	Analysis of coupling noise and it's scalability in dynamic circuits [dynamic logic CMOS ICs].	CICC	2004	DBLP DOI BibTeX RDF
13	Young-Jun Lee, Yong-Bin Kim	A fast and precise interconnect capacitive coupling noise model.	ISCAS (2)	2004	DBLP BibTeX RDF
13	Sarma B. K. Vrudhula, David T. Blaauw, Supamas Sirichotiyakul	Probabilistic analysis of interconnect coupling noise.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
13	Masud H. Chowdhury, Yehea I. Ismail	Analysis of Coupling Noise in Dynamic Circuit.	IWSOC	2003	DBLP DOI BibTeX RDF
13	Sarma B. K. Vrudhula, David T. Blaauw, Supamas Sirichotiyakul	Estimation of the likelihood of capacitive coupling noise.	DAC	2002	DBLP DOI BibTeX RDF	noise, signal integrity, deep submicron
13	Payam Heydari, Massoud Pedram	Analysis and Reduction of Capacitive Coupling Noise in High-Speed VLSI Circuits.	ICCD	2001	DBLP DOI BibTeX RDF
13	Lauren Hui Chen, Malgorzata Marek-Sadowska	Aggressor alignment for worst-case coupling noise.	ISPD	2000	DBLP DOI BibTeX RDF	aggressor alignment, interconnect coupling, signal integrity, crosstalk noise, timing window
13	Guoan Zhong, Cheng-Kok Koh, Kaushik Roy 0001	A Twisted Bundle Layout Structure for Minimizing Inductive Coupling Noise.	ICCAD	2000	DBLP DOI BibTeX RDF
13	Kevin T. Tang, Eby G. Friedman	Interconnect coupling noise in CMOS VLSI circuits.	ISPD	1999	DBLP DOI BibTeX RDF
13	Dong-Sun Min, Dietrich W. Langer	Multiple twisted data line techniques for coupling noise reduction in embedded DRAMs.	CICC	1999	DBLP DOI BibTeX RDF
13	Emrah Acar, Altan Odabasioglu, Mustafa Celik, Lawrence T. Pileggi	S2P: A Stable 2-Pole RC Delay and Coupling Noise Metric.	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF
13	Khalid Rahmat, José Neves 0002, Jin-Fuw Lee	Methods for calculating coupling noise in early design: a comparative analysis.	ICCD	1998	DBLP DOI BibTeX RDF
13	S. Matsushita, T. Moto-Oka	Magnitude of Cross-Coupling Noise in Digital Multiwire Transmission Lines.	IEEE Trans. Computers	1974	DBLP DOI BibTeX RDF
12	Zaid Al-Ars, Martin Herzog, Ivo Schanstra, Ad J. van de Goor	Influence of Bit Line Twisting on the Faulty Behavior of DRAMs.	MTDT	2004	DBLP DOI BibTeX RDF	Bit line twisting, bit line coupling, DRAMs, crosstalk noise, defect simulation, faulty behavior
12	Li Ding 0002, Pinaki Mazumder	The Impact of Bit-Line Coupling and Ground Bounce on CMOS SRAM Performance.	VLSI Design	2003	DBLP DOI BibTeX RDF
12	Yehea I. Ismail	On-chip inductance cons and pros.	IEEE Trans. Very Large Scale Integr. Syst.	2002	DBLP DOI BibTeX RDF
12	Rutuparna Tamhankar, Srinivasan Murali, Stergios Stergiou, Antonio Pullini, Federico Angiolini, Luca Benini, Giovanni De Micheli	Timing-Error-Tolerant Network-on-Chip Design Methodology.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
12	Qing K. Zhu	Memory Generation and Power Distribution In SOC.	DSD	2006	DBLP DOI BibTeX RDF
10	Selçuk Köse, Emre Salman, Zeljko Ignjatovic, Eby G. Friedman	Pseudo-random clocking to enhance signal integrity.	SoCC	2008	DBLP DOI BibTeX RDF
10	Swaroop Ghosh, Swarup Bhunia, Kaushik Roy 0001	Low-Power and testable circuit synthesis using Shannon decomposition.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	Shannon expansion, dynamic supply gating, test coverage, Design-for-test, IDDQ, noise immunity, test power
10	Ravikishore Gandikota, Kaviraj Chopra, David T. Blaauw, Dennis Sylvester, Murat R. Becer, Joao Geada	Victim alignment in crosstalk aware timing analysis.	ICCAD	2007	DBLP DOI BibTeX RDF
10	Yuxin Wang, Zeljko Ignjatovic	On-Chip Substrate Noise Suppression Using Clock Randomization Methodology.	ISCAS	2007	DBLP DOI BibTeX RDF
10	Rutuparna Tamhankar, Srinivasan Murali, Giovanni De Micheli	Performance driven reliable link design for networks on chips.	ASP-DAC	2005	DBLP DOI BibTeX RDF	aggressive design, performance, reliability, networks on chips, link
10	Desmond Kirkpatrick, Peter J. Osler, Louis Scheffer, Prashant Saxena, Dennis Sylvester	The great interconnect buffering debate: are you a chicken or an ostrich?	ISPD	2004	DBLP DOI BibTeX RDF
7	Kip Killpack, Suriyaprakash Natarajan, Arun Krishnamachary, Pouria Bastani	Case Study on Speed Failure Causes in a Microprocessor.	IEEE Des. Test Comput.	2008	DBLP DOI BibTeX RDF
7	Rostislav (Reuven) Dobkin, Arkadiy Morgenshtein, Avinoam Kolodny, Ran Ginosar	Parallel vs. serial on-chip communication.	SLIP	2008	DBLP DOI BibTeX RDF	dual-rail, long-range interconnect serial link, parallel link, asynchronous circuits
7	Jingye Xu, Pervez Khaled, Masud H. Chowdhury	Full waveform accuracy to estimate delay in coupled digital circuits.	ISCAS	2008	DBLP DOI BibTeX RDF
7	Herng-Jer Lee, Chia-Chi Chu, Wu-Shiung Feng	Crosstalk estimation in high-speed VLSI interconnect using coupled RLC-tree models.	APCCAS (1)	2002	DBLP DOI BibTeX RDF