Search results for "cycle-accurate"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
68	Jaejin Lee, Junghyun Kim, Choonki Jang, Seungkyun Kim, Bernhard Egger 0002, Kwangsub Kim, Sangyong Han	FaCSim: a fast and cycle-accurate architecture simulator for embedded systems.	LCTES	2008	DBLP DOI BibTeX RDF	virtual prototyping, architecture simulator, full-system simulation, simulator parallelization, cycle-accurate simulation
55	Matt T. Yourst	PTLsim: A Cycle Accurate Full System x86-64 Microarchitectural Simulator.	ISPASS	2007	DBLP DOI BibTeX RDF	client-server networked benchmark, PTLsim, cycle accurate full system, x86-64 microarchitectural simulator, superscalar x86-64 processor core, full-speed native execution, microarchitectural simulators, x86 ISA, microoperation level, multiprocessor capable simulation, Xen hypervisor, AMD Athlon 64 machine, virtual machine
51	Hoonmo Yang, Moonkey Lee	Embedded Processor Validation Environment Using a Cycle-Accurate Retargetable Instruction-Set Simulator.	J. Supercomput.	2005	DBLP DOI BibTeX RDF	cycle-accurate, validation, system-on-chip (SoC), architecture description language (ADL), retargetable, instruction-set simulator
50	Guillermo Maturana, James L. Ball, Jeffery Gee, Amaresh Iyer, J. Michael O'Connor	Incas: a cycle accurate model of UltraSPARC.	ICCD	1995	DBLP DOI BibTeX RDF	cycle accurate model, UltraSPARC, Incas, message-passing mechanism, simulating concurrent modules, performance evaluation, C++, virtual machines, logic testing, microprocessor chips, performance estimates, diagnostics, tuning, RTL simulations, processor verification
47	Scott J. Weber, Matthew W. Moskewicz, Matthias Gries, Christian Sauer 0001, Kurt Keutzer	Fast cycle-accurate simulation and instruction set generation for constraint-based descriptions of programmable architectures.	CODES+ISSS	2004	DBLP DOI BibTeX RDF	automatic control generation, instruction set extraction, cycle-accurate simulation
47	Sudeep Pasricha, Nikil D. Dutt, Mohamed Ben-Romdhane	Fast exploration of bus-based on-chip communication architectures.	CODES+ISSS	2004	DBLP DOI BibTeX RDF	bus cycle accurate modeling, fast communication architecture exploration, shared bus architectures, transaction level modeling, AMBA
42	Mehrdad Reshadi, Daniel Gajski	A cycle-accurate compilation algorithm for custom pipelined datapaths.	CODES+ISSS	2005	DBLP DOI BibTeX RDF	NISC, cycle-accurate compiler, scheduling
42	Chen Kang Lo, Ren-Song Tsay	Automatic generation of Cycle Accurate and Cycle Count Accurate transaction level bus models from a formal model.	ASP-DAC	2009	DBLP DOI BibTeX RDF
39	Márcio Oyamada, Flávio Rech Wagner, Marius Bonaciu, Wander O. Cesário, Ahmed Amine Jerraya	Software Performance Estimation in MPSoC Design.	ASP-DAC	2007	DBLP DOI BibTeX RDF	cycle-accurate simulation model, software performance estimation, MPSoC design, software-dominated embedded systems, integrated methodology, bus-functional model, multiprocessor platform, MPEG4 encoder, neural networks, performance analysis, design space exploration, design validation
39	Sudeep Pasricha, Nikil D. Dutt, Mohamed Ben-Romdhane	Extending the transaction level modeling approach for fast communication architecture exploration.	DAC	2004	DBLP DOI BibTeX RDF	bus cycle accurate modeling, communication architecture exploration, shared bus architectures, transaction level modeling, AMBA
39	Daniel Christopher Powell, Björn Franke	Using continuous statistical machine learning to enable high-speed performance prediction in hybrid instruction-/cycle-accurate instruction set simulators.	CODES+ISSS	2009	DBLP DOI BibTeX RDF	continuous statistical machine learning, performance prediction, instruction set simulator
38	Joshua L. Kihm, Samuel D. Strom, Daniel A. Connors	Phase-Guided Small-Sample Simulation.	ISPASS	2007	DBLP DOI BibTeX RDF	SpedOOO benchmark suite, phase-guided small-sample simulation, sampled simulation, phase-based simulation, benchmark evaluation suite, execution-aware sampling-based simulation, design space exploration, sampling method, processor design, cycle-accurate simulation
37	Ines Viskic, Samar Abdi, Daniel D. Gajski	Automatic generation of embedded communication SW for heterogeneous MPSoC platforms.	LCTES	2007	DBLP DOI BibTeX RDF	custom communication SW, pin/cycle accurate models, MPSoC, system level design, transaction level models, platform based design, automatic synthesis, on-chip communication
36	Seongbeom Kim, Fang Liu, Yan Solihin, Ravi R. Iyer 0001, Li Zhao 0002, W. Cohen	Accelerating Full-System Simulation through Characterizing and Predicting Operating System Performance.	ISPASS	2007	DBLP DOI BibTeX RDF	memory hierarchy model, full-system simulation acceleration, operating system performance characterization, operating system performance prediction, computer hardware complexity, cycle-accurate processor system simulation overheads, system libraries, OS service performance behavior, processor hierarchy model, Linux, software complexity
36	Hiroshi Nakashima, Masahiro Konishi, Takashi Nakada	An accurate and efficient simulation-based analysis for worst case interruption delay.	CASES	2006	DBLP DOI BibTeX RDF	worst case interruption delay, cycle accurate simulation
35	Soheil Samii, Mikko Selkälä, Erik Larsson, Krishnendu Chakrabarty, Zebo Peng	Cycle-Accurate Test Power Modeling and Its Application to SoC Test Architecture Design and Scheduling.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
35	Smruti R. Sarangi, Brian Greskamp, Josep Torrellas	CADRE: Cycle-Accurate Deterministic Replay for Hardware Debugging.	DSN	2006	DBLP DOI BibTeX RDF
33	Qing Wu 0002, Qinru Qiu, Massoud Pedram, Chih-Shun Ding	Cycle-accurate macro-models for RT-level power analysis.	IEEE Trans. Very Large Scale Integr. Syst.	1998	DBLP DOI BibTeX RDF
33	Michael Ferdman, Babak Falsafi	Last-Touch Correlated Data Streaming.	ISPASS	2007	DBLP DOI BibTeX RDF	predictor lookahead, last-touch correlated data streaming, address-correlating predictor, cache block address identification, correlation data storage, program active memory footprint, prediction lookahead, off-chip correlation data lookup, scalable on-chip table, low-latency lookup, on-chip storage, last-touch predictor, prefetch, superscalar processor, cycle-accurate simulation
33	Shobana Padmanabhan, Phillip H. Jones, David V. Schuehler, Scott J. Friedman, Praveen Krishnamurthy, Huakai Zhang, Roger D. Chamberlain, Ron Cytron, Jason E. Fritts, John W. Lockwood	Extracting and Improving Microarchitecture Performance on Reconfigurable Architectures.	Int. J. Parallel Program.	2005	DBLP DOI BibTeX RDF	cycle-accurate hardware profiling, performance, architecture, Reconfigurable
31	Pankaj Chauhan, Deepak Goyal, Gagan Hasteer, Anmol Mathur, Nikhil Sharma	Non-cycle-accurate sequential equivalence checking.	DAC	2009	DBLP DOI BibTeX RDF	unit product machine, model checking, formal verification, high level synthesis, sequential equivalence checking
31	Dohyung Kim 0007, Soonhoi Ha, Rajesh Gupta 0001	CATS: cycle accurate transaction-driven simulation with multiple processor simulators.	DATE	2007	DBLP DOI BibTeX RDF
31	Lin Zhong 0001, Srivaths Ravi 0001, Anand Raghunathan, Niraj K. Jha	RTL-Aware Cycle-Accurate Functional Power Estimation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
31	Mehrdad Reshadi, Bita Gorjiara, Nikil D. Dutt	Generic Processor Modeling for Automatically Generating Very Fast Cycle-Accurate Simulators.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
31	Mehrdad Reshadi, Nikil D. Dutt	Generic Pipelined Processor Modeling and High Performance Cycle-Accurate Simulator Generation.	DATE	2005	DBLP DOI BibTeX RDF
31	Lin Zhong 0001, Srivaths Ravi 0001, Anand Raghunathan, Niraj K. Jha	Power estimation for cycle-accurate functional descriptions of hardware.	ICCAD	2004	DBLP DOI BibTeX RDF
30	Junghee Lee, Joonhwan Yi	Cycle error correction in asynchronous clock modeling for cycle-based simulation.	ASP-DAC	2006	DBLP DOI BibTeX RDF
30	John W. Haskins Jr., Kevin Skadron	Accelerated warmup for sampled microarchitecture simulation.	ACM Trans. Archit. Code Optim.	2005	DBLP DOI BibTeX RDF	Reuse latency, sampled simulation, warmup
29	Cristiano Pereira, Jeremy Lau, Brad Calder, Rajesh K. Gupta 0001	Dynamic phase analysis for cycle-close trace generation.	CODES+ISSS	2005	DBLP DOI BibTeX RDF	SimPoint, simulation, tracing, phase
29	Björn Franke	Fast cycle-approximate instruction set simulation.	SCOPES	2008	DBLP DOI BibTeX RDF
28	Hans Eveking, Tobias Dornes, Martin Schweikert	Using SystemVerilog assertions to relate non-cycle-accurate to cycle-accurate designs.	HLDVT	2011	DBLP DOI BibTeX RDF
28	Ben L. Titzer, Jens Palsberg	Nonintrusive precision instrumentation of microcontroller software.	LCTES	2005	DBLP DOI BibTeX RDF	cycle-accurate, instruction-level simulation, sensor networks, monitoring, debugging, profiling, instrumentation, parallel simulation
28	Leonardo R. Bachega, José R. Brunheroto, Luiz De Rose, Pedro Mindlin, José E. Moreira	The BlueGene/L pseudo cycle-accurate simulator.	ISPASS	2004	DBLP DOI BibTeX RDF
27	Jürgen Schnerr, Oliver Bringmann 0001, Wolfgang Rosenstiel	Cycle Accurate Binary Translation for Simulation Acceleration in Rapid Prototyping of SoCs.	DATE	2005	DBLP DOI BibTeX RDF
26	Masahiro Yano, Toru Takasaki, Takashi Nakada, Hiroshi Nakashima	An Accurate and Efficient Time-Division Parallelization of Cycle Accurate Architectural Simulators.	Annual Simulation Symposium	2007	DBLP DOI BibTeX RDF
25	Michael Pellauer, Muralidaran Vijayaraghavan, Michael Adler, Arvind, Joel S. Emer	A-Ports: an efficient abstraction for cycle-accurate performance models on FPGAs.	FPGA	2008	DBLP DOI BibTeX RDF	simulation, FPGA, prototyping, performance models, emulation
25	José Gabriel F. Coutinho, Jun Jiang, Wayne Luk	Interleaving Behavioral and Cycle-Accurate Descriptions for Reconfigurable Hardware Compilation.	FCCM	2005	DBLP DOI BibTeX RDF
25	Antoine Fraboulet, Tanguy Risset, Antoine Scherrer	Cycle Accurate Simulation Model Generation for SoC Prototyping.	SAMOS	2004	DBLP DOI BibTeX RDF
25	Syed Saif Abrar	Cycle-Accurate Energy Model and Source-Independent Characterization Methodology for Embedded Processors.	VLSI Design	2004	DBLP DOI BibTeX RDF
25	Antonio Carlos Schneider Beck, Júlio C. B. de Mattos, Flávio Rech Wagner, Luigi Carro	CACO-PS: A General Purpose Cycle-Accurate Configurable Power Simulator.	SBCCI	2003	DBLP DOI BibTeX RDF
25	Bengt Werner, Peter S. Magnusson	A Hybrid Simulation Approach Enabling Performance Characterization of Large Software Systems.	MASCOTS	1997	DBLP DOI BibTeX RDF
23	Rajat Chaudhry, Daniel L. Stasiak, Stephen D. Posluszny, Sang H. Dhong	A cycle accurate power estimation tool.	ASP-DAC	2006	DBLP DOI BibTeX RDF
23	Hoonmo Yang, Moonkey Lee	Design of a Cycle-Accurate User-Retargetable Instruction-Set Simulator Using Process-Based Scheduling Scheme.	CIS	2004	DBLP DOI BibTeX RDF
23	Jingzhao Ou, Viktor K. Prasanna	Design space exploration using arithmetic-level hardware--software cosimulation for configurable multiprocessor platforms.	ACM Trans. Embed. Comput. Syst.	2006	DBLP DOI BibTeX RDF	FPGA, design space exploration, processor, cosimulation
22	Stefan Farfeleder, Andreas Krall, R. Nigel Horspool	Ultra Fast Cycle-Accurate Compiled Emulation of Inorder Pipelined Architectures.	SAMOS	2005	DBLP DOI BibTeX RDF
22	Andrew Over, Peter E. Strazdins, Bill Clarke	Cycle Accurate Memory Modelling: A Case-Study in Validation.	MASCOTS	2005	DBLP DOI BibTeX RDF
22	Naehyuck Chang, Kwanho Kim, Hyung Gyu Lee	Cycle-accurate energy measurement and characterization with a case study of the ARM7TDMI [microprocessors].	IEEE Trans. Very Large Scale Integr. Syst.	2002	DBLP DOI BibTeX RDF
22	Habib ul Hasan Khan, Diana Göhringer	Cycle-Accurate and Cycle-Reproducible Debugging of Embedded Designs Using Artificial Intelligence.	FPL	2018	DBLP DOI BibTeX RDF
22	Sameh W. Asaad, Ralph Bellofatto, Bernard Brezzo, Chuck Haymes, Mohit Kapur, Benjamin D. Parker, Thomas Roewer, Proshanta Saha, Todd Takken, José A. Tierno	A cycle-accurate, cycle-reproducible multi-FPGA system for accelerating multi-core processor simulation.	FPGA	2012	DBLP DOI BibTeX RDF
22	Junghee Lee, Joonhwan Yi	Industrial experience with cycle error computation of cycle-accurate transaction level models.	SoCC	2007	DBLP DOI BibTeX RDF
22	Richard Buchmann	Modélisation et Simulation Rapide au niveau cycle pour l'Exploration Architecturale de Systèmes Intégrés sur puce. (Modeling and Fast Cycle Accurate Simulation for Architectural Exploration of System On Chip).		2006	RDF
21	Hyo-Joong Suh, Sung Woo Chung	An Accurate Architectural Simulator for ARM1136.	EUC	2005	DBLP DOI BibTeX RDF
20	Thomas Edison Yu, Tomokazu Yoneda, Krishnendu Chakrabarty, Hideo Fujiwara	Test infrastructure design for core-based system-on-chip under cycle-accurate thermal constraints.	ASP-DAC	2009	DBLP DOI BibTeX RDF	TAM design, thermal-aware test, wrapper design, test scheduling, SOC test
20	Derek Chiou, Dam Sunwoo, Joonsoo Kim, Nikhil A. Patil, William H. Reinhart, Darrel Eric Johnson, Jebediah Keefe, Hari Angepat	FPGA-Accelerated Simulation Technologies (FAST): Fast, Full-System, Cycle-Accurate Simulators.	MICRO	2007	DBLP DOI BibTeX RDF
20	Nicholas Jun Hao Ip, Stephen A. Edwards	A Processor Extension for Cycle-Accurate Real-Time Software.	EUC	2006	DBLP DOI BibTeX RDF
20	Eunseok Song, Young-Kil Park, Soon Kwon, Soo-Ik Chae	A Cycle-Accurate Energy Estimator for CMOS Digital Circuits.	PATMOS	2004	DBLP DOI BibTeX RDF
20	In-Cheol Park, Se-Hyeon Kang, Yongseok Yi	Fast Cycle-accurate Behavioral Simulation for Pipelined Processors Using Early Pipeline Evaluation.	ICCAD	2003	DBLP DOI BibTeX RDF	C++
20	Hyung Gyu Lee, Sungyuep Nam, Naehyuck Chang	Cycle-accurate Energy Measurement and High-Level Energy Characterization of FPGAs.	ISQED	2003	DBLP DOI BibTeX RDF
20	Naehyuck Chang, Kwanho Kim, Hyung Gyu Lee	Cycle-accurate energy consumption measurement and analysis: case study of ARM7TDMI.	ISLPED	2000	DBLP DOI BibTeX RDF
20	Wu Ye, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin	The design and use of simplepower: a cycle-accurate energy estimation tool.	DAC	2000	DBLP DOI BibTeX RDF
20	Muhammad Rashid, Bernard Pottier	Application Capturing and Performance Estimation in an Holistic Design Environment.	ECBS	2009	DBLP DOI BibTeX RDF
20	Tarek M. Taha, D. Scott Wills	An Instruction Throughput Model of Superscalar Processors.	IEEE International Workshop on Rapid System Prototyping	2003	DBLP DOI BibTeX RDF
17	Olaf Landsiedel, Muhammad Hamad Alizai, Klaus Wehrle	When Timing Matters: Enabling Time Accurate and Scalable Simulation of Sensor Network Applications.	IPSN	2008	DBLP DOI BibTeX RDF
17	Derek Chiou, Dam Sunwoo, Joonsoo Kim, Nikhil A. Patil, William H. Reinhart, Darrel Eric Johnson, Zheng Xu 0004	The FAST methodology for high-speed SoC/computer simulation.	ICCAD	2007	DBLP DOI BibTeX RDF
17	Alex Bobrek, JoAnn M. Paul, Donald E. Thomas	Shared Resource Access Attributes for High-Level Contention Models.	DAC	2007	DBLP DOI BibTeX RDF
17	Ivan Augé, Frédéric Pétrot, François Donnet, Pascal Gomez	Platform-based design from parallel C specifications.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
17	Jingzhao Ou, Viktor K. Prasanna	MATLAB/Simulink Based Hardware/Software Co-Simulation for Designing Using FPGA Configured Soft Processors.	IPDPS	2005	DBLP DOI BibTeX RDF
17	Ozgur Celebican, Tajana Simunic Rosing, Vincent John Mooney III	Energy estimation of peripheral devices in embedded systems.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	audio, device drivers, energy estimation, software optimization
16	Ram Srinivasan, Jeanine E. Cook, Olaf M. Lubeck	Performance modeling using Monte Carlo simulation.	IEEE Comput. Archit. Lett.	2006	DBLP DOI BibTeX RDF
15	Ivano Barbieri, Massimo Bariani, Alberto Cabitto, Marco Raggio	A Simulation and Exploration Technology for Multimedia-Application-Driven Architectures.	J. VLSI Signal Process.	2005	DBLP DOI BibTeX RDF	Hw-Sw co-design, simulation speed, simulation accuracy, simulation, multimedia, system on chip, DSP, flexibility, VLIW, architecture exploration, ISA
15	Tero Rissa, Adam Donlin, Wayne Luk	Evaluation of SystemC Modelling of Reconfigurable Embedded Systems.	DATE	2004	DBLP DOI BibTeX RDF
15	Tao Wang 0004, Qigang Wang, Dong Liu, Michael Liao, Kevin Wang, Lu Cao, Li Zhao 0002, Ravi R. Iyer 0001, Ramesh Illikkal, John Du, Liang Wang	Hardware/Software Co-Simulation for Last Level Cache Exploration.	NAS	2009	DBLP DOI BibTeX RDF
15	Rabie Ben Atitallah, Smaïl Niar, Samy Meftali, Jean-Luc Dekeyser	An MPSoC Performance Estimation Framework Using Transaction Level Modeling.	RTCSA	2007	DBLP DOI BibTeX RDF
14	Daniela Genius, Ludovic Apvrille	Cycle-Accurate Virtual Prototyping with Multiplicity.	MODELSWARD	2024	DBLP BibTeX RDF
14	Eduardo Rhod, Behnam Ghavami, Zhenman Fang, Lesley Shannon	A Cycle-Accurate Soft Error Vulnerability Analysis Framework for FPGA-based Designs.	CoRR	2023	DBLP DOI BibTeX RDF
14	Pietro Nannipieri, Stefano Di Matteo, Luca Crocetti, Luca Zulberti, Luca Fanucci, Sergio Saponara	Cycle-Accurate Verification of the Cryptographic Co-Processor for the European Processor Initiative.	ApplePies	2023	DBLP DOI BibTeX RDF
14	Alban Gruin, Thomas Carle, Christine Rochange, Pascal Sainrat	Validation of Processor Timing Models Using Cycle-Accurate Timing Simulators.	WCET	2023	DBLP DOI BibTeX RDF
14	You Li, Guannan Zhao, Yunqi He, Hai Zhou 0001	SE3: Sequential Equivalence Checking for Non-Cycle-Accurate Design Transformations †.	DAC	2023	DBLP DOI BibTeX RDF
14	Leilei Jin, Wenjie Fu, Ming Ling, Longxing Shi	A Fast Cross-Layer Dynamic Power Estimation Method by Tracking Cycle-Accurate Activity Factors With Spark Streaming.	IEEE Trans. Very Large Scale Integr. Syst.	2022	DBLP DOI BibTeX RDF
14	Nils Wisiol, Patrick Gersch, Jean-Pierre Seifert	Cycle-Accurate Power Side-Channel Analysis Using the ChipWhisperer: a Case Study on Gaussian Sampling.	IACR Cryptol. ePrint Arch.	2022	DBLP BibTeX RDF
14	Nils Wisiol, Patrick Gersch, Jean-Pierre Seifert	Cycle-Accurate Power Side-Channel Analysis Using the ChipWhisperer: A Case Study on Gaussian Sampling.	CARDIS	2022	DBLP DOI BibTeX RDF
14	Kanishkan Vadivel, Fernando García-Redondo, Ali BanaGozar, Henk Corporaal, Shidhartha Das	SACA: System-level Analog CIM Accelerators Simulation Framework: Architecture and Cycle-accurate System-to-device Simulator.	DCIS	2022	DBLP DOI BibTeX RDF
14	Shang Li 0001, Zhiyuan Yang 0001, Dhiraj Reddy, Ankur Srivastava 0001, Bruce L. Jacob	DRAMsim3: A Cycle-Accurate, Thermal-Capable DRAM Simulator.	IEEE Comput. Archit. Lett.	2020	DBLP DOI BibTeX RDF
14	Wenjie Fu, Ming Ling, Wei Wang, Longxing Shi	AMPS: Accelerating McPAT Power Evaluation Without Cycle-Accurate Simulations.	IEEE Embed. Syst. Lett.	2020	DBLP DOI BibTeX RDF
14	Moon Gi Seok, Hessam S. Sarjoughian, Changbeom Choi, Daejin Park	Fast and Cycle-Accurate Simulation of RTL NoC Designs Using Test-Driven Cellular Automata.	IEEE Access	2020	DBLP DOI BibTeX RDF
14	Riaz-ul-haque Mian, Michihiro Shintani, Michiko Inoue	Cycle-Accurate Evaluation of Software-Hardware Co-Design of Decimal Computation in RISC-V Ecosystem.	CoRR	2020	DBLP BibTeX RDF
14	Juan M. Cebrian, Adrián Barredo, Helena Caminal, Miquel Moretó, Marc Casas, Mateo Valero	Semi-automatic validation of cycle-accurate simulation infrastructures: The case for gem5-x86.	Future Gener. Comput. Syst.	2020	DBLP DOI BibTeX RDF
14	Lukas Steiner, Matthias Jung 0001, Felipe S. Prado, Kirill Bykov, Norbert Wehn	DRAMSys4.0: A Fast and Cycle-Accurate SystemC/TLM-Based DRAM Simulator.	SAMOS	2020	DBLP DOI BibTeX RDF
14	Habib ul Hasan Khan, Ariel Podlubne, Gökhan Akgün, Diana Göhringer	Cycle-Accurate Debugging of Embedded Designs Using Recurrent Neural Networks.	ARC	2020	DBLP DOI BibTeX RDF
14	Erwan Lenormand, Thierry Goubier, Loïc Cudennec, Henri-Pierre Charles	A combined fast/cycle accurate simulation tool for reconfigurable accelerator evaluation: application to distributed data management.	RSP	2020	DBLP DOI BibTeX RDF
14	Michael F. Dossis	Rapid, Formal Verification with Automated and Executable, Cycle-accurate simulators, and Generated Testbenches.	PCI	2020	DBLP DOI BibTeX RDF
14	Asif Ali Khan, Fazal Hameed, Robin Bläsing, Stuart S. P. Parkin, Jerónimo Castrillón	RTSim: A Cycle-Accurate Simulator for Racetrack Memories.	IEEE Comput. Archit. Lett.	2019	DBLP DOI BibTeX RDF
14	Yuze Chi, Young-kyu Choi, Jason Cong, Jie Wang 0022	Rapid Cycle-Accurate Simulator for High-Level Synthesis.	FPGA	2019	DBLP DOI BibTeX RDF
14	Habib ul Hasan Khan, Gökhan Akgün, Ariel Podlubne, Felix Wegener, Amir Moradi 0001, Diana Göhringer	Cycle-Accurate Debugging of Multi-clock Reconfigurable Systems.	ReConFig	2019	DBLP DOI BibTeX RDF
14	Shang Li 0001, Rommel Sánchez Verdejo, Petar Radojkovic, Bruce L. Jacob	Rethinking cycle accurate DRAM simulation.	MEMSYS	2019	DBLP DOI BibTeX RDF
14	Konstantinos Iordanou, Oscar Palomar, John Mawer, Cosmin Gorgovan, Andy Nisbet, Mikel Luján	SimAcc: A Configurable Cycle-Accurate Simulator for Customized Accelerators on CPU-FPGAs SoCs.	FCCM	2019	DBLP DOI BibTeX RDF
14	Riaz-ul-haque Mian, Michihiro Shintani, Michiko Inoue	Cycle-Accurate Evaluation of Software-Hardware Co-Design of Decimal Computation in RISC-V Ecosystem.	SoCC	2019	DBLP DOI BibTeX RDF
14	Kun-Chih Jimmy Chen, Ting-Yi George Wang, Yueh-Chi Andrew Yang	Cycle-Accurate NoC-based Convolutional Neural Network Simulator.	COINS	2019	DBLP DOI BibTeX RDF
14	Anushree Mahapatra, Yidi Liu, Benjamin Carrión Schäfer	Accelerating cycle-accurate system-level simulations through behavioral templates.	Integr.	2018	DBLP DOI BibTeX RDF
14	Chalak Ori, Weiguang Cai, Wei Li, Lei Fang, Libing Zheng, Jintang Wang, Zuguang Wu, Xiongli Gu, Haibin Wang, Avi Mendelson	ScaleSimulator: A Fast and Cycle-Accurate Parallel Simulator for Architectural Exploration.	CoRR	2018	DBLP BibTeX RDF