Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
96 | Sivaram Gopalakrishnan, Priyank Kalla |
Optimization of polynomial datapaths using finite ring algebra. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 12(4), pp. 49, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
arithmetic datapaths, finite ring algebra, modulo arithmetic, polynomial datapaths, High-level synthesis |
58 | Sivaram Gopalakrishnan, Priyank Kalla, Florian Enescu |
Optimization of Arithmetic Datapaths with Finite Word-Length Operands. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 12th Conference on Asia South Pacific Design Automation, ASP-DAC 2007, Yokohama, Japan, January 23-26, 2007, pp. 511-516, 2007, IEEE Computer Society, 1-4244-0629-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
arithmetic datapaths, finite word length, operands, polynomial computations, finite integer rings, CAD, area optimization, bit vectors |
57 | Masahiro Fujita |
Behavior-RTL Equivalence Checking Based on Data Transfer Analysis with Virtual Controllers and Datapaths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHARME ![In: Correct Hardware Design and Verification Methods, 13th IFIP WG 10.5 Advanced Research Working Conference, CHARME 2005, Saarbrücken, Germany, October 3-6, 2005, Proceedings, pp. 340-344, 2005, Springer, 3-540-29105-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
50 | Seokjin Kim, Ramalingam Sridhar |
A local clocking approach for self-timed datapath designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 5th Great Lakes Symposium on VLSI (GLS-VLSI '95), March 16-18, 1995, The State University of New York at Buffalo, USA, pp. 152-, 1995, IEEE Computer Society, 0-8186-7035-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
self-timed datapath designs, local clock control circuit, synchronous datapaths, asynchronous environment, locally-clocked multiplier, asynchronous system implementation, timing, logic design, logic design, digital arithmetic, asynchronous circuits, multiplying circuits |
49 | Sabyasachi Das, Sunil P. Khatri |
An efficient and regular routing methodology for datapath designsusing net regularity extraction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(1), pp. 93-101, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
45 | Wei-Sheng Huang, Tay-Jyi Lin, Shih-Hao Ou, Chih-Wei Liu, Chein-Wei Jen |
Pipelining technique for energy-aware datapaths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (2) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 1218-1221, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
45 | Dmitry V. Ponomarev, Gurhan Kucuk, Oguz Ergin, Kanad Ghose |
Energy Efficient Comparators for Superscalar Datapaths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 53(7), pp. 892-904, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
45 | Michiko Inoue, Kazuhiro Suzuki, Hiroyuki Okamoto, Hideo Fujiwara |
Test Synthesis for Datapaths Using Datapath-Controller Functions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, pp. 294-299, 2003, IEEE Computer Society, 0-7695-1951-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
hierarchical test generation, non-scan design, design-for-testability, at-speed testing, RTL circuit |
45 | Mehrdad Nourani, Joan Carletta, Christos A. Papachristou |
Integrated test of interacting controllers and datapaths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 6(3), pp. 401-422, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
built-in self-test, register transfer level, synthesis-for-testability |
45 | Laurence Goodby, Alex Orailoglu |
Redundancy and testability in digital filter datapaths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(5), pp. 631-644, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
45 | Margarida F. Jacome, Gustavo de Veciana |
Lower bound on latency for VLIW ASIP datapaths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999, San Jose, California, USA, November 7-11, 1999, pp. 261-269, 1999, IEEE Computer Society, 0-7803-5832-5. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
37 | Viktor S. Lapinskii, Margarida F. Jacome, Gustavo de Veciana |
Cluster assignment for high-performance embedded VLIW processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 7(3), pp. 430-454, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Operation binding, clustered VLIW datapaths, embedded systems, partitioning, embedded processors |
37 | Reiner W. Hartenstein, Jürgen Becker 0001, Michael Herz, Rainer Kress 0002, Ulrich Nageldinger |
A Synthesis System For Bus-Based Wavefront Array Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 1996 International Conference on Application-Specific Systems, Architectures, and Processors (ASAP '96), August 19-23, 1996, Chicago, IL , USA, pp. 274-283, 1996, IEEE Computer Society, 0-8186-7542-X. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
synthesis system, bus-based wavefront array architectures, datapath synthesis system, reconfigurable datapath architecture, internal data bus, automatic mapping, datapath units, high speed datapaths, parallel architectures, rapid prototyping, reconfigurable architectures, software prototyping, fine grained parallelism, data manipulations |
37 | Seong Yong Ohm, Fadi J. Kurdahi, Nikil D. Dutt, Min Xu |
A comprehensive estimation technique for high-level synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSS ![In: Proceedings of the 8th International Symposium on System Synthesis (ISSS 1995), September 13-15, 1995, Cannes, France, pp. 122-127, 1995, ACM, 0-89791-771-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
HLS benchmarks, RT level components, RTL datapaths, estimation technique, delays, high level synthesis, high-level synthesis, timing, design space exploration, granularity, hardware description languages, data flow graphs, registers, system buses, timing model, buses, behavioral description, layout area |
37 | Wei Zhao, Christos A. Papachristou |
Architectural partitioning of control memory for application specific programmable processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1995, San Jose, California, USA, November 5-9, 1995, pp. 521-526, 1995, IEEE Computer Society / ACM, 0-8186-7213-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
application specific programmable processors, control memory, distributed microcode memory model, microcode memory, repetitive microcodes, distributed memory systems, memory architecture, programmability, microprogram, datapaths, firmware, memory module |
37 | Je-Hoon Lee, Seung-Sook Lee, Kyoung-Rok Cho |
Asynchronous ARM Processor Employing an Adaptive Pipeline Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARC ![In: Reconfigurable Computing: Architectures, Tools and Applications, Third International Workshop, ARC 2007, Mangaratiba, Brazil, March 27-29, 2007., pp. 39-48, 2007, Springer, 978-3-540-71430-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
adaptive pipeline, processor, Asynchronous design |
37 | Liang Han, Jie Chen 0012, Chaoxian Zhou, Ying Li, Xin Zhang, Zhibi Liu, Xiaoyun Wei, Baofeng Li |
An Embedded Reconfigurable SIMD DSP with Capability of Dimension-Controllable Vector Processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 11-13 October 2004, San Jose, CA, USA, Proceedings, pp. 446-451, 2004, IEEE Computer Society, 0-7695-2231-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
37 | Tay-Jyi Lin, Chein-Wei Jen |
CASCADE - configurable and scalable DSP environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2002 International Symposium on Circuits and Systems, ISCAS 2002, Scottsdale, Arizona, USA, May 26-29, 2002, pp. 870-873, 2002, IEEE, 0-7803-7448-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
33 | Namrata Shekhar, Priyank Kalla, M. Brandon Meredith, Florian Enescu |
Simulation Bounds for Equivalence Verification of Polynomial Datapaths Using Finite Ring Algebra. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 16(4), pp. 376-387, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
33 | Neal Tew, Priyank Kalla, Namrata Shekhar, Sivaram Gopalakrishnan |
Verification of arithmetic datapaths using polynomial function models and congruence solving. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2008 International Conference on Computer-Aided Design, ICCAD 2008, San Jose, CA, USA, November 10-13, 2008, pp. 122-128, 2008, IEEE Computer Society, 978-1-4244-2820-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
33 | Namrata Shekhar, Sudhakar Kalla, Florian Enescu |
Equivalence Verification of Polynomial Datapaths Using Ideal Membership Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(7), pp. 1320-1330, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
33 | Vyas Krishnan, Srinivas Katkoori |
A genetic algorithm for the design space exploration of datapaths during high-level synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Evol. Comput. ![In: IEEE Trans. Evol. Comput. 10(3), pp. 213-229, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
33 | Namrata Shekhar, Priyank Kalla, Florian Enescu |
Equivalence verification of arithmetic datapaths with multiple word-length operands. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006, pp. 824-829, 2006, European Design and Automation Association, Leuven, Belgium, 3-9810801-1-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
33 | Namrata Shekhar, Priyank Kalla, M. Brandon Meredith, Florian Enescu |
Simulation Bounds for Equivalence Verification of Arithmetic Datapaths with Finite Word-Length Operands. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FMCAD ![In: Formal Methods in Computer-Aided Design, 6th International Conference, FMCAD 2006, San Jose, California, USA, November 12-16, 2006, Proceedings, pp. 179-186, 2006, IEEE Computer Society, 0-7695-2707-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
33 | Masahiro Fujita |
Equivalence checking between behavioral and RTL descriptions with virtual controllers and datapaths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 10(4), pp. 610-626, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
formal verification, High-level synthesis, equivalence checking, behavior synthesis |
33 | Ranganath Gopalan, Chandramouli Gopalakrishnan, Srinivas Katkoori |
Leakage Power Driven Behavioral Synthesis of Pipelined Datapaths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), New Frontiers in VLSI Design, 11-12 May 2005, Tampa, FL, USA, pp. 167-172, 2005, IEEE Computer Society, 0-7695-2365-X. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
33 | Manjunath Kudlur, Kevin Fan, Michael L. Chu, Rajiv A. Ravindran, Nathan Clark, Scott A. Mahlke |
FLASH: Foresighted Latency-Aware Scheduling Heuristic for Processors with Customized Datapaths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CGO ![In: 2nd IEEE / ACM International Symposium on Code Generation and Optimization (CGO 2004), 20-24 March 2004, San Jose, CA, USA, pp. 201-212, 2004, IEEE Computer Society, 0-7695-2102-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
33 | Chandramouli Gopalakrishnan, Srinivas Katkoori |
An Architectural Leakage Power Simulator for VHDL Structural Datapaths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2003 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2003), New Trends and Technologies for VLSI Systems Design, 20-21 February 2003, Tampa, FL, USA, pp. 211-212, 2003, IEEE Computer Society, 0-7695-1904-0. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
33 | Chandramouli Gopalakrishnan, Srinivas Katkoori |
KnapBind: An Area-Efficient Binding Algorithm for Low-leakage Datapaths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 21st International Conference on Computer Design (ICCD 2003),VLSI in Computers and Processors, 13-15 October 2003, San Jose, CA, USA, Proceedings, pp. 430-435, 2003, IEEE Computer Society, 0-7695-2025-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
33 | Viktor S. Lapinskii, Margarida F. Jacome, Gustavo de Veciana |
Application-specific clustered VLIW datapaths: early exploration on a parameterized design space. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(8), pp. 889-903, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
33 | Katarzyna Radecka, Zeljko Zilic |
Specifying and verifying imprecise sequential datapaths by Arithmetic Transforms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, ICCAD 2002, San Jose, California, USA, November 10-14, 2002, pp. 128-131, 2002, ACM / IEEE Computer Society, 0-7803-7607-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
33 | Chandramouli Gopalakrishnan, Srinivas Katkoori |
Behavioral synthesis of datapaths with low leakage power. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2002 International Symposium on Circuits and Systems, ISCAS 2002, Scottsdale, Arizona, USA, May 26-29, 2002, pp. 699-702, 2002, IEEE, 0-7803-7448-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
33 | Nektarios Kranitis, Antonis M. Paschalis, Dimitris Gizopoulos, Mihalis Psarakis, Yervant Zorian |
An Effective Deterministic BIST Scheme for Shifter/Accumulator Pairs in Datapaths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 17(2), pp. 97-107, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
datapath test, shifter, Built-in self-test, accumulator, arithmetic-logic unit, processor test |
33 | Nektarios Kranitis, Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian |
An Effective Deterministic BIST Scheme for Shifter/Accumulator Pairs in Datapaths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 26-28 March 2001, San Jose, CA, USA, pp. 343-349, 2001, IEEE Computer Society, 0-7695-1025-6. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
33 | Montek Singh, Steven M. Nowick |
High-Throughput Asynchronous Pipelines for Fine-Grain Dynamic Datapaths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000), 2-6 April 2000, Eilat, Israel, pp. 198-, 2000, IEEE Computer Society, 0-7695-0586-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
fine-grain pipelining, VLSI, pipelines, asynchronous, dynamic logic, FIFO, high-throughput, digital design |
33 | Mahadevamurty Nemani, Vivek Tiwari |
Macro-driven circuit design methodology for high-performance datapaths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 37th Conference on Design Automation, Los Angeles, CA, USA, June 5-9, 2000., pp. 661-666, 2000, ACM. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
33 | David Berthelot, Marie-Lise Flottes, Bruno Rouzeyre |
BISTing Datapaths under Heterogeneous Test Schemes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 14(1-2), pp. 115-123, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
RT level, BIST, datapath, test synthesis |
33 | Darren C. Cronquist, Chris Fisher, Miguel E. Figueroa, Paul Franklin, Carl Ebeling |
Architecture Design of Reconfigurable Pipelined Datapaths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARVLSI ![In: 18th Conference on Advanced Research in VLSI (ARVLSI '99), 21-24 March 1999, Atlanta, GA, USA, pp. 23-41, 1999, IEEE Computer Society, 0-7695-0056-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
High-speed computation, Pipelining, Signal processing, Reconfigurable architectures, Configurable computing |
33 | Marie-Lise Flottes, R. Pires, Bruno Rouzeyre, Laurent Volpe |
Scanning Datapaths: A Fast and Effective Partial Scan Selection Technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1998 Design, Automation and Test in Europe (DATE '98), February 23-26, 1998, Le Palais des Congrès de Paris, Paris, France, pp. 921-922, 1998, IEEE Computer Society, 0-8186-8359-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
Scan chain selection, RT and gate levels, Partial scan, Synthesis for testability |
33 | Saman Adham, Sanjay Gupta |
DP-BIST: A Built-In Self Test For DSP DataPaths A Low Overhead and High Fault Coverage Technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 5th Asian Test Symposium (ATS '96), November 20-22, 1996, Hsinchu, Taiwan, pp. 205-212, 1996, IEEE Computer Society, 0-8186-7478-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
33 | Baher Haroun, Behzad Sajjadi |
Synthesis of Signal Processing Structured Datapaths for FPGAs Supporting RAMs and Busses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the Third International ACM Symposium on Field-Programmable Gate Arrays,FPGA 1995, Monterey, California, USA, February 12-14, 1995, pp. 75-81, 1995, ACM, 0-89791-743-X. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
25 | Juan Carlos López 0001, Fernando Rincón, Francisco Moya, José Manuel Moya |
Improving Embedded System Design by Means of HW-SW Compilation on Reconfigurable Coprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSS ![In: Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), October 2-4, 2002, Kyoto, Japan, pp. 255-260, 2002, ACM / IEEE Computer Society, 1-58113-576-9. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
reconfigurable datapaths, hardware-software codesign |
25 | H. Fatih Ugurdag, Thomas E. Fuhrman |
Autocircuit: a clock edge general behavioral synthesis system with a direct path to physical datapath. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1996 International Conference on Computer Design (ICCD '96), VLSI in Computers and Processors, October 7-9, 1996, Austin, TX, USA, Proceedings, pp. 514-529, 1996, IEEE Computer Society, 0-8186-7554-3. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
Autocircuit, clock edge general behavioral synthesis system, physical datapaths, next-generation synthesis tool, behavioral HDL input descriptions, data-flow representations, use-trees, raw-states, word-oriented synthesis, unique parameterized netlist representation, high level synthesis, high-level design |
24 | Yedidya Hilewitz, Ruby B. Lee |
Fast Bit Gather, Bit Scatter and Bit Permutation Instructions for Commodity Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Signal Process. Syst. ![In: J. Signal Process. Syst. 53(1-2), pp. 145-169, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Bit scatter, Bit gather, Parallel deposit, Unpack, Algorithm acceleration, Bioinformatics, Compression, Pattern matching, Steganography, Microprocessors, Permutations, Pack, Instruction set architecture, Cryptology, ISA, Parallel extract, Bit manipulations |
24 | Omkar Dandekar, William Plishker, Shuvra S. Bhattacharyya, Raj Shekhar |
Multiobjective Optimization of FPGA-Based Medical Image Registration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 16th IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2008, 14-15 April 2008, Stanford, Palo Alto, California, USA, pp. 183-192, 2008, IEEE Computer Society, 978-0-7695-3307-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
24 | Yee Jern Chong, Sri Parameswaran |
Rapid application specific floating-point unit generation with bit-alignment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008, pp. 62-67, 2008, ACM, 978-1-60558-115-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
bit-alignment, datapath merging, floating-point |
24 | Peter A. Milder, Franz Franchetti, James C. Hoe, Markus Püschel |
Formal datapath representation and manipulation for implementing DSP transforms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008, pp. 385-390, 2008, ACM, 978-1-60558-115-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
high-level synthesis, streaming, discrete Fourier transform, linear transform |
24 | Harmander Singh, Kanak Agarwal, Dennis Sylvester, Kevin J. Nowka |
Enhanced Leakage Reduction Techniques Using Intermediate Strength Power Gating. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 15(11), pp. 1215-1224, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
24 | Sotirios Xydis, George Economakos, Kiamal Z. Pekmestzi |
Flexibility Inlining into Arithmetic Data-paths Exploiting A Regular Interconnection Scheme. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICSAMOS ![In: Proceedings of the 2007 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (IC-SAMOS 2007), Samos, Greece, July 16-19, 2007, pp. 137-144, 2007, IEEE, 1-4244-1058-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
24 | Kristopher D. Peterson, Justin L. Tripp |
Effective Automatic Memory Allocation Algorithm Based on Schedule Length in Cycles in a Novel C to FPGA Compiler. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: FPL 2007, International Conference on Field Programmable Logic and Applications, Amsterdam, The Netherlands, 27-29 August 2007, pp. 745-748, 2007, IEEE, 1-4244-1060-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
24 | Kaushal R. Gandhi, Nihar R. Mahapatra |
Exploiting data-dependent slack using dynamic multi-VDD to minimize energy consumption in datapath circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006, pp. 1001-1006, 2006, European Design and Automation Association, Leuven, Belgium, 3-9810801-1-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
24 | William B. Toms, David A. Edwards, Andrew Bardsley |
Synthesising Heterogeneously Encoded Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2006), 13-15 March 2006, Grenoble, France, pp. 138-149, 2006, IEEE Computer Society, 0-7695-2498-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
24 | Xun Liu, Marios C. Papaefthymiou |
HyPE: hybrid power estimation for IP-based systems-on-chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(7), pp. 1089-1103, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
24 | Nahri Moreano, Edson Borin, Cid C. de Souza, Guido Araujo |
Efficient datapath merging for partially reconfigurable architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(7), pp. 969-980, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
24 | Abdelhalim Alsharqawi, Abdel Ejnioui |
Synthesis of Self-Resetting Stage Logic Pipelines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), New Frontiers in VLSI Design, 11-12 May 2005, Tampa, FL, USA, pp. 260-262, 2005, IEEE Computer Society, 0-7695-2365-X. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
24 | Dara Kusic, Raymond Hoare, Alex K. Jones, Joshua Fazekas, John Foster 0001 |
Extracting Speedup From C-Code With Poor Instruction-Level Parallelism. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), CD-ROM / Abstracts Proceedings, 4-8 April 2005, Denver, CO, USA, 2005, IEEE Computer Society, 0-7695-2312-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
24 | Philip Brisk, Adam Kaplan, Majid Sarrafzadeh |
Area-efficient instruction set synthesis for reconfigurable system-on-chip designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004, pp. 395-400, 2004, ACM, 1-58113-828-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
field-programmable gate array (FPGA), compiler, resource sharing, integer linear programming (ILP) |
24 | Jürgen Becker 0001, Alexander Thomas, Maik Scheer |
Efficient Processor Instruction Set Extension by Asynchronous Reconfigurable Datapath Integration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 16th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2003, Sao Paulo, Brazil, September 8-11, 2003, pp. 237-242, 2003, IEEE Computer Society, 0-7695-2009-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
24 | Amitabh Menon, S. K. Nandy 0001, Mahesh Mehendale |
Multivoltage scheduling with voltage-partitioned variable storage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003, Seoul, Korea, August 25-27, 2003, pp. 298-301, 2003, ACM, 1-58113-682-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
multivoltage, high level synthesis, datapath synthesis |
24 | Recep O. Ozdag, Peter A. Beerel, Montek Singh, Steven M. Nowick |
High-Speed Non-Linear Asynchronous Pipelines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2002 Design, Automation and Test in Europe Conference and Exposition (DATE 2002), 4-8 March 2002, Paris, France, pp. 1000-1007, 2002, IEEE Computer Society, 0-7695-1471-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
24 | María C. Molina, José M. Mendías, Román Hermida |
Bit-level scheduling of heterogeneous behavioural specifications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, ICCAD 2002, San Jose, California, USA, November 10-14, 2002, pp. 602-608, 2002, ACM / IEEE Computer Society, 0-7803-7607-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
24 | Leilei Song, Keshab K. Parhi, Ichiro Kuroda, Takao Nishitani |
Hardware/software codesign of finite field datapath for low-energy Reed-Solomon codecs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 8(2), pp. 160-172, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
24 | Joan Carletta, Christos A. Papachristou, Mehrdad Nourani |
Detecting Undetectable Controller Faults Using Power Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2000 Design, Automation and Test in Europe (DATE 2000), 27-30 March 2000, Paris, France, pp. 723-728, 2000, IEEE Computer Society / ACM, 0-7695-0537-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
24 | Kenneth Y. Yun |
Recent Advances in Asynchronous Design Methodologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 1999 Conference on Asia South Pacific Design Automation, Wanchai, Hong Kong, China, January 18-21, 1999, pp. 253-, 1999, IEEE Computer Society, 0-7803-5012-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
24 | Mehrdad Nourani, Joan Carletta, Christos A. Papachristou |
A Scheme for Integrated Controller-Datapath Fault Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 34st Conference on Design Automation, Anaheim, California, USA, Anaheim Convention Center, June 9-13, 1997., pp. 546-551, 1997, ACM Press, 0-89791-920-3. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
24 | Hong-Shin Jun, Sun-Young Hwang |
Design of a pipelined datapath synthesis system for digital signal processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 2(3), pp. 292-303, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
21 | Yongqiang Zhang 0006, Siting Liu 0001, Jie Han 0001, Zhendong Lin, Shaowei Wang, Xin Cheng 0001, Guangjun Xie |
An Energy-Efficient Binary-Interfaced Stochastic Multiplier Using Parallel Datapaths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 31(9), pp. 1439-1443, September 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
21 | Tomasz Osinski, Halina Tarasiuk |
New approaches to data plane programmability for software datapaths in the NFV infrastructure. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NetSoft ![In: 9th IEEE International Conference on Network Softwarization, NetSoft 2023, Madrid, Spain, June 19-23, 2023, pp. 320-325, 2023, IEEE, 979-8-3503-9980-6. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
21 | Nusa Zidaric, Mark D. Aagaard |
Tower field support for synthesis of datapaths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CF ![In: Proceedings of the 20th ACM International Conference on Computing Frontiers, CF 2023, Bologna, Italy, May 9-11, 2023, pp. 217-218, 2023, ACM. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
21 | Ahsen Ejaz, Ioannis Sourdis |
FastTrackNoC: A NoC with FastTrack Router Datapaths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: IEEE International Symposium on High-Performance Computer Architecture, HPCA 2022, Seoul, South Korea, April 2-6, 2022, pp. 971-985, 2022, IEEE, 978-1-6654-2027-3. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
21 | Samira Ait Bensaid, Mihail Asavoae, Farhat Thabet, Mathieu Jan |
Work in Progress: Automatic Construction of Pipeline Datapaths from High-Level HDL Code. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RTAS ![In: 28th IEEE Real-Time and Embedded Technology and Applications Symposium, RTAS 2022, Milano, Italy, May 4-6, 2022, pp. 305-308, 2022, IEEE, 978-1-6654-9998-9. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
21 | Daniel Vázquez, Alfonso Rodríguez 0002, Andrés Otero, Eduardo de la Torre |
Extending RISC-V Processor Datapaths with Multi-Grain Reconfigurable Overlays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DCIS ![In: 37th Conference on Design of Circuits and Integrated Systems, DCIS 2022, Pamplona, Spain, November 16-18, 2022, pp. 1-6, 2022, IEEE, 978-1-6654-5950-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
21 | Yoshiya Shikama, Ryuta Kawano, Hiroki Matsutani, Hideharu Amano, Yusuke Nagasaka, Naoto Fukumoto, Michihiro Koibuchi |
Low-Latency Low-Energy Memory-Cube Networks using Dual-Voltage Datapaths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PDP ![In: 29th Euromicro International Conference on Parallel, Distributed and Network-Based Processing, PDP 2021, Valladolid, Spain, March 10-12, 2021, pp. 143-147, 2021, IEEE, 978-1-6654-1455-5. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
21 | Inbal Stanger, Netanel Shavit, Ramiro Taco, Marco Lanuzza, Alexander Fish |
Live Demo: Silicon Evaluation of Multimode Dual Mode Logic for PVT-Aware Datapaths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2021, Daegu, South Korea, May 22-28, 2021, pp. 1, 2021, IEEE, 978-1-7281-9201-7. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
21 | Yiming Qiu, Hongyi Liu, Thomas E. Anderson, Yingyan Lin, Ang Chen 0001 |
Toward reconfigurable kernel datapaths with learned optimizations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HotOS ![In: HotOS '21: Workshop on Hot Topics in Operating Systems, Ann Arbor, Michigan, USA, June, 1-3, 2021., pp. 175-182, 2021, ACM, 978-1-4503-8438-4. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
21 | Philip Rohde |
Merging Datapaths using Data Processing Graphs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2021 |
RDF |
|
21 | Mohammad Reza Esmaeili, Seyed Hamid Zahiri, Seyed Mohammad Razavi |
A novel method for high-level synthesis of datapaths in digital filters using a moth-flame optimization algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Evol. Intell. ![In: Evol. Intell. 13(3), pp. 399-414, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
21 | Inbal Stanger, Netanel Shavit, Ramiro Taco, Marco Lanuzza, Alexander Fish |
Silicon Evaluation of Multimode Dual Mode Logic for PVT-Aware Datapaths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 67-II(9), pp. 1639-1643, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
21 | Vasileios Kokkinos, Athanasios Kakarountas |
Design of Reconfigurable Fault-Tolerant Datapaths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SEEDA-CECNSM ![In: 5th South-East Europe Design Automation, Computer Engineering, Computer Networks and Social Media Conference, SEEDA-CECNSM 2020, Corfu, Greece, September 25-27, 2020, pp. 1-6, 2020, IEEE, 978-1-7281-6445-8. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
21 | Loris Duch, Soumya Basu 0002, Miguel Peón Quirós, Giovanni Ansaloni, Laura Pozzi, David Atienza |
i-DPs CGRA: An Interleaved-Datapaths Reconfigurable Accelerator for Embedded Bio-Signal Processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Embed. Syst. Lett. ![In: IEEE Embed. Syst. Lett. 11(2), pp. 50-53, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
21 | Keith A. Campbell, Chen-Hsuan Lin, Deming Chen |
Cost-Effective Error Detection Through Mersenne Modulo Shadow Datapaths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(6), pp. 1056-1069, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
21 | Alberto A. Del Barrio, Román Hermida, Seda Ogrenci Memik |
A Combined Arithmetic-High-Level Synthesis Solution to Deploy Partial Carry-Save Radix-8 Booth Multipliers in Datapaths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(2), pp. 742-755, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
21 | Alexander J. Groszewski, Travis Lenz |
Deterministic Stochastic Computation Using Parallel Datapaths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 20th International Symposium on Quality Electronic Design, ISQED 2019, Santa Clara, CA, USA, March 6-7, 2019, pp. 138-144, 2019, IEEE, 978-1-7281-0392-1. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
21 | Paul Chaignon |
Software Datapaths for Multi-Tenant Packet Processing. (Plans de données logiciels pour les traitements réseaux en environnements partagés). ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2019 |
RDF |
|
21 | Arman Roohi, Ronald F. DeMara |
NV-Clustering: Normally-Off Computing Using Non-Volatile Datapaths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 67(7), pp. 949-959, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
21 | Sana Mazahir, Osman Hasan, Muhammad Shafique 0001 |
Adaptive Approximate Computing in Arithmetic Datapaths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test ![In: IEEE Des. Test 35(4), pp. 65-74, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
21 | Bruno Miguel Gil Rosa, Henry M. D. Ip, Guang-Zhong Yang |
Wireless Datapaths and Security. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Implantable Sensors and Systems ![In: Implantable Sensors and Systems, From Theory to Practice., pp. 595-635, 2018, Springer, 978-3-319-69747-5. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
21 | Mohammad Saber Golanbari, Mehdi Baradaran Tahoori |
Optimizing Datapaths for Near Threshold Computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SMACD ![In: 15th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2018, Prague, Czech Republic, July 2-5, 2018, pp. 69-72, 2018, IEEE, 978-1-5386-5153-7. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
21 | Christopher Leet, Xin Wang, Yang Richard Yang, James Aspnes |
Toward the First SDN Programming Capacity Theorem on Realizing High-Level Programs on Low-Level Datapaths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
INFOCOM ![In: 2018 IEEE Conference on Computer Communications, INFOCOM 2018, Honolulu, HI, USA, April 16-19, 2018, pp. 711-719, 2018, IEEE, 978-1-5386-4128-6. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
21 | Sheikh Ariful Islam, Srinivas Katkoori |
High-level synthesis of key based obfuscated RTL datapaths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 19th International Symposium on Quality Electronic Design, ISQED 2018, Santa Clara, CA, USA, March 13-14, 2018, pp. 407-412, 2018, IEEE, 978-1-5386-1214-9. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
21 | Amir Sabbagh Molahosseini, Azadeh Alsadat Emrani Zarandi, Paulo Martins 0002, Leonel Sousa |
A Multifunctional Unit for Designing Efficient RNS-Based Datapaths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 5, pp. 25972-25986, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
21 | Matei Istoan, Florent de Dinechin |
Automating the pipeline of arithmetic datapaths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation & Test in Europe Conference & Exhibition, DATE 2017, Lausanne, Switzerland, March 27-31, 2017, pp. 704-709, 2017, IEEE, 978-3-9815370-8-6. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
21 | Philip Gottschling, Christian Hochberger |
ReEP: A Toolset for Generation and Programming of Reconfigurable Datapaths for Event Processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS Workshops ![In: 2017 IEEE International Parallel and Distributed Processing Symposium Workshops, IPDPS Workshops 2017, Orlando / Buena Vista, FL, USA, May 29 - June 2, 2017, pp. 141-149, 2017, IEEE Computer Society, 978-1-5386-3408-0. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
21 | Aurojit Panda, Ori Lahav 0001, Katerina J. Argyraki, Mooly Sagiv, Scott Shenker |
Verifying Reachability in Networks with Mutable Datapaths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NSDI ![In: 14th USENIX Symposium on Networked Systems Design and Implementation, NSDI 2017, Boston, MA, USA, March 27-29, 2017, pp. 699-718, 2017, USENIX Association, 978-1-931971-37-9. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP BibTeX RDF |
|
21 | Aurojit Panda, Ori Lahav 0001, Katerina J. Argyraki, Mooly Sagiv, Scott Shenker |
Verifying Reachability in Networks with Mutable Datapaths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1607.00991, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP BibTeX RDF |
|
21 | Rei Ueno, Sumio Morioka, Naofumi Homma, Takafumi Aoki |
A High Throughput/Gate AES Hardware Architecture by Compressing Encryption and Decryption Datapaths - Toward Efficient CBC-Mode Implementation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IACR Cryptol. ePrint Arch. ![In: IACR Cryptol. ePrint Arch. 2016, pp. 595, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP BibTeX RDF |
|
21 | Donghai Li, Xiaochen Zhu, Zhonglei Fan, Xiaojun Yang |
多项式数据通路的优化方法 (Method of Optimization for Polynomial Datapaths). ![Search on Bibsonomy](Pics/bibsonomy.png) |
计算机科学 ![In: 计算机科学 43(Z11), pp. 517-519, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
21 | Xiaobo Yin, Feng Yu 0003, Zhen-guo Ma |
Resource-Efficient Pipelined Architectures for Radix-2 Real-Valued FFT With Real Datapaths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 63-II(8), pp. 803-807, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
21 | Nachiket Kapre, Deheng Ye |
GPU-Accelerated High-Level Synthesis for Bitwidth Optimization of FPGA Datapaths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Monterey, CA, USA, February 21-23, 2016, pp. 185-194, 2016, ACM, 978-1-4503-3856-1. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
21 | Rei Ueno, Sumio Morioka, Naofumi Homma, Takafumi Aoki |
A High Throughput/Gate AES Hardware Architecture by Compressing Encryption and Decryption Datapaths - Toward Efficient CBC-Mode Implementation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHES ![In: Cryptographic Hardware and Embedded Systems - CHES 2016 - 18th International Conference, Santa Barbara, CA, USA, August 17-19, 2016, Proceedings, pp. 538-558, 2016, Springer, 978-3-662-53139-6. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|