Search results for "dual-core"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
60	Jia-Ming Chen, Chih-Hao Chang, Shau-Yin Tseng, Jenq Kuen Lee, Wei-Kuan Shih	Power Aware H.264/AVC Video Player on PAC Dual-Core SoC Platform.	EUC	2006	DBLP DOI BibTeX RDF	Dual-Core SoC, H.264/AVC, Power-aware, DVFS
54	Kun-Yuan Hsieh, Yen-Chih Liu, Po-Wen Wu, Shou-Wei Chang, Jenq Kuen Lee	Enabling Streaming Remoting on Embedded Dual-Core Processors.	ICPP	2008	DBLP DOI BibTeX RDF
51	Pawel Gepner, David L. Fraser, Michal Filip Kowalik	Performance Evolution and Power Benefits of Cluster System Utilizing Quad-Core and Dual-Core Intel Xeon Processors.	PPAM	2007	DBLP DOI BibTeX RDF	dual-core processors, quad-core processors, parallel processing, benchmarks, HPC, multi-core processors
47	George S. Almási, Leonardo R. Bachega, Siddhartha Chatterjee, Manish Gupta 0002, Derek Lieber, Xavier Martorell, José E. Moreira	Enabling Dual-Core Mode in BlueGene/L: Challenges and Solutions.	SBAC-PAD	2003	DBLP DOI BibTeX RDF
46	Lu Peng 0001, Jih-Kwon Peir, Tribuvan K. Prakash, Yen-Kuang Chen, David M. Koppelman	Memory Performance and Scalability of Intel's and AMD's Dual-Core Processors: A Case Study.	IPCCC	2007	DBLP DOI BibTeX RDF
46	Chun-Hao Hsu, Jian Jhen Chen, Shiao-Li Tsao	Evaluation and modeling of power consumption of a heterogeneous dual-core processor.	ICPADS	2007	DBLP DOI BibTeX RDF
42	Toshinari Takayanagi, Jinuk Luke Shin, Bruce Petrick, Jeffrey Y. Su, Ana Sonia Leon	A dual-core 64b ultraSPARC microprocessor for dense server applications.	DAC	2004	DBLP DOI BibTeX RDF	L2, UltraSPARC, coupling noise, deep submicron technology, dense server, dual-core, throughput computing, cache, multiprocessor, leakage, NBTI, negative bias temperature instability
40	Daisuke Takahashi	An Implementation of Parallel 1-D FFT Using SSE3 Instructions on Dual-Core Processors.	PARA	2006	DBLP DOI BibTeX RDF
39	Christian El Salloum, Andreas Steininger, Peter Tummeltshammer, Werner Harter	Recovery Mechanisms for Dual Core Architectures.	DFT	2006	DBLP DOI BibTeX RDF
39	Cheng-Nan Chiu, Chien-Tang Tseng, Chun-Jen Tsai	Tightly-coupled MPEG-4 video encoder framework on asymmetric dual-core platforms.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
36	Ryan E. Grant, Ahmad Afsahi	A Comprehensive Analysis of OpenMP Applications on Dual-Core Intel Xeon SMPs.	IPDPS	2007	DBLP DOI BibTeX RDF
36	Rui Gong, Kui Dai, Zhiying Wang 0003	Transient Fault Tolerance on Chip Multiprocessor Based on Dual and Triple Core Redundancy.	PRDC	2008	DBLP DOI BibTeX RDF
34	Fadi N. Sibai	Evaluating the performance of single and multiple core processors with PCMARK®05 and benchmark analysis.	SIGMETRICS Perform. Evaluation Rev.	2008	DBLP DOI BibTeX RDF	performance benchmark, single and dual core processors, workload characterization
33	Kwangsik Kim, Dohun Kim, Chanik Park	Real-time Scheduling in Heterogeneous Dual-core Architectures.	ICPADS (2)	2006	DBLP DOI BibTeX RDF
33	Dhiraj D. Kalamkar, Mainak Chaudhuri, Mark A. Heinrich	Simplifying Active Memory Clusters by Leveraging Directory Protocol Threads.	ISPASS	2007	DBLP DOI BibTeX RDF	active memory cluster, directory protocol thread, active memory address remapping, parallel reduction, coherence protocol extension, software protocol, multi-threaded node, dual-core node, active memory architecture, distributed shared memory, multiprocessor architecture, memory controller, matrix transpose
32	Iman Faraji, Moslem Didehban, Hamid R. Zarandi	Analysis of Transient Faults on a MIPS-Based Dual-Core Processor.	ARES	2010	DBLP DOI BibTeX RDF	Dual-core microprocessor, Microprocessor without Interlocked Pipeline Stages (MIPS), simulation-based fault injection, vulnerability analysis, fault propagation
32	Chih-Lun Fang, Tsung-Han Tsai 0001, Ren-Chih Kuo	Design and Implementation of a Videotext Extractor on Dual-Core Platform.	APSCC	2008	DBLP DOI BibTeX RDF
30	Rui Gong, Kui Dai, Zhiying Wang 0003	Transient Fault Recovery on Chip Multiprocessor based on Dual Core Redundancy and Context Saving.	ICYCS	2008	DBLP DOI BibTeX RDF
30	Eric S. Fetzer	Using Adaptive Circuits to Mitigate Process Variations in a Microprocessor Design.	IEEE Des. Test Comput.	2006	DBLP DOI BibTeX RDF	dual core, Itanium microprocessor, Montecito, adaptive circuits, cache safe technology, active clock deskew, process variation, power measurement
29	Hee Seo, Seon Wook Kim	OpenMP Directive Extension for BlackFin 561 Dual Core Processor.	CIT	2006	DBLP DOI BibTeX RDF
28	Meilian Xu, Parimala Thulasiraman	Parallel Algorithm Design and Performance Evaluation of FDTD on 3 Different Architectures: Cluster, Homogeneous Multicore and Cell/B.E.	HPCC	2008	DBLP DOI BibTeX RDF
28	Sadaf R. Alam, Pratul K. Agarwal	On the Path to Enable Multi-scale Biomolecular Simulations on PetaFLOPS Supercomputer with Multi-core Processors.	IPDPS	2007	DBLP DOI BibTeX RDF
27	Viren Kumar, James P. Delgrande	Optimal Multicore Scheduling: An Application of ASP Techniques.	LPNMR	2009	DBLP DOI BibTeX RDF	clingo, edge cover, scheduling, multicore, ASP
27	Kiyotaka Takahashi, Eigo Mori	Architectural Design of a DSP Scripting Language for Mobile Multimedia Terminals.	AINA (2)	2004	DBLP DOI BibTeX RDF
26	Noriyuki Ito, Hiroaki Komatsu, Akira Kanuma, Akihiro Yoshitake, Yoshiyasu Tanamura, Hiroyuki Sugiyama, Ryoichi Yamashita, Ken-ichi Nabeya, Hironobu Yoshino, Hitoshi Yamanaka, Masahiro Yanagida, Yoshitomo Ozeki, Kinya Ishizaka, Takeshi Kono, Yutaka Isoda	Design Methodology for 2.4GHz Dual-Core Microprocessor.	ASP-DAC	2007	DBLP DOI BibTeX RDF
26	Jianxun Jason Ding, Abdul Waheed	Dual Processor Performance Characterization for XML Application-Oriented Networking.	ICPP	2007	DBLP DOI BibTeX RDF
25	Thomas Kottke, Andreas Steininger	A Reconfigurable Generic Dual-Core Architecture.	DSN	2006	DBLP DOI BibTeX RDF
25	Huiyang Zhou	Dual-Core Execution: Building a Highly Scalable Single-Thread Instruction Window.	IEEE PACT	2005	DBLP DOI BibTeX RDF
24	Abdullah Kayi, Yiyi Yao, Tarek A. El-Ghazawi, Gregory B. Newby	Experimental Evaluation of Emerging Multi-core Architectures.	IPDPS	2007	DBLP DOI BibTeX RDF
24	Mark C. Johnson, Eric P. Villasenor, Olga Krachina, Mithuna Thottethodi	Undergraduate dual-core prototyping and analysis of factors influencing student success on dual-core designs.	MSE	2009	DBLP DOI BibTeX RDF
22	Yi Ma, Hongliang Gao, Martin Dimitrov, Huiyang Zhou	Optimizing Dual-Core Execution for Power Efficiency and Transient-Fault Recovery.	IEEE Trans. Parallel Distributed Syst.	2007	DBLP DOI BibTeX RDF	Multiple data stream architectures, fault tolerance, low-power design
22	Michael G. Benjamin, David R. Kaeli	Stream Image Processing on a Dual-Core Embedded System.	SAMOS	2007	DBLP DOI BibTeX RDF
20	Carol Currie Sobczak, James Kessler, David Eldridge	The dual os classroom: if you build it, will they come?	SIGUCCS	2007	DBLP DOI BibTeX RDF	boot camp, deep freeze, intel dual core, winbatch, parallels, imaging, deployment, support, classroom technology
20	David Geer	Industry Trends: Chip Makers Turn to Multicore Processors.	Computer	2005	DBLP DOI BibTeX RDF	dual-core chips, processor architectures, multicore processors
20	Tay-Jyi Lin, Chie-Min Chao, Chia-Hsien Liu, Pi-Chen Hsiao, Shin-Kai Chen, Li-Chun Lin, Chih-Wei Liu, Chein-Wei Jen	A unified processor architecture for RISC & VLIW DSP.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	dual-core processor, register organization, variable-length instruction encoding, digital signal processor
20	Hossein Pourreza, Peter Graham	On the Programming Impact ofMulti-Core, Multi-Processor Nodes inMPI Clusters.	HPCS	2007	DBLP DOI BibTeX RDF
20	James Donald, Margaret Martonosi	An Efficient, Practical Parallelization Methodology for Multicore Architecture Simulation.	IEEE Comput. Archit. Lett.	2006	DBLP DOI BibTeX RDF
20	Hisashige Ando, Nestoras Tzartzanis, William W. Walker	A Case Study: Power and Performance Improvement of a Chip Multiprocessor for Transaction Processing.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
19	Pranav Vaidya, Jaehwan John Lee	Characterization of TPC-H queries for a column-oriented database on a dual-core amd athlon processor.	CIKM	2008	DBLP DOI BibTeX RDF	column-oriented databases, monetdb, tpc-h, performance profiling
19	Eva Beckschulze, Falk Salewski, Thomas Siegbert, Stefan Kowalewski	Fault Handling Approaches on Dual-Core Microcontrollers in Safety-Critical Automotive Applications.	ISoLA	2008	DBLP DOI BibTeX RDF
19	Rod Fatoohi	Performance Evaluation of the Dual-Core Based SGI Altix 4700.	SBAC-PAD	2007	DBLP DOI BibTeX RDF
19	Raj Varada, Mysore Sriram, Kris Chou, James Guzzo	Design and integration methods for a multi-threaded dual core 65nm Xeon® processor.	ICCAD	2006	DBLP DOI BibTeX RDF	Xeon®, Integration, Design Methods, processor
19	Prachuryya Subash Das, Deepjyoti Deb, Rupam Goswami, Santanu Sharma, Rajesh Saha	Fin core dimensionality and corner effect in dual core gate-all-around FinFET.	Microelectron. J.	2024	DBLP DOI BibTeX RDF
19	Sujoy Pandit, Prateek Sikka	Design and Implementation of Power Optimized Dual Core and Single Core DLX Processor on FPGA.	ICCCNT	2018	DBLP DOI BibTeX RDF
19	Dragan S. Rakic, Dragan S. Djordjevic	Star, sharp, core and dual core partial order in rings with involution.	Appl. Math. Comput.	2015	DBLP DOI BibTeX RDF
19	Fan Xu, Li Shen 0007, Zhiying Wang 0003, Hui Guo 0004, Bo Su, Wei Chen 0009	Customized Core Layout: A Case Study on Dual-Core Dynamic Binary Translation System.	CIT	2014	DBLP DOI BibTeX RDF
19	Rajesh Kannan Megalingam, Ashwin Mohan, Shekhil Hassan Thavalengal, Tanmay Muralidhar Rao, Vivek Periye	Low Power Single Core CPU for a Dual Core Microcontroller.	ICETET	2010	DBLP DOI BibTeX RDF
19	Lei Chai, Qi Gao 0004, Dhabaleswar K. Panda 0001	Understanding the Impact of Multi-Core Architecture in Cluster Computing: A Case Study with Intel Dual-Core System.	CCGRID	2007	DBLP DOI BibTeX RDF
18	Ashley M. DeFlumere, Sadaf R. Alam	Exploring multi-core limitations through comparison of contemporary systems.	Richard Tapia Celebration of Diversity in Computing Conference	2009	DBLP DOI BibTeX RDF	performance evaluation and analysis, benchmarking, multi-core processor
18	Sadaf R. Alam, Pratul K. Agarwal, Scott S. Hampton, Hong Ong	Experimental Evaluation of Molecular Dynamics Simulations on Multi-core Systems.	HiPC	2008	DBLP DOI BibTeX RDF	Performance, Multicore, HPC, Molecular Dynamics Simulation
18	Tay-Jyi Lin, Hung-Yueh Lin, Chie-Min Chao, Chih-Wei Liu, Chih-Wei Jen	A Compact DSP Core with Static Floating-Point Arithmetic.	J. VLSI Signal Process.	2006	DBLP DOI BibTeX RDF
18	Shih-Hao Ou, Tay-Jyi Lin, Chao-Wei Huang, Yu-Ting Kuo, Chie-Min Chao, Chih-Wei Liu, Chein-Wei Jen	A 52mW 1200MIPS compact DSP for multi-core media SoC.	ASP-DAC	2006	DBLP DOI BibTeX RDF
18	Tay-Jyi Lin, Hung-Yueh Lin, Chie-Min Chao, Chih-Wei Liu, Chein-Wei Jen	A compact DSP core with static floating-point unit & its microcode generation.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	DSP core, digital signal processor, floating-point units
17	Yuhang Liu, Haifeng Ma	Dual core generalized inverse of third-order dual tensor based on the T-product.	Comput. Appl. Math.	2022	DBLP DOI BibTeX RDF
17	Wei Deng 0001, Haikun Jia, Rui Wu 0001, Shiyan Sun, Chenggang Li, Zhihua Wang 0001, Baoyong Chi	An 8.2-to-21.5 GHz Dual-Core Quad-Mode Orthogonal-Coupled VCO with Concurrently Dual-Output using Parallel 8-Shaped Resonator.	CICC	2021	DBLP DOI BibTeX RDF
17	Haixia Han, Donglian Hou, Nannan Luan, Zhenxu Bai, Li Song, Jianfei Liu, Yongsheng Hu	Surface Plasmon Resonance Sensor Based on Dual-Side Polished Microstructured Optical Fiber with Dual-Core.	Sensors	2020	DBLP DOI BibTeX RDF
17	José Luis García-Lapresta, Ricardo Alberto Marques Pereira	The self-dual core and the anti-self-dual remainder of an aggregation operator.	Fuzzy Sets Syst.	2008	DBLP DOI BibTeX RDF
17	Cameron McNairy, Rohit Bhatia	Montecito: A Dual-Core, Dual-Thread Itanium Processor.	IEEE Micro	2005	DBLP DOI BibTeX RDF	Reliability, Power Management, Cache memories, Multithreaded processors, Testing and Fault-Tolerance
17	Rod Fatoohi	Performance evaluation of NSF application benchmarks on parallel systems.	IPDPS	2008	DBLP DOI BibTeX RDF
17	Subhash Saini, Dale Talcott, Dennis C. Jespersen, M. Jahed Djomehri, Haoqiang Jin, Rupak Biswas	Scientific application-based performance comparison of SGI Altix 4700, IBM POWER5+, and SGI ICE 8200 supercomputers.	SC	2008	DBLP DOI BibTeX RDF
17	Damian Dechev, Peter Pirkelbauer, Bjarne Stroustrup	Lock-Free Dynamically Resizable Arrays.	OPODIS	2006	DBLP DOI BibTeX RDF	real-time systems, concurrency, C++, vector, lock-free, STL
16	Peter Tummeltshammer, Andreas Steininger	On the role of the power supply as an entry for common cause faults - An experimental analysis.	DDECS	2009	DBLP DOI BibTeX RDF
16	Ralph K. Cavin III, James A. Hutchby, Victor V. Zhirnov, Joe E. Brewer, George Bourianoff	Emerging Research Architectures.	Computer	2008	DBLP DOI BibTeX RDF
16	Jaime H. Moreno	Chip-level integration: the new frontier for microprocessor architecture.	SPAA	2006	DBLP DOI BibTeX RDF	chip-level integration, microprocessor architecture
14	Dong Hyuk Woo, Hsien-Hsin S. Lee	PROPHET: goal-oriented provisioning for highly tunable multicore processors in cloud computing.	ACM SIGOPS Oper. Syst. Rev.	2009	DBLP DOI BibTeX RDF
14	Matin Hashemi, Soheil Ghiasi	Exact and Approximate Task Assignment Algorithms for Pipelined Software Synthesis.	DATE	2008	DBLP DOI BibTeX RDF
14	George Teodoro, Daniel Fireman, Dorgival Olavo Guedes Neto, Wagner Meira Jr., Renato Ferreira 0001	Achieving Multi-Level Parallelism in the Filter-Labeled Stream Programming Model.	ICPP	2008	DBLP DOI BibTeX RDF
14	Pitch Patarasuk, Xin Yuan 0001	Bandwidth Efficient All-reduce Operation on Tree Topologies.	IPDPS	2007	DBLP DOI BibTeX RDF
14	Wenlong Li, Xiaofeng Tong, Yimin Zhang 0002	Optimization and Parallelization on a Multimeida Application.	ICME	2007	DBLP DOI BibTeX RDF
14	Rikun Liao, Yuefeng Ji, Hui Li 0033	Interface Design and QoS Performance of Video Monitor System.	ICICIC (3)	2006	DBLP DOI BibTeX RDF
14	Ali El-Moursy, Rajeev Garg, David H. Albonesi, Sandhya Dwarkadas	Compatible phase co-scheduling on a CMP of multi-threaded processors.	IPDPS	2006	DBLP DOI BibTeX RDF
14	Jonathan Ezekiel, Gerald Lüttgen, Radu Siminiceanu	Can Saturation Be Parallelised?	FMICS/PDMC	2006	DBLP DOI BibTeX RDF
14	Lei Chai, Albert Hartono, Dhabaleswar K. Panda 0001	Designing High Performance and Scalable MPI Intra-node Communication Support for Clusters.	CLUSTER	2006	DBLP DOI BibTeX RDF
13	Sadaf R. Alam, Richard F. Barrett, Heike Jagode, Jeffery A. Kuehn, Stephen W. Poole, Ramanan Sankaran	Impact of Quad-Core Cray XT4 System and Software Stack on Scientific Computation.	Euro-Par	2009	DBLP DOI BibTeX RDF
13	Pascal Vezolle, Stéphane Vialle, Xavier Warin	Large scale experiment and optimization of a distributed stochastic control algorithm. Application to energy management problems.	IPDPS	2009	DBLP DOI BibTeX RDF
13	Jing Liang, Yinqin Wu	Wireless ECG Monitoring System Based on OMAP.	CSE (2)	2009	DBLP DOI BibTeX RDF
13	Noriko Takagi, Hiroshi Sasaki 0001, Masaaki Kondo, Hiroshi Nakamura	Cooperative shared resource access control for low-power chip multiprocessors.	ISLPED	2009	DBLP DOI BibTeX RDF	low power, chip multiprocessors, cache partitioning, dvfs, resource conflict
13	Qian Diao, Justin J. Song	Prediction of CPU idle-busy activity pattern.	HPCA	2008	DBLP DOI BibTeX RDF
13	Kostas Papadopoulos, Kyriakos Stavrou, Pedro Trancoso	HelperCoreDB: Exploiting multicore technology to improve database performance.	IPDPS	2008	DBLP DOI BibTeX RDF
13	Partha Tirumalai, Yonghong Song, Spiros Kalogeropulos	Performance Evaluation of Evolutionary Multi-core and Aggressively Multi-threaded Processor Architectures.	Asia-Pacific Computer Systems Architecture Conference	2007	DBLP DOI BibTeX RDF
13	Sadaf R. Alam, Jeremy S. Meredith, Jeffrey S. Vetter	Balancing productivity and performance on the cell broadband engine.	CLUSTER	2007	DBLP DOI BibTeX RDF
13	Sadaf R. Alam, Richard F. Barrett, Jeffery A. Kuehn, Philip C. Roth, Jeffrey S. Vetter	Characterization of Scientific Workloads on Systems with Multi-Core Processors.	IISWC	2006	DBLP DOI BibTeX RDF
13	Guilherme Ottoni, Ram Rangan, Adam Stoler, David I. August	Automatic Thread Extraction with Decoupled Software Pipelining.	MICRO	2005	DBLP DOI BibTeX RDF
12	Zhenkun Shi, Sen Wang 0001, Lin Yue, Yijia Zhang, Binod Kumar Adhikari, Shuai Xue, Wanli Zuo, Xue Li 0001	Dual-core mutual learning between scoring systems and clinical features for ICU mortality prediction.	Inf. Sci.	2023	DBLP DOI BibTeX RDF
12	Demyana Emil, Mohammed Hamdy, Gihan Nagib	Development an efficient AXI-interconnect unit between set of customized peripheral devices and an implemented dual-core RISC-V processor.	J. Supercomput.	2023	DBLP DOI BibTeX RDF
12	Xi Meng, Haoran Li, Peng Chen 0022, Jun Yin 0001, Pui-In Mak, Rui Paulo Martins	Analysis and Design of a 15.2-to-18.2-GHz Inverse-Class-F VCO With a Balanced Dual-Core Topology Suppressing the Flicker Noise Upconversion.	IEEE Trans. Circuits Syst. I Regul. Pap.	2023	DBLP DOI BibTeX RDF
12	Satyam Shukla, Utkarsh, Md Azam, Kailash Chandra Ray	An Efficient Fault-Tolerant Instruction Decoder for RISC-V Based Dual-Core Soft-Processors.	IEEE Trans. Circuits Syst. I Regul. Pap.	2023	DBLP DOI BibTeX RDF
12	Jiayue Wan, Zesong Fei, Zicheng Liu 0009, Quanwen Qi, Fang Han, Xiaoran Li, Zhiming Chen 0001	A 20.65-to-40.55 GHz Dual-Core Quad-Mode VCO With Mode-Independent Transformer-Switching Technique in 65-nm CMOS.	IEEE Trans. Circuits Syst. II Express Briefs	2023	DBLP DOI BibTeX RDF
12	Pegdwende Romaric Nikiema, Angeliki Kritikakou, Marcello Traiola, Olivier Sentieys	Design with low complexity fine-grained Dual Core Lock-Step (DCLS) RISC-V processors.	DSN-S	2023	DBLP DOI BibTeX RDF
12	Duc M. Tran, Joon-Young Choi	Distributed Data Logger Based on Dual-Core MCU in Motor Drive.	MCSoC	2023	DBLP DOI BibTeX RDF
12	Marcello Barbirotta, Francesco Menichelli, Antonio Mastrandrea, Abdallah Cheikh, Marco Angioli, Saeid Jamili, Mauro Olivieri	Heterogeneous Tightly-Coupled Dual Core Architecture Against Single Event Effects.	ApplePies	2023	DBLP DOI BibTeX RDF
12	Qixiu Wu, Wei Deng 0001, Haikun Jia, Hongzhuo Liu, Shiwei Zhang, Zhihua Wang 0001, Baoyong Chi	An 11.5-to-14.3GHz 192.8dBc/Hz FoM at 1MHz Offset Dual-Core Enhanced Class-F VCO with Common-Mode-Noise Self-Cancellation and Isolation Technique.	ISSCC	2023	DBLP DOI BibTeX RDF
12	Jian-Lin Zeng, Tsung-Yi Wu, Don-Gey Liu, Ching-Hwa Cheng	Live Demonstration: A Low-Power Dual-Core Motion Estimation Chip Design and Validation for a Wireless Panoramic Endoscopy.	ISCAS	2023	DBLP DOI BibTeX RDF
12	Jian-Lin Zeng, Tsung-Yi Wu, Don-Gey Liu, Ching-Hwa Cheng	A Low-Power Dual-Core Motion Estimation Chip Design and Validation for a Wireless Panoramic Endoscopy.	ISCAS	2023	DBLP DOI BibTeX RDF
12	Xiangjian Kong, Ding Qiu, Mingchao Jian, Chunbing Guo, Kai Xu	A Dual-Core Quad_Mode VCO with Reconfigurable Magnetic Coupling Mode and Negative-Resistive Mode Switch.	ASICON	2023	DBLP DOI BibTeX RDF
12	Zheng Xu, Xinjie Zhou, Zhiqiang Xiao	A Hardware Backup Dual-Core Lockstep for Error Checking and Recovery.	EITCE	2023	DBLP DOI BibTeX RDF
12	Tonglei Cheng, Bin Li 0066, Fan Zhang 0065, Wei Liu 0133, Xiaoyu Chen, Yuanhongliu Gao, Xin Yan 0004, Xuenan Zhang, Fang Wang, Takenobu Suzuki, Yasutake Ohishi	A Sagnac Interferometer-Based Twist Angle Sensor Drawing on an Eccentric Dual-Core Fiber.	IEEE Trans. Instrum. Meas.	2022	DBLP DOI BibTeX RDF
12	Yujun Xie, Yuan Liu 0022, Xin Zheng 0001, Wenhao Zhu, Junxian Li, Jianzhong Li, Shuting Cai, Xiaoming Xiong	A Dual-Core High-Performance Processor for Elliptic Curve Cryptography in GF(p) Over Generic Weierstrass Curves.	IEEE Trans. Circuits Syst. II Express Briefs	2022	DBLP DOI BibTeX RDF
12	Ethan Chou, Lorenzo Iotti, Ali M. Niknejad	Design of an Inductor-Less 72-GHz 2: 1 CMOS CML Frequency Divider With Dual-Core VCO.	IEEE Trans. Circuits Syst. II Express Briefs	2022	DBLP DOI BibTeX RDF
12	Zhenkun Shi, Qianqian Yuan, Ruoyu Wang 0025, Hoaran Li, Xiaoping Liao, Hongwu Ma	ECRECer: Enzyme Commission Number Recommendation and Benchmarking based on Multiagent Dual-core Learning.	CoRR	2022	DBLP BibTeX RDF