Search results for "floorplanner"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
103	Vinod Narayananan, David LaPotin, Rajesh Gupta 0003, Gopalakrishnan Vijayan	PEPPER - a timing driven early floorplanner.	ICCD	1995	DBLP DOI BibTeX RDF	PEPPER, timing driven early floorplanner, chip complexities, early analysis, performance critical CMOS chips, wireability, floorplan optimization process, performance, computational complexity, optimisation, timing, system design, circuit layout CAD, CMOS integrated circuits, static timing analysis, integrated circuit layout, area, interconnect delay
75	Ou He, Sheqin Dong, Jinian Bian, Satoshi Goto, Chung-Kuan Cheng	A novel fixed-outline floorplanner with zero deadspace for hierarchical design.	ICCAD	2008	DBLP DOI BibTeX RDF	floorplanner, soft modules, zero deadspace, fixed-outline
72	Love Singhal, Elaheh Bozorgzadeh	Novel Multi-Layer floorplanning for Heterogeneous FPGAs.	FPL	2007	DBLP DOI BibTeX RDF
57	Benjamin Carrión Schäfer, Taewhan Kim	Hotspots Elimination and Temperature Flattening in VLSI Circuits.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
57	Tung-Chieh Chen, Yao-Wen Chang	Modern Floorplanning Based on B*-Tree and Fast Simulated Annealing.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
57	Love Singhal, Elaheh Bozorgzadeh	Multi-layer Floorplanning on a Sequence of Reconfigurable Designs.	FPL	2006	DBLP DOI BibTeX RDF
57	Tung-Chieh Chen, Yao-Wen Chang	Modern floorplanning based on fast simulated annealing.	ISPD	2005	DBLP DOI BibTeX RDF	simulated annealing, floorplanning
56	Srinath Sridharan, Michael DeBole, Guangyu Sun 0003, Yuan Xie 0001, Vijaykrishnan Narayanan	A criticality-driven microarchitectural three dimensional (3D) floorplanner.	ASP-DAC	2009	DBLP DOI BibTeX RDF
56	Aseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Kamal S. Khouri, Magdy S. Abadir	LEAF: A System Level Leakage-Aware Floorplanner for SoCs.	ASP-DAC	2007	DBLP DOI BibTeX RDF	LEAF, leakage-aware floorplanning, temperature-aware leakage power, dynamic power profile, system on chip, SoC designs
56	Chien-Chang Chen, Wai-Kei Mak	A multi-technology-process reticle floorplanner and wafer dicing planner for multi-project wafers.	ASP-DAC	2006	DBLP DOI BibTeX RDF
43	Hailin Jiang, Malgorzata Marek-Sadowska	Power-Gating Aware Floorplanning.	ISQED	2007	DBLP DOI BibTeX RDF
43	Jason Cong, Michail Romesis, Joseph R. Shinnerl	Fast floorplanning by look-ahead enabled recursive bipartitioning.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
43	Chuan Lin 0002, Hai Zhou 0001, Chris C. N. Chu	A revisit to floorplan optimization by Lagrangian relaxation.	ICCAD	2006	DBLP DOI BibTeX RDF	floorplan, Lagrangian relaxation
43	Wei-Lun Hung, Greg M. Link, Yuan Xie 0001, Narayanan Vijaykrishnan, Mary Jane Irwin	Interconnect and Thermal-aware Floorplanning for 3D Microprocessors.	ISQED	2006	DBLP DOI BibTeX RDF
43	Mongkol Ekpanyapong, Jacob R. Minz, Thaisiri Watewai, Hsien-Hsin S. Lee, Sung Kyu Lim	Profile-guided microarchitectural floorplanning for deep submicron processor design.	DAC	2004	DBLP DOI BibTeX RDF	microarchitectural planning, computer architecture, floorplanning
42	Chiu-Wing Sham, Evangeline F. Y. Young	Routability-driven floorplanner with buffer block planning.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
42	Chiu-Wing Sham, Evangeline F. Y. Young	Routability driven floorplanner with buffer block planning.	ISPD	2002	DBLP DOI BibTeX RDF
42	Jim E. Crenshaw, Majid Sarrafzadeh, Prithviraj Banerjee, Pradeep Prabhakaran	An Incremental Floorplanner.	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF
29	Fan Mo, Robert K. Brayton	A simultaneous bus orientation and bused pin flipping algorithm.	ICCAD	2007	DBLP DOI BibTeX RDF
29	Milenko Drinic, Darko Kirovski, Seapahn Megerian, Miodrag Potkonjak	Latency-Guided On-Chip Bus-Network Design.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
29	Chih-Hung Lee, Chin-Hung Su, Shih-Hsu Huang, Chih-Yuan Lin, Tsai-Ming Hsieh	Floorplanning with clock tree estimation.	ISCAS (6)	2005	DBLP DOI BibTeX RDF
29	Zion Cien Shen, Chris C. N. Chu	Accurate and efficient flow based congestion estimation in floorplanning.	ASP-DAC	2004	DBLP DOI BibTeX RDF
29	Steve T. W. Lai, Evangeline F. Y. Young, Chris C. N. Chu	A New and Efficient Congestion Evaluation Model in Floorplanning: Wire Density Control with Twin Binary Trees.	DATE	2003	DBLP DOI BibTeX RDF
29	Faran Rafiq, Malgorzata Chrzanowska-Jeske, Hannah Honghua Yang, Naveed A. Sherwani	Integrated floorplanning with buffer/channel insertion for bus-based microprocessor designs.	ISPD	2002	DBLP DOI BibTeX RDF	floorplanning, routability, interconnect estimation
29	Evangeline F. Y. Young, Martin D. F. Wong, Hannah Honghua Yang	Slicing floorplans with range constraint.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
28	David Cuesta, José L. Risco-Martín, José L. Ayala, José Ignacio Hidalgo	Thermal-Aware Floorplanner for 3D IC, including TSVs, Liquid Microchannels and Thermal Domains Optimization.	CoRR	2024	DBLP DOI BibTeX RDF
28	Dima Al Saleh, Yousef Safari, Fahad Rahman Amik, Boris Vaisband	P* Admissible Thermal-Aware Matrix Floorplanner for 3D ICs.	SOCC	2023	DBLP DOI BibTeX RDF
28	Mohammad Amini, Zhanguang Zhang, Surya Penmetsa, Yingxue Zhang 0001, Jianye Hao, Wulong Liu	Generalizable Floorplanner through Corner Block List Representation and Hypergraph Embedding.	KDD	2022	DBLP DOI BibTeX RDF
28	Pengli Ji, Kun He 0001, Zhengli Wang, Yan Jin 0005, Jigang Wu	A Quasi-Newton-based Floorplanner for fixed-outline floorplanning.	Comput. Oper. Res.	2021	DBLP DOI BibTeX RDF
28	Bo Hu, Mustafa M. Shihab, Yiorgos Makris, Benjamin Carrión Schäfer, Carl Sechen	An Efficient MILP-Based Aging-Aware Floorplanner for Multi-Context Coarse-Grained Runtime Reconfigurable FPGAs.	DATE	2020	DBLP DOI BibTeX RDF
28	Somnath Roy Choudhury, Sambhu Nath Pradhan	DOTFloor-A Diffusion Oriented Time-Improved Floorplanner for Macrocells.	IEEE Access	2019	DBLP DOI BibTeX RDF
28	Abdullah Guler, Niraj K. Jha	Hybrid Monolithic 3-D IC Floorplanner.	IEEE Trans. Very Large Scale Integr. Syst.	2018	DBLP DOI BibTeX RDF
28	Tuan D. A. Nguyen, Akash Kumar 0001	PRFloor: An Automatic Floorplanner for Partially Reconfigurable FPGA Systems.	FPGA	2016	DBLP DOI BibTeX RDF
28	Sri Harsha Gade, Praveen Kumar, Sujay Deb	A Pre-RTL floorplanner tool for automated CMP design space exploration with thermal awareness.	VDAT	2016	DBLP DOI BibTeX RDF
28	David Cuesta, José L. Risco-Martín, José L. Ayala, José Ignacio Hidalgo	Thermal-aware floorplanner for 3D IC, including TSVs, liquid microchannels and thermal domains optimization.	Appl. Soft Comput.	2015	DBLP DOI BibTeX RDF
28	Wei Guo, Minxuan Zhang, Peng Li, Chaoyun Yao	Floorplanner for multi-core micro-processors in 3D ICs with interlayer cooling system.	IEICE Electron. Express	2015	DBLP DOI BibTeX RDF
28	Wei Guo, Minxuan Zhang, Peng Li, Chaoyun Yao, Hongwei Zhou	Thermal-Aware Floorplanner for Multi-core 3D ICs with Interlayer Cooling.	NCCET	2015	DBLP DOI BibTeX RDF
28	David Cuesta, José Luis Risco-Martín, José L. Ayala, José Ignacio Hidalgo	3D thermal-aware floorplanner using a MOEA approximation.	Integr.	2013	DBLP DOI BibTeX RDF
28	Ignacio Arnaldo, José Luis Risco-Martín, José Luis Ayala, José Ignacio Hidalgo	Power profiling-guided floorplanner for 3D multi-processor systems-on-chip.	IET Circuits Devices Syst.	2012	DBLP DOI BibTeX RDF
28	David Cuesta, José Luis Risco-Martín, José L. Ayala	3D thermal-aware floorplanner using a MILP approximation.	Microprocess. Microsystems	2012	DBLP DOI BibTeX RDF
28	Ignacio Arnaldo, José L. Risco-Martín, José L. Ayala, José Ignacio Hidalgo	Power Profiling-Guided Floorplanner for Thermal Optimization in 3D Multiprocessor Architectures.	PATMOS	2011	DBLP DOI BibTeX RDF
28	David Cuesta, José L. Risco-Martín, José L. Ayala, David Atienza	3D Thermal-aware floorplanner for many-core single-chip systems.	LATW	2011	DBLP DOI BibTeX RDF
28	Jackey Z. Yan, Chris Chu	DeFer: deferred decision making enabled fixed-outline floorplanner.	DAC	2008	DBLP DOI BibTeX RDF	deferred decision making, floorplanning, fixed outline
28	Hsun-Cheng Lee, Yao-Wen Chang, Hannah Honghua Yang	MBast-Tree: A Multilevel Floorplanner for Large-Scale Building-Module Design.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
28	Love Singhal, Elaheh Bozorgzadeh	Heterogeneous Floorplanner for FPGA.	FCCM	2007	DBLP DOI BibTeX RDF
28	Kia Bazargan, Samjung Kim, Majid Sarrafzadeh	Nostradamus: a floorplanner of uncertain designs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
28	Kia Bazargan, Samjung Kim, Majid Sarrafzadeh	Nostradamus: a floorplanner of uncertain design.	ISPD	1998	DBLP DOI BibTeX RDF
28	Henrik Esbensen, Ernest S. Kuh	EXPLORER: an interactive floorplanner for design space exploration.	EURO-DAC	1996	DBLP DOI BibTeX RDF
28	Sadiq M. Sait, Habib Youssef, Shahid K. Tanvir, Muhammad S. T. Benten	Timing influenced generell-cell genetic floorplanner.	ASP-DAC	1995	DBLP DOI BibTeX RDF
28	Abdelhakim Safir, Baher Haroun, Krishnaiyan Thulasiraman	A Floorplanner driven by Structural & Timing Constraints.	ISCAS	1994	DBLP DOI BibTeX RDF
28	Suhail Ahmed, T. V. Nagesh, Ramoji Rao, B. Naveen, P. K. Fangaria, K. S. Raghunathan	FLOR: A Hierarchical Floorplanner Under Vinyas VCX System - System Overview.	VLSI Design	1993	DBLP DOI BibTeX RDF
28	R. Shanker	DEFLAN- A delay estimator for floorplanner.	VLSI Design	1992	DBLP DOI BibTeX RDF
28	Noritake Yonezawa, Nobuyuki Nishiguchi, Atsushi Etani, Fumiaki Tsukuda, Ryuichi Hashishita	A VLSI floorplanner based on "balloon" expansion.	EURO-DAC	1990	DBLP DOI BibTeX RDF
28	Masako Murofushi, Masaaki Yamada, Takashi Mitsuhashi	FOLM-Planner: A New Floorplanner with a Frame Overlapping Floorplan Model Suitable for SOG (Sea-of-Gates) Type Gate Arrays.	ICCAD	1990	DBLP DOI BibTeX RDF
14	David Cuesta, José Luis Ayala, José Ignacio Hidalgo, Massimo Poncino, Andrea Acquaviva, Enrico Macii	Thermal-aware floorplanning exploration for 3D multi-core architectures.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	3D, floorplanning, MPSoC, temperature
14	Bo-Shiun Wu, Tsung-Yi Ho	Bus-pin-aware bus-driven floorplanning.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	bus planning, floorplanning
14	Dipanjan Sengupta, Resve A. Saleh	Application-Driven Voltage-Island Partitioning for Low-Power System-on-Chip Design.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2009	DBLP DOI BibTeX RDF
14	Michael B. Healy, Hsien-Hsin S. Lee, Gabriel H. Loh, Sung Kyu Lim	Thermal optimization in multi-granularity multi-core floorplanning.	ASP-DAC	2009	DBLP DOI BibTeX RDF
14	Jia Wang 0003, Hai Zhou 0001	Exploring adjacency in floorplanning.	ASP-DAC	2009	DBLP DOI BibTeX RDF
14	Gregory Lucas, Scott Cromar, Deming Chen	FastYield: variation-aware, layout-driven simultaneous binding and module selection for performance yield optimization.	ASP-DAC	2009	DBLP DOI BibTeX RDF
14	Zaichen Qian, Evangeline F. Y. Young	Multi-voltage floorplan design with optimal voltage assignment.	ISPD	2009	DBLP DOI BibTeX RDF	multi-voltage assignment optimization branch-and-bound
14	Tung-Chieh Chen, Yao-Wen Chang, Shyh-Chang Lin	A New Multilevel Framework for Large-Scale Interconnect-Driven Floorplanning.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
14	Jeremy Chan, Sri Parameswaran	NoCOUT : NoC topology generation with mixed packet-switched and point-to-point networks.	ASP-DAC	2008	DBLP DOI BibTeX RDF
14	Love Singhal, Sejong Oh, Eli Bozorgzadeh	Statistical power profile correlation for realistic thermal estimation.	ASP-DAC	2008	DBLP DOI BibTeX RDF
14	Tilen Ma, Evangeline F. Y. Young	TCG-based multi-bend bus driven floorplanning.	ASP-DAC	2008	DBLP DOI BibTeX RDF
14	Qiang Ma 0002, Evangeline F. Y. Young	Network flow-based power optimization under timing constraints in MSV-driven floorplanning.	ICCAD	2008	DBLP DOI BibTeX RDF
14	Amir Hossein Gholamipour, Elaheh Bozorgzadeh, Lichun Bao	Seamless sequence of software defined radio designs through hardware reconfigurability of FPGAs.	ICCD	2008	DBLP DOI BibTeX RDF
14	Pradeep Fernando, Srinivas Katkoori	An Elitist Non-Dominated Sorting Based Genetic Algorithm for Simultaneous Area and Wirelength Minimization in VLSI Floorplanning.	VLSI Design	2008	DBLP DOI BibTeX RDF
14	Dipanjan Sengupta, Resve A. Saleh	Application-driven floorplan-aware voltage island design.	DAC	2008	DBLP DOI BibTeX RDF	dynamic programming, energy, floorplan, voltage island
14	Michael B. Healy, Mario Vittes, Mongkol Ekpanyapong, Chinnakrishnan S. Ballapuram, Sung Kyu Lim, Hsien-Hsin S. Lee, Gabriel H. Loh	Multiobjective Microarchitectural Floorplanning for 2-D and 3-D ICs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
14	Andrew B. Kahng, Ion I. Mandoiu, Xu Xu 0001, Alexander Zelikovsky	Enhanced Design Flow and Optimizations for Multiproject Wafers.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
14	Vyas Krishnan, Srinivas Katkoori	Minimizing wire delays by net-topology aware binding during floorplan- driven high level synthesis.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
14	Song Chen 0001, Takeshi Yoshimura	A stable fixed-outline floorplanning method.	ISPD	2007	DBLP DOI BibTeX RDF	floorplanning, sequence pair, fixed-outline
14	Pingqiang Zhou, Yuchun Ma, Zhuoyuan Li, Robert P. Dick, Li Shang, Hai Zhou 0001, Xianlong Hong, Qiang Zhou 0001	3D-STAF: scalable temperature and leakage aware floorplanning for three-dimensional integrated circuits.	ICCAD	2007	DBLP DOI BibTeX RDF
14	Qiang Ma 0002, Evangeline F. Y. Young	Voltage island-driven floorplanning.	ICCAD	2007	DBLP DOI BibTeX RDF
14	Yici Cai, Bin Liu 0007, Jin Shi, Qiang Zhou 0001, Xianlong Hong	Power Delivery Aware Floorplanning for Voltage Island Designs.	ISQED	2007	DBLP DOI BibTeX RDF
14	Yan Feng, Dinesh P. Mehta	Module relocation to obtain feasible constrained floorplans.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
14	Mario R. Casu, Luca Macchiarulo	Floorplanning With Wire Pipelining in Adaptive Communication Channels.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
14	Michael B. Healy, Mario Vittes, Mongkol Ekpanyapong, Chinnakrishnan S. Ballapuram, Sung Kyu Lim, Hsien-Hsin S. Lee, Gabriel H. Loh	Microarchitectural floorplanning under performance and thermal tradeoff.	DATE	2006	DBLP DOI BibTeX RDF
14	Ryan Kastner, Wenrui Gong, Xin Hao, Forrest Brewer, Adam Kaplan, Philip Brisk, Majid Sarrafzadeh	Layout driven data communication optimization for high level synthesis.	DATE	2006	DBLP DOI BibTeX RDF
14	Chih-Yang Peng, Wen-Chang Chao, Yao-Wen Chang, Jyh-Herng Wang	Simultaneous block and I/O buffer floorplanning for flip-chip design.	ASP-DAC	2006	DBLP DOI BibTeX RDF
14	Krishnan Srinivasan, Karam S. Chatha	Layout aware design of mesh based NoC architectures.	CODES+ISSS	2006	DBLP DOI BibTeX RDF	network-on-chip, automated design, mesh topology
14	Wan-Ping Lee, Hung-Yi Liu, Yao-Wen Chang	Voltage island aware floorplanning for power and timing optimization.	ICCAD	2006	DBLP DOI BibTeX RDF
14	Vidyasagar Nookala, David J. Lilja, Sachin S. Sapatnekar	Temperature-aware floorplanning of microarchitecture blocks with IPC-power dependence modeling and transient analysis.	ISLPED	2006	DBLP DOI BibTeX RDF	floorplanning, microarchitecture, transient analysis
14	Tan Yan, Qing Dong, Yasuhiro Takashima, Yoji Kajitani	How does partitioning matter for 3D floorplanning?	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	partitioning, floorplanning, 3D IC, wire length
14	Jia Wang 0003, Hai Zhou 0001, Ping-Chih Wu	Processing Rate Optimization by Sequential System Floorplanning.	ISQED	2006	DBLP DOI BibTeX RDF
14	Hung-Ming Chen, Li-Da Huang, I-Min Liu, Martin D. F. Wong	Simultaneous power supply planning and noise avoidance in floorplan design.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
14	Saurabh N. Adya, Igor L. Markov	Combinatorial techniques for mixed-size placement.	ACM Trans. Design Autom. Electr. Syst.	2005	DBLP DOI BibTeX RDF	VLSI, placement, floorplanning
14	Lei Cheng 0001, Liang Deng, Martin D. F. Wong	Floorplanning for 3-D VLSI design.	ASP-DAC	2005	DBLP DOI BibTeX RDF
14	Grzegorz Blakiewicz, Marcin Jeske, Malgorzata Chrzanowska-Jeske, Jin S. Zhang	Substrate noise modeling in early floorplanning of MS-SOCs.	ASP-DAC	2005	DBLP DOI BibTeX RDF
14	Mario R. Casu, Luca Macchiarulo	Floorplan assisted data rate enhancement through wire pipelining: a real assessment.	ISPD	2005	DBLP DOI BibTeX RDF	through-put, systems-on-chip, floorplanning, wire pipelining
14	Natarajan Viswanathan, Min Pan, Chris C. N. Chu	FastPlace: an analytical placer for mixed-mode designs.	ISPD	2005	DBLP DOI BibTeX RDF	mixed-mode placement, floorplanning, analytical placement
14	Tony F. Chan, Jason Cong, Michail Romesis, Joseph R. Shinnerl, Kenton Sze, Min Xie 0004	mPL6: a robust multilevel mixed-size placement engine.	ISPD	2005	DBLP DOI BibTeX RDF	mixed-size placement, legalization, helmholtz equation, force-directed placement, multilevel optimization
14	Yongpan Liu, Huazhong Yang, Rong Luo, Hui Wang 0004	A Hierarchical Approach for Incremental Floorplan Based on Genetic Algorithms.	ICNC (3)	2005	DBLP DOI BibTeX RDF
14	Song Chen 0001, Xianlong Hong, Sheqin Dong, Yuchun Ma, Chung-Kuan Cheng	Floorplanning with Consideration of White Space Resource Distribution for Repeater Planning.	ISQED	2005	DBLP DOI BibTeX RDF
14	S. A. Moghaddam, Nasser Masoumi, Caro Lucas	A Stochastic Power-Supply Noise Reduction Technique Using Max-Flow Algorithm and Decoupling Capacitance.	IWSOC	2005	DBLP DOI BibTeX RDF
14	Yi-Lin Hsieh, Tsai-Ming Hsieh	A New Effective Congestion Model in Floorplan Design.	DATE	2004	DBLP DOI BibTeX RDF
14	Hayward H. Chan, Igor L. Markov	Practical slicing and non-slicing block-packing without simulated annealing.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	block-packing, optimal, evaluation, branch-and-bound, floorplanning, slicing, hierarchical, large-scale, soft blocks
14	Saurabh N. Adya, Igor L. Markov	Fixed-outline floorplanning: enabling hierarchical design.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
14	Faran Rafiq, Malgorzata Chrzanowska-Jeske, Hannah Honghua Yang, Marcin Jeske, Naveed A. Sherwani	Integrated floorplanning with buffer/channel insertion for bus-based designs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF