Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
99 | Yee Jern Chong, Sri Parameswaran |
Flexible multi-mode embedded floating-point unit for field programmable gate arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, FPGA 2009, Monterey, California, USA, February 22-24, 2009, pp. 171-180, 2009, ACM, 978-1-60558-410-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
dual-precision, embedded block, fpu, fpga, floating-point, fpga architecture |
85 | Yongsoon Lee, Seok-Bum Ko |
FPGA Implementation of a Face Detector using Neural Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCECE ![In: Proceedings of the Canadian Conference on Electrical and Computer Engineering, CCECE 2006, May 7-10, 2006, Ottawa Congress Centre, Ottawa, Canada, pp. 1914-1917, 2006, IEEE, 1-4244-0038-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
77 | In-hye Seo, Heau-Jo Kang, Tai-Hoon Kim |
Performance Analysis of Adaptive Digital FPU Transmission System in Fading Environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICIC (1) ![In: Intelligent Computing, International Conference on Intelligent Computing, ICIC 2006, Kunming, China, August 16-19, 2006. Proceedings, Part I, pp. 1062-1071, 2006, Springer, 3-540-37271-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
68 | Kingshuk Karuri, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Monu Kedia |
Design and implementation of a modular and portable IEEE 754 compliant floating-point unit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE Designers' Forum ![In: Proceedings of the Conference on Design, Automation and Test in Europe: Designers' Forum, DATE 2006, Munich, Germany, March 6-10, 2006, pp. 221-226, 2006, European Design and Automation Association, Leuven, Belgium, 3-9810801-0-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
68 | Ajay Naini, Atul Dhablania, Warren James, Debjit Das Sarma |
1-GHz HAL SPARC64 Dual Floating Point Unit with RAS Features. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 15th IEEE Symposium on Computer Arithmetic (Arith-15 2001), 11-17 June 2001, Vail, CO, USA, pp. 173-183, 2001, IEEE Computer Society, 0-7695-1150-3. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
52 | Dmitry E. Pelinovsky, Guido Schneider |
The monoatomic FPU system as a limit of a diatomic FPU system. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Appl. Math. Lett. ![In: Appl. Math. Lett. 107, pp. 106387, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
52 | Jing Pu, Sameh Galal, Xuan Yang, Ofer Shacham, Mark Horowitz |
FPMax: a 106GFLOPS/W at 217GFLOPS/mm2 Single-Precision FPU, and a 43.7GFLOPS/W at 74.6GFLOPS/mm2 Double-Precision FPU, in 28nm UTBB FDSOI. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1606.07852, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP BibTeX RDF |
|
51 | Yee Jern Chong, Sri Parameswaran |
Automatic application specific floating-point unit generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2007 Design, Automation and Test in Europe Conference and Exposition, DATE 2007, Nice, France, April 16-20, 2007, pp. 461-466, 2007, EDA Consortium, San Jose, CA, USA, 978-3-9810801-2-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
51 | Silvia M. Müller, Christian Jacobi 0002, Hwa-Joon Oh, Kevin D. Tran, Scott R. Cottier, Brad W. Michael, Hiroo Nishikawa, Yonetaro Totsuka, Tatsuya Namatame, Naoka Yano, Takashi Machida, Sang H. Dhong |
The Vector Floating-Point Unit in a Synergistic Processor Element of a CELL Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 17th IEEE Symposium on Computer Arithmetic (ARITH-17 2005), 27-29 June 2005, Cape Cod, MA, USA, pp. 59-67, 2005, IEEE Computer Society, 0-7695-2366-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
51 | Leonardo R. Bachega, Siddhartha Chatterjee, Kenneth A. Dockser, John A. Gunnels, Manish Gupta 0002, Fred G. Gustavson, Christopher A. Lapkowski, Gary K. Liu, Mark P. Mendell, Charles D. Wait, T. J. Christopher Ward |
A High-Performance SIMD Floating Point Unit for BlueGene/L: Architecture, Compilation, and Algorithm Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE PACT ![In: 13th International Conference on Parallel Architectures and Compilation Techniques (PACT 2004), 29 September - 3 October 2004, Antibes Juan-les-Pins, France, pp. 85-96, 2004, IEEE Computer Society, 0-7695-2229-7. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
51 | Zhenyu Tang, Lei He 0001, Norman Chang, Shen Lin, Weize Xie, O. Sam Nakagawa |
Instruction Prediction for Step Power Reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 26-28 March 2001, San Jose, CA, USA, pp. 211-216, 2001, IEEE Computer Society, 0-7695-1025-6. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
51 | Zhenyu Tang, Norman Chang, Shen Lin, Weize Xie, O. Sam Nakagawa, Lei He 0001 |
Ramp Up/Down Functional Unit to Reduce Step Power. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PACS ![In: Power-Aware Computer Systems, First International Workshop, PACS 2000, Cambridge, MA, USA, November 12, 2000, Revised Papers, pp. 13-24, 2000, Springer, 3-540-42329-X. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
34 | Seyed Mohammad Hossein Shekarian, Alireza Ejlali, Seyed Ghassem Miremadi |
A Low Power Error Detection Technique for Floating-Point Units in Embedded Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUC (1) ![In: 2008 IEEE/IPIP International Conference on Embedded and Ubiquitous Computing (EUC 2008), Shanghai, China, December 17-20, 2008, Volume I, pp. 199-205, 2008, IEEE Computer Society, 978-0-7695-3492-3. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
34 | Yee Jern Chong, Sri Parameswaran |
Rapid application specific floating-point unit generation with bit-alignment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008, pp. 62-67, 2008, ACM, 978-1-60558-115-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
bit-alignment, datapath merging, floating-point |
34 | Thomas Y. Yeh, Petros Faloutsos, Milos D. Ercegovac, Sanjay J. Patel, Glenn Reinman |
The Art of Deception: Adaptive Precision Reduction for Area Efficient Physics Acceleration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-40 2007), 1-5 December 2007, Chicago, Illinois, USA, pp. 394-406, 2007, IEEE Computer Society, 0-7695-3047-8. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
34 | J. Gonzalez-Gomez, Iván González, Francisco J. Gomez-Arribas, Eduardo I. Boemo |
Evaluation of a Locomotion Algorithm for Worm-Like Robots on FPGA-Embedded Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARC ![In: Reconfigurable Computing: Architectures and Applications, Second International Workshop, ARC 2006, Delft, The Netherlands, March 1-3, 2006, Revised Selected Papers, pp. 24-29, 2006, Springer. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
34 | Neil Burgess |
Prenormalization rounding in IEEE floating-point operations using a flagged prefix adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 13(2), pp. 266-277, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
34 | Christian Jacobi 0002, Christoph Berg |
Formal Verification of the VAMP Floating Point Unit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Formal Methods Syst. Des. ![In: Formal Methods Syst. Des. 26(3), pp. 227-266, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
IEEE standard 754, formal verification, theorem proving, PVS, floating point unit |
34 | Christian Jacobi 0002, Kai Weber 0001, Viresh Paruthi, Jason Baumgartner |
Automatic Formal Verification of Fused-Multiply-Add FPUs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2005 Design, Automation and Test in Europe Conference and Exposition (DATE 2005), 7-11 March 2005, Munich, Germany, pp. 1298-1303, 2005, IEEE Computer Society, 0-7695-2288-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
34 | Marc Epalza, Paolo Ienne, Daniel Mlynek |
Adding Limited Reconfigurability to Superscalar Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE PACT ![In: 13th International Conference on Parallel Architectures and Compilation Techniques (PACT 2004), 29 September - 3 October 2004, Antibes Juan-les-Pins, France, pp. 53-62, 2004, IEEE Computer Society, 0-7695-2229-7. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
34 | Jens Peter Wittenburg, Ulrich Schreiber, Ulrich Gries, Markus Schneider 0003, Tim Niggemeier |
A Cost-Efficient RISC Processor Platform for Real Time Audio Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAMOS ![In: Computer Systems: Architectures, Modeling, and Simulation, Third and Fourth International Workshops, SAMOS 2003 and SAMOS 2004, Samos, Greece, July 21-23, 2003 and July 19-21, 2004, Proceedings, pp. 39-48, 2004, Springer, 3-540-22377-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
34 | Eric M. Schwarz, Ronald M. Smith, Christopher A. Krygowski |
The S/390 G5 Floating Point Unit Supporting Hex and Binary Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 14th IEEE Symposium on Computer Arithmetic (Arith-14 '99), 14-16 April 1999, Adelaide, Australia, pp. 258-265, 1999, IEEE Computer Society, 0-7695-0116-8. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
32 | David Monniaux |
The pitfalls of verifying floating-point computations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Program. Lang. Syst. ![In: ACM Trans. Program. Lang. Syst. 30(3), pp. 12:1-12:41, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
AMD64, FPU, IA32, x87, Verification, Static analysis, Abstract interpretation, Program testing, Embedded software, Floating point, Safety-Critical Software, Rounding, PowerPC, IEEE-754 |
32 | Michael J. Beauchamp, Scott Hauck, Keith D. Underwood, K. Scott Hemmert |
Embedded floating-point units in FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, FPGA 2006, Monterey, California, USA, February 22-24, 2006, pp. 12-20, 2006, ACM, 1-59593-292-5. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
FPU, FPGA, floating-point, FPGA architecture |
26 | Lyle Parsons, Guang Deng, Robert Ross |
Detecting image edges in IOT nodes without FPU. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Multim. Tools Appl. ![In: Multim. Tools Appl. 83(10), pp. 31161-31175, March 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
26 | Bastian Hilder, Björn de Rijk, Guido Schneider |
Moving Modulating Pulse and Front Solutions of Permanent Form in a FPU Model with Nearest and Next-to-Nearest Neighbor Interaction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIAM J. Appl. Dyn. Syst. ![In: SIAM J. Appl. Dyn. Syst. 22(2), pp. 1076-1113, June 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
26 | Chris Keilbart, Yuhui Gao, Martin Chua, Eric Matthews, Steven J. E. Wilton, Lesley Shannon |
Designing a configurable IEEE-compliant FPU that supports variable precision for soft processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 31st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2023, Marina Del Rey, CA, USA, May 8-11, 2023, pp. 202, 2023, IEEE, 979-8-3503-1205-8. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
26 | Jina Park, Kyuseung Han, Eunjin Choi, Sukho Lee, Jae-Jin Lee, Woojoo Lee, Massoud Pedram |
Florian: Developing a Low-Power RISC-V Multicore Processor with a Shared Lightweight FPU. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2023, Vienna, Austria, August 7-8, 2023, pp. 1-6, 2023, IEEE, 979-8-3503-1175-4. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
26 | Sridutt Bhalachandra, Brian Austin, Samuel Williams 0001, Nicholas J. Wright |
Understanding the Impact of Input Entropy on FPU, CPU, and GPU Power. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2212.08805, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
26 | Henry Duran, Jesús Cuevas-Maraver, Panayotis G. Kevrekidis, Anna Vainchtein |
Moving discrete breathers in a β-FPU lattice revisited. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Commun. Nonlinear Sci. Numer. Simul. ![In: Commun. Nonlinear Sci. Numer. Simul. 111, pp. 106435, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
26 | Won Jeon, Yong Cheol Peter Cho, Hyun-Mi Kim, Hyeji Kim, Jaehoon Chung, Ju-Yeob Kim, Miyoung Lee, Chun-Gi Lyuh, Jinho Han, Youngsu Kwon |
M3FPU: Multiformat Matrix Multiplication FPU Architectures for Neural Network Computations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AICAS ![In: 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, AICAS 2022, Incheon, Republic of Korea, June 13-15, 2022, pp. 150-153, 2022, IEEE, 978-1-6654-0996-4. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
26 | Davide Zoni, Andrea Galimberti, William Fornaciari |
An FPU design template to optimize the accuracy-efficiency-area trade-off. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Sustain. Comput. Informatics Syst. ![In: Sustain. Comput. Informatics Syst. 29(Part), pp. 100450, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
26 | Peng Chen |
Periodic motion for FPU lattice dynamical systems with the strongly indefinite case. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Appl. Math. Lett. ![In: Appl. Math. Lett. 113, pp. 106837, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
26 | Chiara Caracciolo, Ugo Locatelli |
Elliptic tori in FPU non-linear chains with a small number of nodes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Commun. Nonlinear Sci. Numer. Simul. ![In: Commun. Nonlinear Sci. Numer. Simul. 97, pp. 105759, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
26 | Noureddine Ait Said, Mounir Benabdenbi, Katell Morin-Allory |
FPU Reduced Variable Precision in Time: Application to the Jacobi Iterative Method. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2021, Tampa, FL, USA, July 7-9, 2021, pp. 170-175, 2021, IEEE, 978-1-6654-3946-6. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
26 | Luca Bertaccini, Matteo Perotti, Stefan Mach, Pasquale Davide Schiavone, Florian Zaruba, Luca Benini |
Tiny-FPU: Low-Cost Floating-Point Support for Small RISC-V MCU Cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2021, Daegu, South Korea, May 22-28, 2021, pp. 1-5, 2021, IEEE, 978-1-7281-9201-7. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
26 | Luca Cremona, William Fornaciari, Andrea Galimberti, Andrea Romanoni, Davide Zoni |
VGM-Bench: FPU Benchmark Suite for Computer Vision, Computer Graphics and Machine Learning Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAMOS ![In: Embedded Computer Systems: Architectures, Modeling, and Simulation - 20th International Conference, SAMOS 2020, Samos, Greece, July 5-9, 2020, Proceedings, pp. 323-335, 2020, Springer, 978-3-030-60938-2. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
26 | Noureddine Ait Said, Mounir Benabdenbi, Katell Morin-Allory |
FPU Bit-Width Optimization for Approximate Computing: A Non-Intrusive Approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DTIS ![In: 15th Design & Technology of Integrated Systems in Nanoscale Era, DTIS 2020, Marrakech, Morocco, April 1-3, 2020, pp. 1-6, 2020, IEEE, 978-1-7281-5426-8. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
26 | Athanassios Tziouvaras, Georgios Dimitriou, Michael F. Dossis, Georgios I. Stamoulis |
Adaptive Operation-Based ALU and FPU Clocking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MOCAST ![In: 9th International Conference on Modern Circuits and Systems Technologies, MOCAST 2020, Bremen, Germany, September 7-9, 2020, pp. 1-4, 2020, IEEE, 978-1-7281-6687-2. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
26 | Roelof Bruggeman, Ferdinand Verhulst |
Near-Integrability and Recurrence in FPU Chains with Alternating Masses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Nonlinear Sci. ![In: J. Nonlinear Sci. 29(1), pp. 183-206, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
26 | Xiang Yi, Shixiao Liu |
Mobility of Discrete Breather in a FPU-KG Chain. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CIS ![In: 15th International Conference on Computational Intelligence and Security, CIS 2019, Macao, SAR, China, December 13-16, 2019, pp. 197-200, 2019, IEEE, 978-1-7281-6092-4. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
26 | Aneesh Raveendran, Vinay Kumar, Vivian Desalphine, David Selvakumar |
Functional Simulation Verification of RISC-V Instruction Set Based High Level Language Modeled FPU. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: VLSI Design and Test - 23rd International Symposium, VDAT 2019, Indore, India, July 4-6, 2019, Revised Selected Papers, pp. 496-509, 2019, Springer, 978-981-32-9766-1. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
26 | Julian Stecklina, Thomas Prescher 0002 |
LazyFP: Leaking FPU Register State using Microarchitectural Side-Channels. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1806.07480, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP BibTeX RDF |
|
26 | Michael Herrmann |
High-Energy Waves in Superpolynomial FPU-Type Chains. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Nonlinear Sci. ![In: J. Nonlinear Sci. 27(1), pp. 213-240, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
26 | Ferdinand Verhulst |
Near-Integrability and Recurrence in FPU-Cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Bifurc. Chaos ![In: Int. J. Bifurc. Chaos 26(14), pp. 1650230:1-1650230:23, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
26 | Alexandre Aminot, Yves Lhuillier, Andrea Castagnetti, Henri-Pierre Charles |
FPU Speedup Estimation for Task Placement Optimization on Asymmetric Multicore Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MCSoC ![In: IEEE 9th International Symposium on Embedded Multicore/Many-core Systems-on-Chip, MCSoC 2015, Turin, Italy, September 23-25, 2015, pp. 81-87, 2015, IEEE Computer Society, 978-1-4799-8670-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
26 | Jeremy Gaison, Shari Moskow, J. Douglas Wright, Qimin Zhang |
Approximation of Polyatomic FPU Lattices by KdV Equations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Multiscale Model. Simul. ![In: Multiscale Model. Simul. 12(3), pp. 953-995, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
26 | Aarti Gupta, V. M. Achutha KiranKumar, Rajnish Ghughal |
Formally Verifying Graphics FPU - An Intel® Experience. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FM ![In: FM 2014: Formal Methods - 19th International Symposium, Singapore, May 12-16, 2014. Proceedings, pp. 673-687, 2014, Springer, 978-3-319-06409-3. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
26 | Bogdan Pasca 0001 |
Low-cost multiplier-based FPU for embedded processing on FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 24th International Conference on Field Programmable Logic and Applications, FPL 2014, Munich, Germany, 2-4 September, 2014, pp. 1-4, 2014, IEEE. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
26 | Angelos Ntasios, Minas Dasygenis |
Design, Implementation and Verification of a Customizing IP Soft Core With FPU Support. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Panhellenic Conference on Informatics ![In: 18th Panhellenic Conference on Informatics, PCI '14, Athens, Greece, October 2-4, 2014, pp. 34:1-34:2, 2014, ACM, 978-1-4503-2897-5. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
26 | Michail Maniatakos, Prabhakar Kudva, Bruce M. Fleischer, Yiorgos Makris |
Low-Cost Concurrent Error Detection for Floating-Point Unit (FPU) Controllers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 62(7), pp. 1376-1388, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
26 | Marat Dukhan |
What a fast FPU means for algorithms: A story of vector elementary functions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Hot Chips Symposium ![In: 2013 IEEE Hot Chips 25 Symposium (HCS), Stanford University, CA, USA, August 25-27, 2013, pp. 1, 2013, IEEE, 978-1-4673-8881-8. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
26 | Sameh Galal, Ofer Shacham, John S. Brunhaver, Jing Pu, Artem Vassiliev, Mark Horowitz |
FPU Generator for Design Space Exploration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 21st IEEE Symposium on Computer Arithmetic, ARITH 2013, Austin, TX, USA, April 7-10, 2013, pp. 25-34, 2013, IEEE Computer Society, 978-1-4673-5644-2. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
26 | Abbas Rahimi, Andrea Marongiu, Rajesh K. Gupta 0001, Luca Benini |
A variability-aware OpenMP environment for efficient execution of accuracy-configurable computation on shared-FPU processor clusters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2013, Montreal, QC, Canada, September 29 - October 4, 2013, pp. 35:1-35:10, 2013, IEEE, 978-1-4799-1417-3. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
26 | Mohammad Reza Kakoee, Igor Loi, Luca Benini |
A shared-FPU architecture for ultra-low power MPSoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Conf. Computing Frontiers ![In: Computing Frontiers Conference, CF'13, Ischia, Italy, May 14 - 16, 2013, pp. 3:1-3:8, 2013, ACM, 978-1-4503-2053-5. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
26 | V. M. Achutha KiranKumar, Aarti Gupta, Rajnish Ghughal |
Symbolic Trajectory Evaluation: The primary validation Vehicle for next generation Intel® Processor Graphics FPU. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FMCAD ![In: Formal Methods in Computer-Aided Design, FMCAD 2012, Cambridge, UK, October 22-25, 2012, pp. 149-156, 2012, IEEE, 978-1-4673-4832-4. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP BibTeX RDF |
|
26 | Michael Herrmann |
Action Minimising Fronts in General FPU-type Chains. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Nonlinear Sci. ![In: J. Nonlinear Sci. 21(1), pp. 33-55, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
26 | Jaume Joven, Per Strict, David Castells-Rufas, Akash Bagdia, Giovanni De Micheli, Jordi Carrabina |
HW-SW implementation of a decoupled FPU for ARM-based Cortex-M1 SoCs in FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIES ![In: Industrial Embedded Systems (SIES), 2011 6th IEEE International Symposium on, SIES 2011. Vasteras, Sweden, June 15-17, 2011, pp. 1-8, 2011, IEEE, 978-1-61284-818-1. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
26 | Minh Thien Trieu, Huong Thien Hoang, Phong The Vo, Hung Bao Vo, Yoichi Yuyama |
Saving 78.11% Dhrystone power consumption in FPU by clock gating while still keeping co-operation with CPU. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASICON ![In: 2011 IEEE 9th International Conference on ASIC, ASICON 2011, Xiamen, China, October 25-28, 2011, pp. 39-42, 2011, IEEE, 978-1-61284-192-2. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
26 | Michail Maniatakos, Yiorgos Makris, Prabhakar Kudva, Bruce M. Fleischer |
Exponent monitoring for low-cost concurrent error detection in FPU control logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 29th IEEE VLSI Test Symposium, VTS 2011, May 1-5, 2011, Dana Point, California, USA, pp. 235-240, 2011, IEEE Computer Society, 978-1-61284-657-6. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
26 | Michael Herrmann, Jens D. M. Rademacher |
Heteroclinic Travelling Waves in Convex FPU-Type Chains. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIAM J. Math. Anal. ![In: SIAM J. Math. Anal. 42(4), pp. 1483-1504, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
26 | T. R. Gopalakrishnan Nair, R. Selvarani, Vighnaraju Saraf |
Execution and Result Integration Scheme in FPU Farms for Co-ordinated Performance ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1001.3460, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP BibTeX RDF |
|
26 | Bob Rink |
Fermi Pasta Ulam systems (FPU): mathematical aspects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Scholarpedia ![In: Scholarpedia 4(12), pp. 9217, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
26 | Fumio Arakawa, Takashi Okada, Tomoichi Hayashi, Osamu Nishii, Toshihiro Hattori |
An embedded processor core for consumer appliances with 5.6 GFLOPS and 73M polygons/s FPU. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microprocess. Microsystems ![In: Microprocess. Microsystems 33(4), pp. 254-259, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
26 | Hartmut Schwetlick, Johannes Zimmer |
Solitary Waves for Nonconvex FPU Lattices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Nonlinear Sci. ![In: J. Nonlinear Sci. 17(1), pp. 1-12, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
26 | Yung-Ming Chang, Juan-Ming Yuan, Chin-Chieh Chiang |
FPU Recurrence in the KdV-Type Equations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICICIC (2) ![In: First International Conference on Innovative Computing, Information and Control (ICICIC 2006), 30 August - 1 September 2006, Beijing, China, pp. 523-526, 2006, IEEE Computer Society, 0-7695-2616-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
26 | Charles D. Wait |
IBM PowerPC 440 FPU with complex-arithmetic extensions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IBM J. Res. Dev. ![In: IBM J. Res. Dev. 49(2-3), pp. 249-254, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
26 | Juergen Lorenz, Stefan Kral, Franz Franchetti, Christoph W. Ueberhuber |
Vectorization techniques for the Blue Gene/L double FPU. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IBM J. Res. Dev. ![In: IBM J. Res. Dev. 49(2-3), pp. 437-446, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
26 | Eric M. Schwarz, Martin S. Schmookler, Son Dao Trong |
FPU Implementations with Denormalized Numbers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 54(7), pp. 825-836, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Denormalized numbers, subnormals, floating-point hardware, underflow trap, IEEE 754 Standard |
26 | Claudio Brunelli, Fabio Campi, Juha Kylliäinen, Jari Nurmi |
A reconfigurable FPU as IP component for SoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SoC ![In: Proceedings of the 2004 International Symposium on System-on-Chip, Tampere, Finland, November 16-18, 2004, pp. 103-106, 2004, IEEE, 0-7803-8558-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
26 | Franz Franchetti, Stefan Kral, Juergen Lorenz, Markus Püschel, Christoph W. Ueberhuber |
Automatically Tuned FFTs for BlueGene/L's Double FPU. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VECPAR ![In: High Performance Computing for Computational Science - VECPAR 2004, 6th International Conference, Valencia, Spain, June 28-30, 2004, Revised Selected and Invited Papers, pp. 23-36, 2004, Springer, 3-540-25424-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
26 | Mourad Aberbour, A. Houelle, Habib Mehrez, Nicolas Vaucher, Alain Guyot |
On portable macrocell FPU generators for division and square root operators complying to the full IEEE-754 standard. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 6(1), pp. 114-121, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
17 | Florent de Dinechin, Jérémie Detrey, Octavian Cret, Radu Tudoran |
When FPGAs are better at floating-point than microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 16th International Symposium on Field Programmable Gate Arrays, FPGA 2008, Monterey, California, USA, February 24-26, 2008, pp. 260, 2008, ACM, 978-1-59593-934-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
FPGA, floating-point, arithmetic |
17 | Andrew G. Schmidt, William V. Kritikos, Siddhartha Datta, Ron Sass |
Reconfigurable Computing Cluster Project: Phase I Brief. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 16th IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2008, 14-15 April 2008, Stanford, Palo Alto, California, USA, pp. 300-301, 2008, IEEE Computer Society, 978-0-7695-3307-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
17 | Karthik Ganesan 0006, Lizy Kurian John, Valentina Salapura, James C. Sexton |
A Performance Counter Based Workload Characterization on Blue Gene/P. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPP ![In: 2008 International Conference on Parallel Processing, ICPP 2008, September 8-12, 2008, Portland, Oregon, USA, pp. 330-337, 2008, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
17 | Xuehai Qian, He Huang, Zhenzhong Duan, Junchao Zhang, Nan Yuan, Yongbin Zhou, Hao Zhang 0009, Huimin Cui, Dongrui Fan |
Optimized Register Renaming Scheme for Stack-Based x86 Operations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARCS ![In: Architecture of Computing Systems - ARCS 2007, 20th International Conference, Zurich, Switzerland, March 12-15, 2007, Proceedings, pp. 43-56, 2007, Springer, 978-3-540-71267-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
17 | Libo Huang, Li Shen 0007, Kui Dai, Zhiying Wang 0003 |
A New Architecture For Multiple-Precision Floating-Point Multiply-Add Fused Unit Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 18th IEEE Symposium on Computer Arithmetic (ARITH-18 2007), 25-27 June 2007, Montpellier, France, pp. 69-76, 2007, IEEE Computer Society, 0-7695-2854-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
17 | Libo Huang, Ming-che Lai, Kui Dai, Hong Yue, Li Shen 0007 |
Hardware Support for Arithmetic Units of Processor with Multimedia Extension. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MUE ![In: 2007 International Conference on Multimedia and Ubiquitous Engineering (MUE 2007), 26-28 April 2007, Seoul, Korea, pp. 633-637, 2007, IEEE Computer Society, 978-0-7695-2777-2. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
17 | Viay Holimath, Javier D. Bruguera |
A Linear Convergent Functional Iterative DivisionWithout a Look-Up Table. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August - 1 September 2006, Dubrovnik, Croatia, pp. 236-239, 2006, IEEE Computer Society, 0-7695-2609-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
17 | Dong-Sun Kim 0002, Hyunsik Kim, Duck-Jin Chung |
Implementation of a Neural Network Processor Based on RISC Architecture for Various Signal Processing Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISNN (2) ![In: Advances in Neural Networks - ISNN 2006, Third International Symposium on Neural Networks, Chengdu, China, May 28 - June 1, 2006, Proceedings, Part III, pp. 1340-1349, 2006, Springer, 3-540-34482-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
17 | Kyprianos Papademetriou, Apostolos Dollas |
A Task Graph Approach for Efficient Exploitation of Reconfiguration in Dynamically Reconfigurable Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 14th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2006), 24-26 April 2006, Napa, CA, USA, Proceedings, pp. 307-308, 2006, IEEE Computer Society, 0-7695-2661-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
17 | Tim Barrett, Sumit D. Mediratta, Taek-Jun Kwon, Ravinder Singh, Sachit Chandra, Jeff Sondeen, Jeffrey T. Draper |
A double-data rate (DDR) processing-in-memory (PIM) device with wideword floating-point capability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
17 | Taek-Jun Kwon, Jeff Sondeen, Jeffrey T. Draper |
Design trade-offs in floating-point unit implementation for embedded and processing-in-memory systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 3331-3334, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
17 | François Gygi, Robert K. Yates, Juergen Lorenz, Erik W. Draeger, Franz Franchetti, Christoph W. Ueberhuber, Bronis R. de Supinski, Stefan Kral, John A. Gunnels, James C. Sexton |
Large-Scale First-Principles Molecular Dynamics simulations on the BlueGene/L Platform using the Qbox code. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SC ![In: Proceedings of the ACM/IEEE SC2005 Conference on High Performance Networking and Computing, November 12-18, 2005, Seattle, WA, USA, CD-Rom, pp. 24, 2005, IEEE Computer Society, 1-59593-061-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Electronic structure, Ab initio simulations, First-principles simulations, BlueGene/L, Parallel computing, Molecular Dynamics |
17 | Sangsoo Park, Yonghee Lee, Heonshik Shin |
Experimental Performance Evaluation of Embedded Linux Using Alternative CPU Core Organizations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUC ![In: Embedded and Ubiquitous Computing, International Conference EUC 2004, Aizu-Wakamatsu City, Japan, August 25-27, 2004, Proceedings, pp. 119-130, 2004, Springer, 3-540-22906-X. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
17 | Jiansheng Chen, Yiu Sang Moon, K. F. Fong |
Efficient Fingerprint Image Enhancement for Mobile Embedded Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ECCV Workshop BioAW ![In: Biometric Authentication, ECCV 2004 International Workshop, BioAW 2004, Prague, Czech Republic, May 15, 2004, Proceedings, pp. 146-157, 2004, Springer, 3-540-22499-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
17 | Pavel Tvrdík, Ivan Simecek |
Analytical Modeling of Optimized Sparse Linear Code. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PPAM ![In: Parallel Processing and Applied Mathematics, 5th International Conference, PPAM 2003, Czestochowa, Poland, September 7-10, 2003. Revised Papers, pp. 207-216, 2003, Springer, 3-540-21946-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
17 | Jeffrey Bolz, Peter Schröder |
Rapid evaluation of Catmull-Clark subdivision surfaces. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Web3D ![In: Proceedings of the Seventh International Conference on 3D Web Technology, Web3D 2002, Tempe Mission Palms, Tempe, Arizona, USA, February 24-28, 2002, pp. 11-17, 2002, ACM, 1-58113-468-1. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
17 | Cheol-Ho Jeong, Woo-Chan Park, Tack-Don Han, Moon Key Lee, Sang-Woo Kim |
In-Order Issue Out-of-Order Execution Floating-Point Coprocessor for CalmRISC32. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 15th IEEE Symposium on Computer Arithmetic (Arith-15 2001), 11-17 June 2001, Vail, CO, USA, pp. 195-, 2001, IEEE Computer Society, 0-7695-1150-3. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
17 | Christoph Berg, Christian Jacobi 0002 |
Formal Verification of the VAMP Floating Point Unit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHARME ![In: Correct Hardware Design and Verification Methods, 11th IFIP WG 10.5 Advanced Research Working Conference, CHARME 2001, Livingston, Scotland, UK, September 4-7, 2001, Proceedings, pp. 325-339, 2001, Springer, 3-540-42541-1. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
17 | Matthias Pflanz, Karsten Walther, Heinrich Theodor Vierhaus |
On-line Error Detection Techniques for Dependable Embedded Processors with High Complexity. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTW ![In: 7th IEEE International On-Line Testing Workshop (IOLTW 2001), 9-11 July 2001, Taormina, Italy, pp. 51-53, 2001, IEEE Computer Society, 0-7695-1290-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
17 | Gülbin Ezer |
Xtensa with User Defined DSP Coprocessor Microarchitectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, ICCD '00, Austin, Texas, USA, September 17-20, 2000, pp. 335-342, 2000, IEEE Computer Society, 0-7695-0801-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
17 | Stuart F. Oberman, Hesham A. Al-Twaijry, Michael J. Flynn |
The SNAP Project: Design of Floating Point Arithmetic Unit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 13th Symposium on Computer Arithmetic (ARITH-13 '97), 6-9 July 1997, Asilomar, CA, USA, pp. 156-, 1997, IEEE Computer Society, 0-8186-7846-1. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
performance-area tradeoffs, computer arithmetic, multiplication, division, Addition, floating point unit |
17 | Peter Soderquist, Miriam Leeser |
An Area/Performance Comparison of Subtractive and Multiplicative Divide/Square Root Implementations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 12th Symposium on Computer Arithmetic (ARITH-12 '95), July 19-21, 1995, Bath, England, UK, pp. 132-139, 1995, IEEE Computer Society, 0-8186-7089-4. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
Newton-Raphson method, Goldschmidt's algorithm, microprocessor, Floating-point, division, square root, SRT |
17 | Michael H. Arnold, Walter S. Scott |
An Interactive Maze Router with Hints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 25th ACM/IEEE Conference on Design Automation, DAC '88, Anaheim, CA, USA, June 12-15, 1988., pp. 672-676, 1988, ACM. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP BibTeX RDF |
|