Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
122 | Anand Raghunathan, Sujit Dey, Niraj K. Jha |
Register-transfer level estimation techniques for switching activity and power consumption. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1996, San Jose, CA, USA, November 10-14, 1996, pp. 158-165, 1996, IEEE Computer Society / ACM, 0-8186-7597-7. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
gate-level implementation, register-transfer level estimation, logic design, power consumption, switching activity, glitching, RTL designs |
72 | Anand Raghunathan, Sujit Dey, Niraj K. Jha |
High-level macro-modeling and estimation techniques for switching activity and power consumption. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 11(4), pp. 538-557, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
66 | Janardhan H. Satyanarayana, Keshab K. Parhi |
Theoretical analysis of word-level switching activity in the presence of glitching and correlation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 8(2), pp. 148-159, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
60 | Chad Spensky, Aravind Machiry, Nathan Burow, Hamed Okhravi, Rick Housley, Zhongshu Gu, Hani Jamjoom, Christopher Kruegel, Giovanni Vigna |
Glitching Demystified: Analyzing Control-flow-based Glitching Attacks and Defenses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSN ![In: 51st Annual IEEE/IFIP International Conference on Dependable Systems and Networks, DSN 2021, Taipei, Taiwan, June 21-24, 2021, pp. 400-412, 2021, IEEE, 978-1-6654-3572-7. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
54 | Anand Raghunathan, Sujit Dey, Niraj K. Jha |
Register transfer level power optimization with emphasis on glitch analysis and reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(8), pp. 1114-1131, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
51 | Anantha P. Chandrakasan |
Ultra low power digital signal processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 9th International Conference on VLSI Design (VLSI Design 1996), 3-6 January 1996, Bangalore, India, pp. 352-357, 1996, IEEE Computer Society, 0-8186-7228-5. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
ultra low power digital signal processing, portable wireless device, capacitance minimization, spatial signal correlations, temporal signal correlations, re-synchronization, operation reduction, 1 V, logic design, DSP, power consumption, switching, integrated circuit design, voltage scaling, digital signal processing chips, circuit optimisation, circuit design, data representation, circuit optimization, glitching, architecture optimization |
48 | Janardhan H. Satyanarayana, Keshab K. Parhi |
Theoretical Analysis of Word-Level Switching Activity in the Presence of Glitching and Correlation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 4-6 March 1999, Ann Arbor, MI, USA, pp. 46-49, 1999, IEEE Computer Society, 0-7695-0104-4. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
36 | Ruzica Jevtic, Carlos Carreras |
Analytical High-Level Power Model for LUT-Based Components. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 18th International Workshop, PATMOS 2008, Lisbon, Portugal, September 10-12, 2008. Revised Selected Papers, pp. 369-378, 2008, Springer, 978-3-540-95947-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
36 | Ruzica Jevtic, Carlos Carreras, Gabriel Caffarena |
Switching Activity Models for Power Estimation in FPGA Multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARC ![In: Reconfigurable Computing: Architectures, Tools and Applications, Third International Workshop, ARC 2007, Mangaratiba, Brazil, March 27-29, 2007., pp. 201-213, 2007, Springer, 978-3-540-71430-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
36 | Ahmed Sayed, Hussain Al-Asaad |
A New Statistical Approach for Glitch Estimation in Combinational Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 1641-1644, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
36 | Brock J. LaMeres, Kanupriya Gulati, Sunil P. Khatri |
Controlling inductive cross-talk and power in off-chip buses using CODECs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, Yokohama, Japan, January 24-27, 2006, pp. 850-855, 2006, IEEE, 0-7803-9451-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
36 | Xun Liu, Marios C. Papaefthymiou |
Incorporation of input glitches into power macromodeling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2002 International Symposium on Circuits and Systems, ISCAS 2002, Scottsdale, Arizona, USA, May 26-29, 2002, pp. 846-849, 2002, IEEE, 0-7803-7448-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
30 | Hao Lin 0005, Cai Liu, Zhenhua Li 0001, Feng Qian 0001, Mingliang Li, Ping Xiong, Yunhao Liu 0001 |
Aging or Glitching? What Leads to Poor Android Responsiveness and What Can We Do About It? ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Mob. Comput. ![In: IEEE Trans. Mob. Comput. 23(2), pp. 1521-1533, February 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
30 | Xhani Marvin Saß, Richard Mitev, Ahmad-Reza Sadeghi |
Oops..! I Glitched It Again! How to Multi-Glitch the Glitching-Protections on ARM TrustZone-M. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2302.06932, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
30 | Xhani Marvin Saß, Richard Mitev, Ahmad-Reza Sadeghi |
Oops..! I Glitched It Again! How to Multi-Glitch the Glitching-Protections on ARM TrustZone-M. ![Search on Bibsonomy](Pics/bibsonomy.png) |
USENIX Security Symposium ![In: 32nd USENIX Security Symposium, USENIX Security 2023, Anaheim, CA, USA, August 9-11, 2023, pp. 6239-6256, 2023, USENIX Association. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP BibTeX RDF |
|
30 | Jonas Ruchti, Michael Gruber, Michael Pehl |
When the Decoder Has to Look Twice: Glitching a PUF Error Correction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IACR Trans. Cryptogr. Hardw. Embed. Syst. ![In: IACR Trans. Cryptogr. Hardw. Embed. Syst. 2022(3), pp. 26-70, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
30 | Otto Bittner, Thilo Krachenfels, Andreas Galauner, Jean-Pierre Seifert |
The Forgotten Threat of Voltage Glitching: A Case Study on Nvidia Tegra X2 SoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2108.06131, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP BibTeX RDF |
|
30 | Jonas Ruchti, Michael Gruber, Michael Pehl |
When the Decoder Has to Look Twice: Glitching a PUF Error Correction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IACR Cryptol. ePrint Arch. ![In: IACR Cryptol. ePrint Arch. 2021, pp. 958, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP BibTeX RDF |
|
30 | Jonathon Durand, Anisul Abedin, Jakub Szefer |
Ultra Freezing Attacks and Clock Glitching of Clock Oscillator Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AsianHOST ![In: Asian Hardware Oriented Security and Trust Symposium, AsianHOST 2021, Shanghai, China, December 16-18, 2021, pp. 1-6, 2021, IEEE, 978-1-6654-4185-8. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
30 | Otto Bittner, Thilo Krachenfels, Andreas Galauner, Jean-Pierre Seifert |
The Forgotten Threat of Voltage Glitching: A Case Study on Nvidia Tegra X2 SoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDTC ![In: 18th Workshop on Fault Detection and Tolerance in Cryptography, FDTC 2021, Milan, Italy, September 17, 2021, pp. 86-97, 2021, IEEE, 978-1-6654-3673-1. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
30 | Mingliang Li, Hao Lin 0005, Cai Liu, Zhenhua Li 0001, Feng Qian 0001, Yunhao Liu 0001, Nian Xiang Sun, Tianyin Xu |
Experience: aging or glitching? why does android stop responding and what can we do about it? ![Search on Bibsonomy](Pics/bibsonomy.png) |
MobiCom ![In: MobiCom '20: The 26th Annual International Conference on Mobile Computing and Networking, London, United Kingdom, September 21-25, 2020, pp. 20:1-20:11, 2020, ACM, 978-1-4503-7085-1. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
30 | G. Surya, Paolo Maistri, Sriram Sankaran |
Local Clock Glitching Fault Injection with Application to the ASCON Cipher. ![Search on Bibsonomy](Pics/bibsonomy.png) |
iSES ![In: IEEE International Symposium on Smart Electronic Systems, iSES 2020 (Formerly iNiS), Chennai, India, December 14-16, 2020, pp. 271-276, 2020, IEEE, 978-1-6654-0478-5. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
30 | Thomas Polzer, Florian Huemer, Andreas Steininger |
An Experimental Study of Metastability-Induced Glitching Behavior. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 28(Supplement-1), pp. 1940006:1-1940006:21, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
30 | Yifan Lu |
Injecting Software Vulnerabilities with Voltage Glitching. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1903.08102, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP BibTeX RDF |
|
30 | Raúl Jiménez-Naharro, Fernando Gómez-Bravo, Jonathan Medina García, Manuel Sanchez-Raya, Juan Antonio Gómez Galán |
A Smart Sensor for Defending against Clock Glitching Attacks on the I2C Protocol in Robotic Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Sensors ![In: Sensors 17(4), pp. 677, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
30 | Beverley Hood |
Glitching. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Creativity & Cognition ![In: Proceedings of the 2015 ACM SIGCHI Conference on Creativity and Cognition, C&C '15, Glasgow, United Kingdom, June 22-25, 2015, pp. 351-352, 2015, ACM, 978-1-4503-3598-0. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
30 | Michael Meixner, Tobias G. Noll |
Statistical Modeling of Glitching Effects in Estimation of Dynamic Power Consumption. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSID ![In: 2014 27th International Conference on VLSI Design, VLSID 2014, and 2014 13th International Conference on Embedded Systems, Mumbai, India, January 5-9, 2014, pp. 415-420, 2014, IEEE Computer Society, 978-1-4799-2513-1. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
30 | Jakub Korczyc, Andrzej Krasniewski |
Evaluation of susceptibility of FPGA-based circuits to fault injection attacks based on clock glitching. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2012, Tallinn, Estonia, April 18-20, 2012, pp. 171-174, 2012, IEEE, 978-1-4673-1187-8. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
30 | Tomasz S. Czajkowski, Stephen Dean Brown |
Using Negative Edge Triggered FFs to Reduce Glitching Power in FPGA Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 44th Design Automation Conference, DAC 2007, San Diego, CA, USA, June 4-8, 2007, pp. 324-329, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
30 | Sangjin Hong, Shu-Shin Chin, Magesh Sadasivam |
Glitching power reduction through supply voltage adaptation mechanism for low power array structure design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (2) ![In: Proceedings of the 2004 International Symposium on Circuits and Systems, ISCAS 2004, Vancouver, BC, Canada, May 23-26, 2004, pp. 733-736, 2004, IEEE, 0-7803-8251-X. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP BibTeX RDF |
|
30 | Ioannis Karafyllidis, Stelios Mavridis, Dimitrios Soudris, Adonios Thanailakis |
Estimation of power dissipation in glitching using complex-time cellular automata. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 6th IEEE International Conference on Electronics, Circuits and Systems, ICECS 1999, Pafos, Cyprus, September 5-8, 1999, pp. 1639-1642, 1999, IEEE, 0-7803-5682-9. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
18 | Julien Lamoureux, Guy G. Lemieux, Steven J. E. Wilton |
GlitchLess: Dynamic Power Minimization in FPGAs Through Edge Alignment and Glitch Filtering. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 16(11), pp. 1521-1534, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
18 | Fuding Ge, Malay Trivedi, Brent Thomas, William Jiang, Hongjiang Song |
1.5V 0.5mW 2MSPS 10B DAC with rail-to-rail output in 0.13mum CMOS technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SoCC ![In: 21st Annual IEEE International SoC Conference, SoCC 2008, September 17-20, 2008, Radisson Hotel, Newport Beach, CA, USA, Proceedings, pp. 257-260, 2008, IEEE, 978-1-4244-2596-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
18 | Julien Lamoureux, Guy G. Lemieux, Steven J. E. Wilton |
GlitchLess: an active glitch minimization technique for FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 15th International Symposium on Field Programmable Gate Arrays, FPGA 2007, Monterey, California, USA, February 18-20, 2007, pp. 156-165, 2007, ACM, 978-1-59593-600-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
field-programmable gate arrays, power minimization |
18 | V. R. Devanathan, C. P. Ravikumar, V. Kamakoti 0001 |
Interactive presentation: On power-profiling and pattern generation for power-safe scan tests. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2007 Design, Automation and Test in Europe Conference and Exposition, DATE 2007, Nice, France, April 16-20, 2007, pp. 534-539, 2007, EDA Consortium, San Jose, CA, USA, 978-3-9810801-2-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
18 | V. R. Devanathan, C. P. Ravikumar, V. Kamakoti 0001 |
Glitch-Aware Pattern Generation and Optimization Framework for Power-Safe Scan Test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 25th IEEE VLSI Test Symposium (VTS 2007), 6-10 May 2007, Berkeley, California, USA, pp. 167-172, 2007, IEEE Computer Society, 0-7695-2812-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Low Power ATPG, Glitch Power, IR Drop, Peak Power, Power-profiling |
18 | Dhananjai Madhava Rao, Philip A. Wilsey |
Applying parallel, dynamic-resolution simulations to accelerate VLSI power estimation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WSC ![In: Proceedings of the Winter Simulation Conference WSC 2006, Monterey, California, USA, December 3-6, 2006, pp. 694-702, 2006, IEEE Computer Society, 1-4244-0501-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
18 | Olli Vertanen |
Java Type Confusion and Fault Attacks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDTC ![In: Fault Diagnosis and Tolerance in Cryptography, Third International Workshop, FDTC 2006, Yokohama, Japan, October 10, 2006, Proceedings, pp. 237-251, 2006, Springer, 3-540-46250-3. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
type confusion, Java, embedded systems, fault attacks, Java Card |
18 | Wieland Fischer, Berndt M. Gammel |
Masking at Gate Level in the Presence of Glitches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHES ![In: Cryptographic Hardware and Embedded Systems - CHES 2005, 7th International Workshop, Edinburgh, UK, August 29 - September 1, 2005, Proceedings, pp. 187-200, 2005, Springer, 3-540-28474-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
random masking, masked logic circuits, Cryptanalysis, side-channel attacks, DPA, power analysis, logic circuits, digital circuits, masking, glitches |
18 | Sangjin Hong, Shu-Shin Chin |
Incorporating Power Reduction Mechanism in Arithmetic Core Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), Emerging Trends in VLSI Systems Design, 19-20 February 2004, Lafayette, LA, USA, pp. 249-250, 2004, IEEE Computer Society, 0-7695-2097-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
18 | Victor V. Zyuban |
Optimization of scannable latches for low energy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 11(5), pp. 778-788, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
18 | Horng-Bin Wang, Shi-Yu Huang, Jing-Reng Huang |
Gate-Delay Fault Diagnosis Using the Inject-and-Evaluate Paradigm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 6-8 November 2002, Vancouver, BC, Canada, Proceedings, pp. 117-128, 2002, IEEE Computer Society, 0-7695-1831-1. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
18 | Sergei P. Skorobogatov, Ross J. Anderson |
Optical Fault Induction Attacks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHES ![In: Cryptographic Hardware and Embedded Systems - CHES 2002, 4th International Workshop, Redwood Shores, CA, USA, August 13-15, 2002, Revised Papers, pp. 2-12, 2002, Springer, 3-540-00409-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
18 | K'Andrea C. Bickerstaff, Earl E. Swartzlander Jr., Michael J. Schulte |
Analysis of Column Compression Multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 15th IEEE Symposium on Computer Arithmetic (Arith-15 2001), 11-17 June 2001, Vail, CO, USA, pp. 33-39, 2001, IEEE Computer Society, 0-7695-1150-3. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
18 | Artur Wróblewski, Otto Schumacher, Christian V. Schimpfle, Josef A. Nossek |
Minimizing gate capacitances with transistor sizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, pp. 186-189, 2001, IEEE, 0-7803-6685-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
18 | Antonio G. M. Strollo, Ettore Napoli, Carlo Cimino |
Analysis of power dissipation in double edge-triggered flip-flops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 8(5), pp. 624-629, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
18 | Subodh Gupta, Farid N. Najm |
Power modeling for high-level power estimation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 8(1), pp. 18-29, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
18 | Henrik Eriksson, Per Larsson-Edefors |
Impact of Voltage Scaling on Glitch Power Consumption. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation, 10th International Workshop, PATMOS 2000, Göttingen, Germany, September 13-15, 2000, Proceedings, pp. 139-148, 2000, Springer, 3-540-41068-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
18 | Sujit Dey, Anand Raghunathan, Niraj K. Jha, Kazutoshi Wakabayashi |
Controller-based power management for control-flow intensive designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(10), pp. 1496-1508, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
18 | Christian V. Schimpfle, Sven Simon 0001, Josef A. Nossek |
Device level based cell modeling for fast power estimation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30 - June 2, 1999, pp. 90-93, 1999, IEEE, 0-7803-5471-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
18 | Anand Raghunathan, Sujit Dey, Niraj K. Jha, Kazutoshi Wakabayashi |
Power Management Techniques for Control-Flow Intensive Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 34st Conference on Design Automation, Anaheim, California, USA, Anaheim Convention Center, June 9-13, 1997., pp. 429-434, 1997, ACM Press, 0-89791-920-3. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
18 | Chin-Chi Teng, Anthony M. Hill, Sung-Mo Kang |
Estimation of maximum transition counts at internal nodes in CMOS VLSI circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1995, San Jose, California, USA, November 5-9, 1995, pp. 366-370, 1995, IEEE Computer Society / ACM, 0-8186-7213-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
maximum switching activity, uncertainty waveforms, circuit reliability |
18 | Srinivas Devadas, Kurt Keutzer, Jacob K. White 0001 |
Estimation of power dissipation in CMOS combinational circuits using Boolean function manipulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(3), pp. 373-383, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|