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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 6626 occurrences of 3075 keywords
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Results
Found 22479 publication records. Showing 22466 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
83 | Matthew T. O'Keefe, Henry G. Dietz |
Loop Coalescing and Scheduling for Barrier MIMD Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 4(9), pp. 1060-1064, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
barrier MIMD, multiple instruction stream, multiple datastream, loop coalescing, nested loop structures, compiler parallelization, static barrierMIMD, scheduling, scheduling, parallel programming, parallel architectures, compiler optimization, program compilers, asynchronous, loop transformations, barrier synchronization, linear scheduling |
80 | Kathryn S. McKinley, Steve Carr 0001, Chau-Wen Tseng |
Improving Data Locality with Loop Transformations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Program. Lang. Syst. ![In: ACM Trans. Program. Lang. Syst. 18(4), pp. 424-453, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
loop distribution, loop permutation, loop reversal, simulation, Cache, microprocessors, compiler optimization, data locality, loop transformations, loop fusion |
77 | Meilin Liu, Qingfeng Zhuge, Zili Shao, Chun Xue, Mei Kang Qiu, Edwin Hsing-Mean Sha |
Loop Distribution and Fusion with Timing and Code Size Optimization for Embedded DSPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUC ![In: Embedded and Ubiquitous Computing - EUC 2005, International Conference EUC 2005, Nagasaki, Japan, December 6-9, 2005, Proceedings, pp. 121-130, 2005, Springer, 3-540-30807-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Loop Distribution, Embedded DSP, Scheduling, Code Size, Loop Fusion |
76 | Litong Song, Krishna M. Kavi |
What can we gain by unfolding loops? ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM SIGPLAN Notices ![In: ACM SIGPLAN Notices 39(2), pp. 26-33, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
loop peeling, loop quasi invariant code motion, quasi-index variable, quasi-invariant variable, loop unrolling |
75 | Sachin Shaw, Pawan Kumar |
Loop-dead optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM SIGPLAN Notices ![In: ACM SIGPLAN Notices 40(2), pp. 33-40, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
69 | Jack W. Davidson, Sanjay Jinturkar |
Aggressive Loop Unrolling in a Retargetable Optimizing Compiler. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CC ![In: Compiler Construction, 6th International Conference, CC'96, Linköping, Sweden, April 24-26, 1996, Proceedings, pp. 59-73, 1996, Springer, 3-540-61053-7. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
Code improving transformations, Compiler optimizations, Loop transformations, Loop unrolling |
68 | Dorit Nuzman, Ayal Zaks |
Outer-loop vectorization: revisited for short SIMD architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PACT ![In: 17th International Conference on Parallel Architectures and Compilation Techniques, PACT 2008, Toronto, Ontario, Canada, October 25-29, 2008, pp. 2-11, 2008, ACM, 978-1-60558-282-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
SIMD, vectorization, data reuse, subword parallelism |
65 | Chandan Kumar Behera, Pawan Kumar |
An improved algorithm for loop dead optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM SIGPLAN Notices ![In: ACM SIGPLAN Notices 41(5), pp. 11-20, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
loop invariant computations, loop optimization, compiler design |
65 | Chandan Kumar Behera, Pawan Kumar |
An improved algorithm for loop dead optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM SIGPLAN Notices ![In: ACM SIGPLAN Notices 40(11), pp. 18-28, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
loop invariant computations, loop optimization, compiler design |
65 | Uwe Horn, Thomas Wiegand, Bernd Girod |
Bit Allocation Methods for Closed-Loop Coding of Oversampled Pyramid Decompositions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICIP (2) ![In: Proceedings 1997 International Conference on Image Processing, ICIP '97, Santa Barbara, California, USA, October 26-29, 1997, pp. 17-20, 1997, IEEE Computer Society, 0-8186-8183-7. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
bit allocation methods, closed-loop coding, oversampled pyramid decompositions, quantization noise feedback, selected operational points, optimal open-loop bit allocation, video coding, resolution, scalable video coding, rate-distortion performance |
64 | Robert Müllner, Carsten F. Ball, Kolio Ivanov, Johann Lienhart, Peter Hric |
Performance comparison between open-loop and closed-loop uplink power control in UTRAN LTE networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IWCMC ![In: Proceedings of the International Conference on Wireless Communications and Mobile Computing: Connecting the World Wirelessly, IWCMC 2009, Leipzig, Germany, June 21-24, 2009, pp. 1410-1416, 2009, ACM, 978-1-60558-569-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
FPC, closed-loop PC, open-loop PC, LTE, UL |
64 | R. Al-Omari, G. Manimaran, Murti V. Salapaka, Arun K. Somani |
Novel Algorithms for Open-Loop and Closed-Loop Scheduling of Real-Time Tasks in Multiprocessor Systems Based on Execution Time Estimation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 22-26 April 2003, Nice, France, CD-ROM/Abstracts Proceedings, pp. 7, 2003, IEEE Computer Society, 0-7695-1926-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Open-loop scheduling, Closed-loop scheduling, Modeling, Real-time scheduling, Multiprocessor systems, Feedback control |
60 | Rajiv Gupta 0001 |
Loop displacement: an approach for transforming and scheduling loops for parallel execution. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SC ![In: Proceedings Supercomputing '90, New York, NY, USA, November 12-16, 1990, pp. 388-397, 1990, IEEE Computer Society, 0-89791-412-0. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
59 | Muriel Médard, Richard A. Barry, Steven G. Finn, Wenbo He, Steven Lumetta |
Generalized loop-back recovery in optical mesh networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE/ACM Trans. Netw. ![In: IEEE/ACM Trans. Netw. 10(1), pp. 153-164, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
loop-back, network restoration, mesh networks, WDM |
56 | Michael E. Wolf, Monica S. Lam |
A Loop Transformation Theory and an Algorithm to Maximize Parallelism. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 2(4), pp. 452-471, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
loop transformation theory, general loops, dependence vectors, lexicographically positive, compound transformations, coarsest fully permutable loop nests, fully permutable nests, parallel algorithm, parallel algorithms, parallel programming, heuristics, program compilers, precedence constraints, legality, code transformation, fine-grain parallelism, canonical form, wavefront, coarse grain parallelism, loop iterations, maximum degree |
56 | Hongbo Rong, Zhizhong Tang, Ramaswamy Govindarajan, Alban Douillet, Guang R. Gao |
Single-dimension software pipelining for multidimensional loops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Archit. Code Optim. ![In: ACM Trans. Archit. Code Optim. 4(1), pp. 7, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Software pipelining, loop transformation, modulo scheduling |
56 | Qi Ning, Vincent Van Dongen, Guang R. Gao |
Automatic data and computation decomposition for distributed memory machines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HICSS (2) ![In: 28th Annual Hawaii International Conference on System Sciences (HICSS-28), January 3-6, 1995, Kihei, Maui, Hawaii, USA, pp. 103-112, 1995, IEEE Computer Society, 0-8186-6945-4. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
automatic data decomposition, automatic computation decomposition, compile-time technique, complex programs, perfect loop nests, nonperfect loop nests, loop-carried dependences, loop nest clusters, data locality constraint relaxation, homogeneous linear equations, hierarchical program nesting structures, nesting levels, compiler development, EPPP project, Environment for Portable Parallel Programming, computational complexity, parallel programming, parallelism, polynomial time algorithms, distributed memory systems, software portability, relaxation, distributed memory machines, program control structures, parallelising compilers, data redistributions, equations, data handling |
55 | Alain Darte, Guillaume Huard |
Loop Shifting for Loop Compaction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCPC ![In: Languages and Compilers for Parallel Computing, 12th International Workshop, LCPC'99, La Jolla/San Diego, CA, USA, August 4-6, 1999, Proceedings, pp. 415-431, 1999, Springer, 3-540-67858-1. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
55 | Jian Wang, Guang R. Gao |
Pipelining-Dovetailing: A Transformation to Enhance Software Pipelining for Nested Loops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CC ![In: Compiler Construction, 6th International Conference, CC'96, Linköping, Sweden, April 24-26, 1996, Proceedings, pp. 1-17, 1996, Springer, 3-540-61053-7. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
Very Long Instruction Word(VLIW), Instruction-Level Parallelism, Software Pipelining, Superscalar, Nested Loop, Loop Scheduling, Fine-Grain Parallelism |
54 | Evangelos P. Markatos, Thomas J. LeBlanc |
Using Processor Affinity in Loop Scheduling on Shared-Memory Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 5(4), pp. 379-400, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
processoraffinity, kernel programs, Silicon Graphics multiprocessor, BBN Butterfly, SequentSymmetry, KSR-1, scheduling, performance evaluation, synchronization, shared-memory multiprocessors, shared memory systems, iterations, performance improvements, communication overhead, loop scheduling, loop iterations, load imbalance |
53 | Litong Song, Krishna M. Kavi, Ron Cytron |
An Unfolding-Based Loop Optimization Technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SCOPES ![In: Software and Compilers for Embedded Systems, 7th International Workshop, SCOPES 2003, Vienna, Austria, September 24-26, 2003, Proceedings, pp. 117-132, 2003, Springer, 3-540-20145-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
52 | Jordi Torres, Eduard Ayguadé, Jesús Labarta, Mateo Valero |
Loop Parallelization: Revisiting Framework of Unimodular Transformations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PDP ![In: 4th Euromicro Workshop on Parallel and Distributed Processing (PDP '96), January 24-26, 1996, Portugal, pp. 420-428, 1996, IEEE Computer Society, 0-8186-7376-1. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
linear loop transformations, nonlinear step, transformation process, maximum loop parallelism, perfect nested loops, tight recurrences, MIMD system, parallel algorithms, parallelizing algorithm, parallel programming, graph theory, dependence graph, loop parallelization, optimising compilers, coarse grain parallelism, unimodular transformations |
50 | Qing Yi, Ken Kennedy, Vikram S. Adve |
Transforming Complex Loop Nests for Locality. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Supercomput. ![In: J. Supercomput. 27(3), pp. 219-264, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
complex loop structure, linear algebra kernels, compiler optimization, loop transformation |
50 | Michael E. Wolf, Dror E. Maydan, Ding-Kai Chen |
Combining Loop Transformations Considering Caches and Scheduling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 29th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 29, Paris, France, December 2-4, 1996, pp. 274-286, 1996, ACM/IEEE Computer Society, 0-8186-7641-8. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
cache tiling, fission, loop interchange, outer loop unrolling, fusion, instruction scheduling |
49 | T. S. B. Sudarshan, Rahil Mir, S. Vijayalakshmi |
DRIL- A Flexible Architecture for Blowfish Encryption Using Dynamic Reconfiguration, Replication, Inner-Loop Pipelining, Loop Folding Techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asia-Pacific Computer Systems Architecture Conference ![In: Advances in Computer Systems Architecture, 10th Asia-Pacific Conference, ACSAC 2005, Singapore, October 24-26, 2005, Proceedings, pp. 625-639, 2005, Springer, 3-540-29643-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Blowfish, inner loop pipeline, loop folding, four - tier architecture, Platform independent architecture, DRIL Architecture, replication, Dynamic reconfiguration |
49 | Qubo Hu, Per Gunnar Kjeldsberg, Arnout Vandecappelle, Martin Palkovic, Francky Catthoor |
Incremental hierarchical memory size estimation for steering of loop transformations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 12(4), pp. 50, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Data optimization, memory architecture exploration, memory size estimation, high-level synthesis, code transformation |
48 | Seng Lin Shee, Sri Parameswaran, Newton Cheung |
Novel architecture for loop acceleration: a case study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2005, Jersey City, NJ, USA, September 19-21, 2005, pp. 297-302, 2005, ACM, 1-59593-161-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
tightly coupled, architecture, ASIP, hardware/software partitioning, coprocessor, loop optimization, latency hiding, loop pipelining, loop acceleration |
48 | Minjoong Rim, Rajiv Jain |
Valid Transformations: A New Class of Loop Transformations for High-Level Synthesis and Pipelined Scheduling Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 7(4), pp. 399-410, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
super-scalar, loop compilation, High-level synthesis, VLIW, loop transformations, loop optimization, pipeline scheduling |
48 | Erik H. D'Hollander |
Partitioning and Labeling of Loops by Unimodular Transformations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 3(4), pp. 465-476, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
loop labelling, invariant dependence relation, independent subsets, constant dependence vectors, serial loop, parallel DO-ALL loops, dependent iterations, n-fold nested loop, multithreaded dynamicscheduling, join primitive, scheduling, parallel algorithms, computational complexity, program compilers, programming theory, partitioning algorithm, parallelprogramming, labelling algorithm, unimodular transformations, unimodular transformation, loop partitioning, dependence matrix |
47 | Xiucai Ji, Hui Zhang 0053, Dan Hai, Zhiqiang Zheng |
A Decision-Theoretic Active Loop Closing Approach to Autonomous Robot Exploration and Mapping. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RoboCup ![In: RoboCup 2008: Robot Soccer World Cup XII [papers from the 12th annual RoboCup International Symposium, Suzhou, China, July 15-18, 2008], pp. 507-518, 2008, Springer, 978-3-642-02920-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
active loop closing, particle filter, decision theory, SLAM |
47 | Xingwu Liu, Juhua Pu, Jianzhong Pan |
A Classification of Degenerate Loop Agreement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IFIP TCS ![In: Fifth IFIP International Conference On Theoretical Computer Science - TCS 2008, IFIP 20th World Computer Congress, TC 1, Foundations of Computer Science, September 7-10, 2008, Milano, Italy, pp. 203-213, 2008, Springer, 978-0-387-09679-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
loop agreement, classification, distributed computing, computability |
47 | Chun Xue, Zili Shao, Edwin Hsing-Mean Sha |
Maximize Parallelism Minimize Overhead for Nested Loops via Loop Striping. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 47(2), pp. 153-167, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
optimization, parallelism, loop transformation |
47 | Meilin Liu, Qingfeng Zhuge, Zili Shao, Edwin Hsing-Mean Sha |
General loop fusion technique for nested loops considering timing and code size. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2004 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2004, Washington DC, USA, September 22 - 25, 2004, pp. 190-201, 2004, ACM, 1-58113-890-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
embedded DSP, scheduling, retiming, code size, loop fusion |
47 | Waibhav Tembe, Santosh Pande |
Loop Restructuring for Data I/O Minimization on Limited On-Chip Memory Embedded Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 51(10), pp. 1269-1280, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
embedded processors, data locality, program dependence graph, Loop fusion, limited memory |
47 | Mahmut T. Kandemir, Alok N. Choudhary, J. Ramanujam, Prithviraj Banerjee |
A Matrix-Based Approach to the Global Locality Optimization Problem. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE PACT ![In: Proceedings of the 1998 International Conference on Parallel Architectures and Compilation Techniques, Paris, France, October 12-18, 1998, pp. 306-313, 1998, IEEE Computer Society, 0-8186-8591-3. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
optimizing for locality, global (whole program) optimization, combined unified loop and data transformations, loop transformations, data layout optimizations |
46 | Gayathri Krishnamurthy, Elana D. Granston, Eric Stotzer |
Affinity-based cluster assignment for unrolled loops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICS ![In: Proceedings of the 16th international conference on Supercomputing, ICS 2002, New York City, NY, USA, June 22-26, 2002, pp. 107-116, 2002, ACM, 1-58113-483-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
affinity-based clustering (ABC) algorithms, homogeneous clusters, partitioned register files, software pipelining, loop optimizations, loop scheduling, VLIW architectures, loop unrolling, cluster assignment |
46 | Yin-Chao Huang, Chung-Len Lee 0001, Jun-Weir Lin, Jwu E. Chen, Chauchin Su |
A methodology for fault model development for hierarchical linear systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, pp. 90-95, 2000, IEEE Computer Society, 0-7695-0887-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
closed loop systems, hierarchical linear systems, transfer function model, open-loop, element faults, benchmark state-variable filter, AC fault model, state variable filter, fault diagnosis, fault model, fault simulation, modules, Monte Carlo methods, Monte Carlo simulation, transfer functions, computation time, operational amplifiers, operational amplifiers, closed loop, analogue circuits |
46 | Wesley K. Kaplow, William Maniatty, Boleslaw K. Szymanski |
Impact of memory hierarchy on program partitioning and scheduling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HICSS (2) ![In: 28th Annual Hawaii International Conference on System Sciences (HICSS-28), January 3-6, 1995, Kihei, Maui, Hawaii, USA, pp. 93-102, 1995, IEEE Computer Society, 0-8186-6945-4. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
parallel program scheduling, nonlinear cache-miss rates, loop nest execution simulation, architecturally parameterized cache simulator, loop range, cache-miss ratio, loop interchange, iteration-space blocking, program runtime estimation, IBM 9076 SP1, SuperSPARC, scheduling, parallel programming, optimisation, memory hierarchy, processor scheduling, software performance evaluation, memory architecture, cache storage, program optimization, cache performance, program control structures, program partitioning, Intel i860 |
45 | Mahmut T. Kandemir, Taylan Yemliha, Seung Woo Son 0001, Ozcan Ozturk 0001 |
Memory bank aware dynamic loop scheduling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2007 Design, Automation and Test in Europe Conference and Exposition, DATE 2007, Nice, France, April 16-20, 2007, pp. 1671-1676, 2007, EDA Consortium, San Jose, CA, USA, 978-3-9810801-2-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
45 | Meilin Liu, Qingfeng Zhuge, Zili Shao, Chun Xue, Meikang Qiu, Edwin Hsing-Mean Sha |
Maximum Loop Distribution and Fusion for Two-level Loops Considering Code Size. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPAN ![In: 8th International Symposium on Parallel Architectures, Algorithms, and Networks, ISPAN 2005, December 7-9. 2005, Las Vegas, Nevada, USA, pp. 126-131, 2005, IEEE Computer Society, 0-7695-2509-1. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
45 | Zhong Wang, Edwin Hsing-Mean Sha, Xiaobo Hu 0001 |
Combined partitioning and data padding for scheduling multiple loop nests. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2001 International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES 2001, Atlanta, Georgia, USA, November 16-17, 2001, pp. 67-75, 2001, ACM, 1-58113-399-5. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
45 | Reinhard von Hanxleden, Ken Kennedy |
Relaxing SIMD Control Flow Constraints using Loop Transformations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PLDI ![In: Proceedings of the ACM SIGPLAN'92 Conference on Programming Language Design and Implementation (PLDI), San Francisco, California, USA, June 17-19, 1992, pp. 188-199, 1992, ACM, 0-89791-475-9. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
FORTRAN |
44 | Marta Jiménez, José M. Llabería, Agustín Fernández |
A Cost-Effective Implementation of Multilevel Tiling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 14(10), pp. 1006-1020, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
multilevel tiling, Compilers, memory hierarchy, loop transformations |
44 | Ravi S. Prasad, Constantine Dovrolis |
Beyond the Model of Persistent TCP Flows: Open-Loop vs Closed-Loop Arrivals of Non-persistent Flows. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Annual Simulation Symposium ![In: Proceedings 41st Annual Simulation Symposium (ANSS-41 2008), April 14-16, 2008, Ottawa, Canada, pp. 121-130, 2008, IEEE Computer Society, 0-7695-3143-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
44 | Kin Leong Ho, Paul M. Newman |
Detecting Loop Closure with Scene Sequences. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Comput. Vis. ![In: Int. J. Comput. Vis. 74(3), pp. 261-286, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
loop closing, scene appearance and navigation, multi-robot navigation, mobile robotics, SLAM |
44 | Liping Xue, Mahmut T. Kandemir, Guangyu Chen, Taylan Yemliha |
SPM Conscious Loop Scheduling for Embedded Chip Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPADS (1) ![In: 12th International Conference on Parallel and Distributed Systems, ICPADS 2006, Minneapolis, Minnesota, USA, July 12-15, 2006, pp. 391-400, 2006, IEEE Computer Society, 0-7695-2612-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
SPM (Scratch-Pad Memory), dynamic loop scheduling, parallelization, compiler, CMP (chip multiprocessor), data locality |
43 | Minyi Guo, Weng-Long Chang, Yi Pan 0001 |
Optimization Techniques for Parallel Codes of Irregular Scientific Computations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPP Workshops ![In: 31st International Conference on Parallel Processing Workshops (ICPP 2002 Workshops), 20-23 August 2002, Vancouver, BC, Canada, pp. 405-413, 2002, IEEE Computer Society, 0-7695-1680-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Irregular scientific application, Interprocedural optimization, Parallelizing compilers, Loop transformation, Communication optimization, Loop partitioning |
42 | Duo Liu, Zili Shao, Meng Wang 0005, Minyi Guo, Jingling Xue |
Optimal loop parallelization for maximizing iteration-level parallelism. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2009 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2009, Grenoble, France, October 11-16, 2009, pp. 67-76, 2009, ACM. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
iteration-level parallelism, retiming, loop transformation, loop parallelization, data dependence graph |
42 | Mahmut T. Kandemir, Prithviraj Banerjee, Alok N. Choudhary, J. Ramanujam, Eduard Ayguadé |
Static and Dynamic Locality Optimizations Using Integer Linear Programming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 12(9), pp. 922-941, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
cache miss estimation, compiler optimizations, integer linear programming, Data reuse, cache locality, memory layouts |
42 | Alex Waibel, Hartwig U. Steusloff, Rainer Stiefelhagen, Kym Watson |
Computers in the Human Interaction Loop. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Computers in the Human Interaction Loop ![In: Computers in the Human Interaction Loop, pp. 3-6, 2009, Springer, 978-1-84882-053-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
42 | Tien-Fu Chen |
Efficient trace-sampling simulation techniques for cache performance analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Annual Simulation Symposium ![In: Proceedings 29st Annual Simulation Symposium (SS '96), April 8-11, 1996, New Orleans, LA, USA, pp. 54-, 1996, IEEE Computer Society, 0-8186-7432-6. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
efficient trace sampling simulation techniques, cache performance analysis, large cache simulation, space sampling technique, index of locality, trace references, time sampling approach, inter loop intervals, time sampling technique, representative performance results, loop execution, simulation time, small estimate errors, performance evaluation, virtual machines, digital simulation, performance metric, cache storage, stratified sampling, loop iterations, trace reduction |
42 | Zbigniew Chamski |
Enumeration of dense non-convex iteration sets. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PDP ![In: 3rd Euromicro Workshop on Parallel and Distributed Processing (PDP '95), January 25-27, 1995, San Remo, Italy, pp. 156-163, 1995, IEEE Computer Society, 0-8186-7031-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
dense non-convex iteration sets, algorithmic problems, iteration domains, loop structures, arbitrary unions, dense convex polyhedra, incremental construction, nested loop sequence, loop execution, parallel algorithms, parallel programming, parallel programming, set theory, polyhedron, scientific programs |
41 | Yuan Zhao, Ken Kennedy |
Scalarization Using Loop Alignment and Loop Skewing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Supercomput. ![In: J. Supercomput. 31(1), pp. 5-46, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
array syntax, loop alignment, loop skewing, Fortran 90/95, memory hierarchy performance, compiler optimization, stencil computation, scalarization |
41 | Ozcan Ozturk 0001, Mahmut T. Kandemir, Sri Hari Krishna Narayanan |
A Scratch-Pad Memory Aware Dynamic Loop Scheduling Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 9th International Symposium on Quality of Electronic Design (ISQED 2008), 17-19 March 2008, San Jose, CA, USA, pp. 738-743, 2008, IEEE Computer Society, 978-0-7695-3117-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Scheduling and Partitioning, Compilers, Multiprocessor Systems |
41 | Tsu-Ming Liu, Wen-Ping Lee, Chen-Yi Lee |
An In/Post-Loop Deblocking Filter With Hybrid Filtering Schedule. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. Video Technol. ![In: IEEE Trans. Circuits Syst. Video Technol. 17(7), pp. 937-943, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
41 | Sanghun Lee, Hirotomo Aso |
Loop-Synthesizing Transformation for Maintaining Parallelism and Enhancing Locality. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPP Workshops ![In: 32nd International Conference on Parallel Processing Workshops (ICPP 2003 Workshops), 6-9 October 2003, Kaohsiung, Taiwan, pp. 156-163, 2003, IEEE Computer Society, 0-7695-2018-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
41 | Bob Blainey, Christopher Barton, José Nelson Amaral |
Removing Impediments to Loop Fusion Through Code Transformations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCPC ![In: Languages and Compilers for Parallel Computing, 15th Workshop, LCPC 2002, College Park, MD, USA, July 25-27, 2002, Revised Papers, pp. 309-328, 2002, Springer, 3-540-30781-8. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
40 | Qubo Hu, Arnout Vandecappelle, Martin Palkovic, Per Gunnar Kjeldsberg, Erik Brockmeyer, Francky Catthoor |
Hierarchical memory size estimation for loop fusion and loop shifting in data-dominated applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, Yokohama, Japan, January 24-27, 2006, pp. 606-611, 2006, IEEE, 0-7803-9451-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
40 | Jingling Xue, Minyi Guo, Daming Wei |
Improving the parallelism of iterative methods by aggressive loop fusion. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Supercomput. ![In: J. Supercomput. 43(2), pp. 147-164, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Parallelism, Data dependence, Cache locality, Loop fusion |
40 | Hovhannes A. Harutyunyan, Edward Maraachlian |
Near Optimal Broadcasting in Optimal Triple Loop Graphs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AINA ![In: 22nd International Conference on Advanced Information Networking and Applications, AINA 2008, GinoWan, Okinawa, Japan, March 25-28, 2008, pp. 227-233, 2008, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
triple loop graphs, Broadcasting |
40 | Kevin Fan, Manjunath Kudlur, Hyunchul Park 0001, Scott A. Mahlke |
Increasing hardware efficiency with multifunction loop accelerators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2006, Seoul, Korea, October 22-25, 2006, pp. 276-281, 2006, ACM, 1-59593-370-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
multifunction design, high-level synthesis, modulo scheduling, loop accelerator, application-specific hardware |
40 | Wen-Chung Shih, Chao-Tung Yang, Shian-Shyong Tseng |
A Hybrid Parallel Loop Scheduling Scheme on Grid Environments. ![Search on Bibsonomy](Pics/bibsonomy.png) |
GCC ![In: Grid and Cooperative Computing - GCC 2005, 4th International Conference, Beijing, China, November 30 - December 3, 2005, Proceedings, pp. 370-381, 2005, Springer, 3-540-30510-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
grid computing, Globus, Loop scheduling, self-scheduling, NWS |
40 | Enric Rodríguez-Carbonell, Deepak Kapur |
Automatic generation of polynomial loop. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSAC ![In: Symbolic and Algebraic Computation, International Symposium ISSAC 2004, Santander, Spain, July 4-7, 2004, Proceedings, pp. 266-273, 2004, ACM, 1-58113-827-X. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
ideal, loop invariant, groebner basis |
40 | Joe W. Duran |
Heuristics for program synthesis using loop invariants. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Annual Conference (2) ![In: Proceedings 1978 ACM Annual Conference, Washington, DC, USA, December 4-6, 1978, Volume II, pp. 891-900, 1978, ACM, 978-0-89791-000-2. The full citation details ...](Pics/full.jpeg) |
1978 |
DBLP DOI BibTeX RDF |
Automatic programming, Program synthesis, Program correctness, Loop invariants |
39 | Like Yan, Gang Wang, Tianzhou Chen |
The input-aware dynamic adaptation of area and performance for reconfigurable accelerator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, FPGA 2009, Monterey, California, USA, February 22-24, 2009, pp. 281, 2009, ACM, 978-1-60558-410-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
dynamic adaption, reconfigurable system, loop unrolling, loop accelerator |
39 | G. Ramalingam |
On loops, dominators, and dominance frontiers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Program. Lang. Syst. ![In: ACM Trans. Program. Lang. Syst. 24(5), pp. 455-490, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
irreducible graph, iterated dominance frontier, least common ancestor, loop nesting forest, sparse evaluation, graph transformation, Dominator, loop |
39 | Martin Griebl, Christian Lengauer |
On Scanning Space-Time Mapped While Loops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CONPAR ![In: Parallel Processing: CONPAR 94 - VAPP VI, Third Joint International Conference on Vector and Parallel Processing, Linz, Austria, September 6-8, 1994, Proceedings, pp. 677-688, 1994, Springer, 3-540-58430-7. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
while loop, parallelizing compilation, loop parallelization, space-time mapping |
38 | Li-Juan Jia, Ran Tao 0003, Yue Wang 0001, Kiyoshi Wada |
Realizations of BELS as WIV method in both direct and indirect closed-loop system identification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Sci. China Ser. F Inf. Sci. ![In: Sci. China Ser. F Inf. Sci. 52(4), pp. 712-722, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
direct closed-loop system identification, indirect closed-loop system identification, bias eliminated least squares method, weighted instrumental variables method |
38 | Alain Darte |
On the Complexity of Loop Fusion. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE PACT ![In: Proceedings of the 1999 International Conference on Parallel Architectures and Compilation Techniques, Newport Beach, California, USA, October 12-16, 1999, pp. 149-157, 1999, IEEE Computer Society, 0-7695-0425-6. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
loop distribution, complexity, parallelization, loop fusion |
38 | Cheng-Tien Wu, Chao-Tung Yang, Shian-Shyong Tseng |
PPD: A practical parallel loop detector for parallelizing compilers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPADS ![In: 1996 International Conference on Parallel and Distributed Systems (ICPADS '96), June 3-6, 1996, Tokyo, Japan, Proceedings, pp. 274-281, 1996, IEEE Computer Society, 0-8186-7267-6. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
PPD, practical parallel loop detector, DOALL, practical parallelism detector, portable FORTRAN parallelizing compiler, OSF/1, ZIV test, I test, array subscripts, synchronization statement, parallel programming, FORTRAN, synchronisation, parallelizing compilers, parallelising compilers, DOACROSS loop |
38 | Wei Li 0015, Keshav Pingali |
Access Normalization: Loop Restructuring for NUMA Compilers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Comput. Syst. ![In: ACM Trans. Comput. Syst. 11(4), pp. 353-375, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
nonsingular loop transformation, nonuniform memory access machines, parallelizing compilers, data locality, loop transformation |
38 | Hongbo Rong, Zhizhong Tang, Ramaswamy Govindarajan, Alban Douillet, Guang R. Gao |
Single-Dimension Software Pipelining for Multi-Dimensional Loops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CGO ![In: 2nd IEEE / ACM International Symposium on Code Generation and Optimization (CGO 2004), 20-24 March 2004, San Jose, CA, USA, pp. 163-174, 2004, IEEE Computer Society, 0-7695-2102-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
38 | Kalyan Muthukumar, Gautam Doshi |
Software Pipelining of Nested Loops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CC ![In: Compiler Construction, 10th International Conference, CC 2001 Held as Part of the Joint European Conferences on Theory and Practice of Software, ETAPS 2001 Genova, Italy, April 2-6, 2001, Proceedings, pp. 165-181, 2001, Springer, 3-540-41861-X. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
37 | Kyoko Iwasawa, Alan Mycroft |
Choosing Method of the Most Effective Nested Loop Shearing for Parallelism. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PDCAT ![In: Eighth International Conference on Parallel and Distributed Computing, Applications and Technologies (PDCAT 2007), 3-6 December 2007, Adelaide, Australia, pp. 267-276, 2007, IEEE Computer Society, 0-7695-3049-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
37 | Chun Xue, Zili Shao, Meilin Liu, Mei Kang Qiu, Edwin Hsing-Mean Sha |
Loop Striping: Maximize Parallelism for Nested Loops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUC ![In: Embedded and Ubiquitous Computing, International Conference, EUC 2006, Seoul, Korea, August 1-4, 2006, Proceedings, pp. 405-414, 2006, Springer, 3-540-36679-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
37 | Guang Chen, Mengjie Zhang 0001 |
Evolving While-Loop Structures in Genetic Programming for Factorial and Ant Problems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Australian Conference on Artificial Intelligence ![In: AI 2005: Advances in Artificial Intelligence, 18th Australian Joint Conference on Artificial Intelligence, Sydney, Australia, December 5-9, 2005, Proceedings, pp. 1079-1085, 2005, Springer, 3-540-30462-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
37 | Sumit Gupta, Nikil D. Dutt, Rajesh Gupta 0001, Alexandru Nicolau |
Loop Shifting and Compaction for the High-Level Synthesis of Designs with Complex Control Flow. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France, pp. 114-121, 2004, IEEE Computer Society, 0-7695-2085-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
37 | Mao-Jun He, Wen-Jian Cai, Shaoyuan Li |
New criterion for control loop configuration of multivariable processes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICARCV ![In: 8th International Conference on Control, Automation, Robotics and Vision, ICARCV 2004, Kunming, China, 6-9 December 2004, Proceedings, pp. 913-918, 2004, IEEE, 0-7803-8653-1. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
37 | Alberto Porta, Raffaello Furlan, Ornella Rimoldi, Massimo Pagani, Alberto Malliani, Philippe van de Borne |
Quantifying the strength of the linear causal coupling in closed loop interacting cardiovascular variability signals. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Biol. Cybern. ![In: Biol. Cybern. 86(3), pp. 241-251, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
37 | Lei Wang, Waibhav Tembe, Santosh Pande |
A Framework for Loop Distribution on Limited On-Chip Memory Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CC ![In: Compiler Construction, 9th International Conference, CC 2000, Held as Part of the European Joint Conferences on the Theory and Practice of Software, ETAPS 2000, Berlin, Germany, March 25 - April 2, 2000, Proceedings, pp. 141-156, 2000, Springer, 3-540-67263-X. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
37 | Mahmut T. Kandemir, J. Ramanujam, Alok N. Choudhary, Prithviraj Banerjee |
A Layout-Conscious Iteration Space Transformation Technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 50(12), pp. 1321-1336, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
program optimization, loop transformations, Data reuse, cache locality, memory layouts |
37 | Jingling Xue |
Affine-by-Statement Transformations of Imperfectly Nested Loops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPPS ![In: Proceedings of IPPS '96, The 10th International Parallel Processing Symposium, April 15-19, 1996, Honolulu, Hawaii, USA, pp. 34-38, 1996, IEEE Computer Society, 0-8186-7255-2. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
imperfectly nested loops, code generation, loop transformation |
36 | Frank Hannig, Hritam Dutta, Jürgen Teich |
Parallelization Approaches for Hardware Accelerators - Loop Unrolling Versus Loop Partitioning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARCS ![In: Architecture of Computing Systems - ARCS 2009, 22nd International Conference, Delft, The Netherlands, March 10-13, 2009. Proceedings, pp. 16-27, 2009, Springer, 978-3-642-00453-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
36 | Tristan Crolard, Emmanuel Polonowski, Pierre Valarcher |
Extending the loop language with higher-order procedural variables. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Comput. Log. ![In: ACM Trans. Comput. Log. 10(4), pp. 26:1-26:37, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Gödel System T, Loop language, higher-order procedures, procedural variables |
36 | Vicente Torres-Carot, A. Perez-Pascual, T. Sansaloni, Javier Valls |
Design and FPGA-Implementation of a High Performance Timing Recovery Loop for Broadband Communications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Signal Process. Syst. ![In: J. Signal Process. Syst. 56(1), pp. 17-23, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Timing recovery, FPGA, Synchronization, SDR, Feedback loop |
36 | Yan Yang, Jinwen Ma |
A Single Loop EM Algorithm for the Mixture of Experts Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISNN (2) ![In: Advances in Neural Networks - ISNN 2009, 6th International Symposium on Neural Networks, ISNN 2009, Wuhan, China, May 26-29, 2009, Proceedings, Part II, pp. 959-968, 2009, Springer, 978-3-642-01509-0. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
The mixture of experts (ME) architecture, The EM algorithm, Gating network, Single loop, Least mean square regression |
36 | Prateek Saxena, Pongsin Poosankam, Stephen McCamant, Dawn Song |
Loop-extended symbolic execution on binary programs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSTA ![In: Proceedings of the Eighteenth International Symposium on Software Testing and Analysis, ISSTA 2009, Chicago, IL, USA, July 19-23, 2009, pp. 225-236, 2009, ACM, 978-1-60558-338-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
loop summaries, vulnerability discovery and diagnosis |
36 | Mounira Bachir, Sid Ahmed Ali Touati, Albert Cohen 0001 |
Post-pass periodic register allocation to minimise loop unrolling degree. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES ![In: Proceedings of the 2008 ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'08), Tucson, AZ, USA, June 12-13, 2008, pp. 141-150, 2008, ACM, 978-1-60558-104-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
embedded code optimisation, periodic register allocation, software pipelining, loop unrolling |
36 | Guojun Ji |
Virtual Enterprise in Closed-Loop Supply Chain and Performance Evaluation Based on Exergoeconomics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CONFENIS (1) ![In: Research and Practical Issues of Enterprise Information Systems II, Volume 1, IFIP TC 8 WG 8.9 International Conference on Research and Practical Issues of Enterprise Information Systems (CONFENIS 2007), October 14-16, 2007, Beijing, China, pp. 135-143, 2007, Springer, 978-0-387-75901-2. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Closed-loop supply chain, Exergoeconomics, Virtual enterprise |
36 | Jiann-Liang Chen, Nong-Kun Chen |
Feedback Closed-Loop Scheduling Discipline for QoS Guarantee in Mobile Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Wirel. Networks ![In: Wirel. Networks 12(2), pp. 223-232, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
highly interactive e-learning system, wireless mobile communications, closed-loop scheduling discipline, feedback control, quality-of-service guarantee |
36 | Ying Hu 0003, Clark W. Barrett, Benjamin Goldberg |
Theory and Algorithms for the Generation and Validation of Speculative Loop Optimizations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SEFM ![In: 2nd International Conference on Software Engineering and Formal Methods (SEFM 2004), 28-30 September 2004, Beijing, China, pp. 281-289, 2004, IEEE Computer Society, 0-7695-2222-X. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Compiler validation, speculative loop optimizations, formal methods, translation validation |
36 | Tao Yu, Zhizhong Tang, Chihong Zhang, Jun Luo |
Control Mechanism for Software Pipelining on Nested Loop. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APDC ![In: Proceedings of the 1997 Advances in Parallel and Distributed Computing Conference (APDC '97), March 19-21, 1997, Shanghai, China, pp. 345-350, 1997, IEEE Computer Society, 0-8186-7876-3. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
ILSP, software pipelining, VLIW, dataflow, nested loop |
36 | Agustín Fernández, José M. Llabería, Miguel Valero-García |
Loop Transformation Using Nonunimodular Matrices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 6(8), pp. 832-840, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
nonunimodular transformations, loop transformations, linear transformations, Iteration space, unimodular transformations, Hermite Normal Form |
35 | Joonseok Park, Pedro C. Diniz |
Partial Data Reuse for Windowing Computations: Performance Modeling for FPGA Implementations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARC ![In: Reconfigurable Computing: Architectures, Tools and Applications, Third International Workshop, ARC 2007, Mangaratiba, Brazil, March 27-29, 2007., pp. 97-109, 2007, Springer, 978-3-540-71430-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
scalar replacement, loop splitting, loop interchange, Field Programmable Gate Arrays (FPGA), Reconfigurable Computing, data reuse |
35 | Yijun Yu, Erik H. D'Hollander |
Non-Uniform Dependences Partitioned by Recurrence Chains. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPP ![In: 33rd International Conference on Parallel Processing (ICPP 2004), 15-18 August 2004, Montreal, Quebec, Canada, pp. 100-107, 2004, IEEE Computer Society, 0-7695-2197-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
non-uniform dependences, recurrence chains, iteration space partitioning, imperfectly nested loop, loop parallelization |
35 | Naraig Manjikian, Tarek S. Abdelrahman |
Fusion of Loops for Parallelism and Locality. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 8(2), pp. 193-209, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
Locality enhancement, data-parallel applications, loop transformations, loop fusion, scalable shared-memory multiprocessors, cache conflicts |
35 | Dirk Olszewski |
Targeted Audio. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Computers in the Human Interaction Loop ![In: Computers in the Human Interaction Loop, pp. 133-141, 2009, Springer, 978-1-84882-053-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
35 | Oliver Brdiczka, James L. Crowley, Jan Curín, Jan Kleindienst |
Situation Modeling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Computers in the Human Interaction Loop ![In: Computers in the Human Interaction Loop, pp. 121-132, 2009, Springer, 978-1-84882-053-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
35 | Gerhard Sutschet |
The CHIL Reference Model Architecture for Multimodal Perceptual Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Computers in the Human Interaction Loop ![In: Computers in the Human Interaction Loop, pp. 291-296, 2009, Springer, 978-1-84882-053-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
35 | Oswald Lanz, Roberto Brunelli, Paul Chippendale, Michael Voit, Rainer Stiefelhagen |
Extracting Interaction Cues: Focus of Attention, Body Pose, and Gestures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Computers in the Human Interaction Loop ![In: Computers in the Human Interaction Loop, pp. 87-93, 2009, Springer, 978-1-84882-053-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
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