Search results for "loop-unrolling"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
206	Jack W. Davidson, Sanjay Jinturkar	Aggressive Loop Unrolling in a Retargetable Optimizing Compiler.	CC	1996	DBLP DOI BibTeX RDF	Code improving transformations, Compiler optimizations, Loop transformations, Loop unrolling
136	Mounira Bachir, Sid Ahmed Ali Touati, Albert Cohen 0001	Post-pass periodic register allocation to minimise loop unrolling degree.	LCTES	2008	DBLP DOI BibTeX RDF	embedded code optimisation, periodic register allocation, software pipelining, loop unrolling
113	Litong Song, Krishna M. Kavi	What can we gain by unfolding loops?	ACM SIGPLAN Notices	2004	DBLP DOI BibTeX RDF	loop peeling, loop quasi invariant code motion, quasi-index variable, quasi-invariant variable, loop unrolling
112	Betul Buyukkurt, Zhi Guo, Walid A. Najjar	Impact of Loop Unrolling on Area, Throughput and Clock Frequency in ROCCC: C to VHDL Compiler for FPGAs.	ARC	2006	DBLP DOI BibTeX RDF
100	Srikanth Kurra, Neeraj Kumar Singh 0004, Preeti Ranjan Panda	The impact of loop unrolling on controller delay in high level synthesis.	DATE	2007	DBLP DOI BibTeX RDF
94	Akira Koseki, Hideaki Komatsu, Yoshiaki Fukazawa	A method for estimating optimal unrolling times for nested loops.	ISPAN	1997	DBLP DOI BibTeX RDF	reuse of data, benchmark tests, parallelization, parallelism, heuristic algorithm, heuristic programming, nested loops, loop unrolling
91	Frank Hannig, Hritam Dutta, Jürgen Teich	Parallelization Approaches for Hardware Accelerators - Loop Unrolling Versus Loop Partitioning.	ARCS	2009	DBLP DOI BibTeX RDF
83	Gayathri Krishnamurthy, Elana D. Granston, Eric Stotzer	Affinity-based cluster assignment for unrolled loops.	ICS	2002	DBLP DOI BibTeX RDF	affinity-based clustering (ABC) algorithms, homogeneous clusters, partitioned register files, software pipelining, loop optimizations, loop scheduling, VLIW architectures, loop unrolling, cluster assignment
81	Litong Song, Krishna M. Kavi, Ron Cytron	An Unfolding-Based Loop Optimization Technique.	SCOPES	2003	DBLP DOI BibTeX RDF
80	Ozana Silvia Dragomir, Todor P. Stefanov, Koen Bertels	Loop unrolling and shifting for reconfigurable architectures.	FPL	2008	DBLP DOI BibTeX RDF
79	Lizy Kurian John, Vinod Reddy, Paul T. Hulina, Lee D. Coraor	A comparative evaluation of software techniques to hide memory latency.	HICSS (1)	1995	DBLP DOI BibTeX RDF	comparative software evaluation, software oriented techniques, superscalar machines, superpipelined machines, software cache prefetching, data fetch request, software controlled prefetching, aggressive prefetching, memory bandwidth requirements, bus traffic, performance, parallel machines, program compilers, processor scheduling, software performance evaluation, software pipelining, pipeline processing, microarchitecture, cache storage, instruction set architecture, memory latency, loop unrolling, static scheduling, conditional branches
78	Michael E. Wolf, Dror E. Maydan, Ding-Kai Chen	Combining Loop Transformations Considering Caches and Scheduling.	MICRO	1996	DBLP DOI BibTeX RDF	cache tiling, fission, loop interchange, outer loop unrolling, fusion, instruction scheduling
72	João M. P. Cardoso, Pedro C. Diniz	Modeling Loop Unrolling: Approaches and Open Issues.	SAMOS	2004	DBLP DOI BibTeX RDF
66	Byoungro So, Mary W. Hall, Pedro C. Diniz	A Compiler Approach to Fast Hardware Design Space Exploration in FPGA-based Systems.	PLDI	2002	DBLP DOI BibTeX RDF	reuse analysis, design space exploration, loop transformations, data dependence analysis
63	Ken Naono, Toshiyuki Imamura	An Evaluation Towards Automatically Tuned Eigensolvers.	LSSC	2005	DBLP DOI BibTeX RDF
62	Shlomo Weiss, James E. Smith 0001	A Study of Scalar Compilation Techniques for Pipelined Supercomputers.	ASPLOS	1987	DBLP DOI BibTeX RDF
59	Sarah Thompson, Alan Mycroft	Bit-level partial evaluation of synchronous circuits.	PEPM	2006	DBLP DOI BibTeX RDF	partial evaluation, loop unrolling, synchronous circuits
59	Hojin Kee, Newton Petersen, Jacob Kornerup, Shuvra S. Bhattacharyya	Systematic generation of FPGA-based FFT implementations.	ICASSP	2008	DBLP DOI BibTeX RDF
53	F. Jesús Sánchez, Antonio González 0001	The Effectiveness of Loop Unrolling for Modulo Scheduling in Clustered VLIW Architectures.	ICPP	2000	DBLP DOI BibTeX RDF
51	Ganesh Lakshminarayana, Kamal S. Khouri, Niraj K. Jha	Wavesched: a novel scheduling technique for control-flow intensive behavioral descriptions.	ICCAD	1997	DBLP DOI BibTeX RDF	control-flow intensive, scheduling, parallelism, pipelining, loop unrolling
51	Doosan Cho, Ravi Ayyagari, Gang-Ryung Uh, Yunheung Paek	Instruction Re-selection for Iterative Modulo Scheduling on High Performance Multi-issue DSPs.	EUC Workshops	2006	DBLP DOI BibTeX RDF
51	François Bodin, François Charot	Loop optimization for horizontal microcoded machines.	ICS	1990	DBLP DOI BibTeX RDF
48	Michel J. Daydé, Iain S. Duff	The RISC BLAS: a blocked implementation of level 3 BLAS for RISC processors.	ACM Trans. Math. Softw.	1999	DBLP DOI BibTeX RDF	matrix-matrix kernels, blocking, loop-unrolling, level 3 BLAS, RISC processors
48	Seongbae Park, SangMin Shim, Soo-Mook Moon	Evaluation of Scheduling Techniques on a SPARC-based VLIW Testbed.	MICRO	1997	DBLP DOI BibTeX RDF	SPARC-based VLIW testbed, VLIW microprocessors, Very Long Instruction Word microprocessors, all-path speculation, gcc-generated optimized SPARC code, high-performance VLIW code, nongreedy enhanced pipeline scheduling, nonspeculative operations, profile-based all-path speculation, restricted speculative loads, scheduling compiler, speculative operations, trace-based speculation, performance, compiler, computer architecture, parallel machines, software pipelining, loop unrolling, renaming, memory disambiguation, copies, scheduling techniques
47	Gennette Gill, John Hansen, Montek Singh	Loop pipelining for high-throughput stream computation using self-timed rings.	ICCAD	2006	DBLP DOI BibTeX RDF
47	Antoine Monsifrot, François Bodin, Rene Quiniou	A Machine Learning Approach to Automatic Production of Compiler Heuristics.	AIMSA	2002	DBLP DOI BibTeX RDF
46	Jae-Jin Lee, Gi-Yong Song	High-Level Synthesis Using SPARK and Systolic Array.	ARC	2006	DBLP DOI BibTeX RDF
45	Pascal Benoit, Lionel Torres, Gilles Sassatelli, Michel Robert, Gaston Cambon	Automatic Task Scheduling / Loop Unrolling using Dedicated RTR Controllers in Coarse Grain Reconfigurable Architectures.	IPDPS	2005	DBLP DOI BibTeX RDF
42	Sumit Gupta, Nikil D. Dutt, Rajesh Gupta 0001, Alexandru Nicolau	Loop Shifting and Compaction for the High-Level Synthesis of Designs with Complex Control Flow.	DATE	2004	DBLP DOI BibTeX RDF
41	Monica Magalhães Pereira, Sílvio R. F. de Araújo, Bruno Cruz de Oliveira, Ivan Saraiva Silva	Using traditional loop unrolling to fit application on a new hybrid reconfigurable architecture.	SAC	2008	DBLP DOI BibTeX RDF	stream-based, optimization, performance, reconfigurable architecture
39	Bertrand A. Maher, Aaron Smith, Doug Burger, Kathryn S. McKinley	Merging Head and Tail Duplication for Convergent Hyperblock Formation.	MICRO	2006	DBLP DOI BibTeX RDF
39	Mark Stephenson, Saman P. Amarasinghe	Predicting Unroll Factors Using Supervised Classification.	CGO	2005	DBLP DOI BibTeX RDF
35	Yi Qian, Steve Carr 0001, Philip H. Sweany	Optimizing Loop Performance for Clustered VLIW Architectures.	IEEE PACT	2002	DBLP DOI BibTeX RDF
35	Sylvain Lelait, Guang R. Gao, Christine Eisenbeis	A New Fast Algorithm for Optimal Register Allocation in Modulo Scheduled Loops.	CC	1998	DBLP DOI BibTeX RDF
35	Catherine H. Gebotys, Robert J. Gebotys	Power Minimization in Heterogeneous Processing.	HICSS (1)	1996	DBLP DOI BibTeX RDF
32	Narasinga Rao Miniskar, Pankaj Shailendra Gode, Soma Kohli, Donghoon Yoo	Function inlining and loop unrolling for loop acceleration in reconfigurable processors.	CASES	2012	DBLP DOI BibTeX RDF
32	Paul Lokuciejewski, Peter Marwedel	Combining Worst-Case Timing Models, Loop Unrolling, and Static Loop Analysis for WCET Minimization.	ECRTS	2009	DBLP DOI BibTeX RDF	WCET minimization, WCET-driven optimizations, High-Level Optimizations, compiler, WCET
32	Litong Song, Yuhua Zhang, Krishna M. Kavi	Loop Transformation Techniques To Aid In Loop Unrolling and Multithreading.	PDCS	2003	DBLP BibTeX RDF
32	Like Yan, Gang Wang, Tianzhou Chen	The input-aware dynamic adaptation of area and performance for reconfigurable accelerator.	FPGA	2009	DBLP DOI BibTeX RDF	dynamic adaption, reconfigurable system, loop unrolling, loop accelerator
32	Nachiket Kapre, André DeHon	Accelerating SPICE Model-Evaluation using FPGAs.	FCCM	2009	DBLP DOI BibTeX RDF	Analog Circuit Simulator, VLIW Scheduling, Floating-Point, Spice, Loop Unrolling, Spatial Computation
32	Peter Gottschling, Andrew Lumsdaine	Integrating semantics and compilation: using c++ concepts to develop robust and efficient reusable libraries.	GPCE	2008	DBLP DOI BibTeX RDF	semantic verification, optimization, c++, concepts, loop unrolling, semantic properties
32	Jeremy R. Johnson, Werner Krandick, Anatole D. Ruslanov	Architecture-aware classical Taylor shift by 1.	ISSAC	2005	DBLP DOI BibTeX RDF	ILP scheduling, Taylor shift, delayed carry propagation, multiprecision arithmetic, register tiling, high-performance computing, code generation, memory hierarchy, polynomials, performance tuning, loop unrolling
32	Mikio Takeuchi, Hideaki Komatsu, Toshio Nakatani	A new speculation technique to optimize floating-point performance while preserving bit-by-bit reproducibility.	ICS	2003	DBLP DOI BibTeX RDF	bit-by-bit reproducibility, floating-point speculation, fused multiply-add, reassociation, striding, Java, prefetching, accuracy, instruction-level parallelism, software pipelining, just-in-time compiler, loop unrolling, privatization, IA-64, IEEE 754
32	Daniel M. Lavery, Wen-mei W. Hwu	Unrolling-based optimizations for modulo scheduling.	MICRO	1995	DBLP DOI BibTeX RDF	optimization, instruction-level parallelism, software pipelining, modulo scheduling, loop unrolling
31	Yosi Ben-Asher, Nadav Rotem	The effect of unrolling and inlining for Python bytecode optimizations.	SYSTOR	2009	DBLP DOI BibTeX RDF	optimizations, Python, bytecode, dynamic languages
31	JongSoo Park, Sung-Boem Park, James D. Balfour, David Black-Schaffer, Christos Kozyrakis, William J. Dally	Register pointer architecture for efficient embedded processors.	DATE	2007	DBLP DOI BibTeX RDF
31	Yanwei Niu, Ziang Hu, Kenneth E. Barner, Guang R. Gao	Performance Modelling and Optimization of Memory Access on Cellular Computer Architecture Cyclops64.	NPC	2005	DBLP DOI BibTeX RDF
31	Ganesh Lakshminarayana, Niraj K. Jha	FACT: a framework for applying throughput and power optimizing transformations to control-flow-intensive behavioral descriptions.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
31	Ganesh Lakshminarayana, Niraj K. Jha	FACT: A Framework for the Application of Throughput and Power Optimizing Transformations to Control-Flow Intensive Behavioral Descriptions.	DAC	1998	DBLP DOI BibTeX RDF	high-level synthesis, telecommunication
31	Min Zhao 0009, Bruce R. Childers, Mary Lou Soffa	Predicting the impact of optimizations for embedded systems.	LCTES	2003	DBLP DOI BibTeX RDF	code models, embedded systems, prediction, optimizing compilers, loop optimizations, resource models, optimization models
31	Gang-Ryung Uh, Yuhong Wang, David B. Whalley, Sanjay Jinturkar, Chris Burns, Vincent Cao	Techniques for Effectively Exploiting a Zero Overhead Loop Buffer.	CC	2000	DBLP DOI BibTeX RDF
31	Gang-Ryung Uh, Yuhong Wang, David B. Whalley, Sanjay Jinturkar, Chris Burns, Vincent Cao	Effective Exploitation of a Zero Overhead Loop Buffer.	Workshop on Languages, Compilers, and Tools for Embedded Systems	1999	DBLP DOI BibTeX RDF
27	Suhyun Kim, Soo-Mook Moon	Rotating Register Allocation for Enhanced Pipeline Scheduling.	PACT	2007	DBLP DOI BibTeX RDF
27	Nahid Emad, Olfa Hamdi-Larbi, Z. Mahjoub	On sparse matrix-vector product optimization.	AICCSA	2005	DBLP DOI BibTeX RDF
27	F. Jesús Sánchez, Antonio González 0001	Instruction Scheduling for Clustered VLIW Architectures.	ISSS	2000	DBLP DOI BibTeX RDF
27	Sudipta Kundu, Zachary Tatlock, Sorin Lerner	Proving optimizations correct using parameterized program equivalence.	PLDI	2009	DBLP DOI BibTeX RDF	compiler optimization, correctness, translation validation
27	Joonseok Park, Pedro C. Diniz	Partial Data Reuse for Windowing Computations: Performance Modeling for FPGA Implementations.	ARC	2007	DBLP DOI BibTeX RDF	scalar replacement, loop splitting, loop interchange, Field Programmable Gate Arrays (FPGA), Reconfigurable Computing, data reuse
26	Bertrand Meyer 0001	Loop unrolling (for test coverage): formal definition.	CoRR	2024	DBLP DOI BibTeX RDF
26	Alnis Murtovi, Giorgis Georgakoudis, Konstantinos Parasyris, Chunhua Liao, Ignacio Laguna, Bernhard Steffen	Enhancing Performance Through Control-Flow Unmerging and Loop Unrolling on GPUs.	CGO	2024	DBLP DOI BibTeX RDF
26	Francisco J. Soulignac, Pablo Terlisky	Loop unrolling of UCA models: distance labeling.	CoRR	2022	DBLP BibTeX RDF
26	Ruiki Kobayashi, Shogo Muramatsu, Shunsuke Ono	Proximal Gradient-Based Loop Unrolling with Interscale Thresholding.	APSIPA ASC	2021	DBLP BibTeX RDF
26	G. Georgiou, Georgios Theodoridis	Studying the impacts of loop unrolling and pipeline in the FPGA design of the Simon and RoadRunneR lightweght ciphers.	MOCAST	2021	DBLP DOI BibTeX RDF
26	Xiaowei Guo, Chao Li, Wei Li, Yu Cao, Yi Liu, Ran Zhao, Sen Zhang, Canqun Yang	Improving performance for simulating complex fluids on massively parallel computers by component loop-unrolling and communication hiding.	HPCC/DSS/SmartCity	2020	DBLP DOI BibTeX RDF
26	Rodrigo C. O. Rocha, Vasileios Porpodas, Pavlos Petoumenos, Luís F. W. Góes, Zheng Wang 0001, Murray Cole, Hugh Leather	Vectorization-aware loop unrolling with seed forwarding.	CC	2020	DBLP DOI BibTeX RDF
26	Naveen Kumar Dumpala, Shivukumar B. Patil, Daniel E. Holcomb, Russell Tessier	Loop Unrolling for Energy Efficiency in Low-Cost Field-Programmable Gate Arrays.	ACM Trans. Reconfigurable Technol. Syst.	2019	DBLP DOI BibTeX RDF
26	Asma Balamane, Zina Taklit	Using Deep Neural Networks for Estimating Loop Unrolling Factor.	CoRR	2019	DBLP BibTeX RDF
26	Scott Young, Alexandrea Demmings, Nasrin Eshraghi Ivari, Jean-Philippe Legault, Kenneth B. Kent	Verilog Loop Unrolling, Module Generation, Part-Select and Arithmetic Right Shift Support in Odin II.	RSP	2019	DBLP DOI BibTeX RDF
26	Marcelino Rodriguez-Cancio, Benoît Combemale, Benoit Baudry	Approximate loop unrolling.	CF	2019	DBLP DOI BibTeX RDF
26	Qiyuan Liu 0001, Alexander Edward, Dadian Zhou, José Silva-Martínez	A Continuous-Time MASH 1-1-1 Delta-Sigma Modulator With FIR DAC and Encoder-Embedded Loop-Unrolling Quantizer in 40-nm CMOS.	IEEE Trans. Very Large Scale Integr. Syst.	2018	DBLP DOI BibTeX RDF
26	David Leopoldseder, Roland Schatz, Lukas Stadler, Manuel Rigger, Thomas Würthinger, Hanspeter Mössenböck	Fast-path loop unrolling of non-counted loops to enable subsequent compiler optimizations.	ManLang	2018	DBLP DOI BibTeX RDF
26	Lukas Johannes Jung, Christian Hochberger	Lookahead Memory Prefetching for CGRAs Using Partial Loop Unrolling.	ARC	2018	DBLP DOI BibTeX RDF
26	Karim Soliman, Marwa El Shenawy, Ahmed Abou El Farag	Loop unrolling effect on parallel code optimization.	ICFNDS	2018	DBLP DOI BibTeX RDF
26	Georgios Zacharopoulos, Andrea Barbon, Giovanni Ansaloni, Laura Pozzi	Machine Learning Approach for Loop Unrolling Factor Prediction in High Level Synthesis.	HPCS	2018	DBLP DOI BibTeX RDF
26	Kunal Banerjee 0001, Ramanuj Chouksey, Chandan Karfa, Pankaj Kumar Kalita	Automatic detection of inverse operations while avoiding loop unrolling.	ICSE (Companion Volume)	2018	DBLP DOI BibTeX RDF
26	Yi-Xuan Lu, Jih-Ching Chiu, Shu-Jung Chao, Yong-Bin Ye	Design of Instruction Analyzer with Semantic-Based Loop Unrolling Mechanism in the Hyperscalar Architecture.	ICS	2018	DBLP DOI BibTeX RDF
26	Anirban Sengupta, Saumya Bhadauria, Saraju P. Mohanty	TL-HLS: Methodology for Low Cost Hardware Trojan Security Aware Scheduling With Optimal Loop Unrolling Factor During High Level Synthesis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2017	DBLP DOI BibTeX RDF
26	Naveen Kumar Dumpala, Shivukumar B. Patil, Daniel E. Holcomb, Russell Tessier	Energy Efficient Loop Unrolling for Low-Cost FPGAs.	FCCM	2017	DBLP DOI BibTeX RDF
26	Wei Gao 0011, Rongcai Zhao, Haining Yu, Qinghua Zhang	循环展开技术在向量程序中的应用 (Loop Unrolling in Vectorized Programs).	计算机科学	2016	DBLP DOI BibTeX RDF
26	David Sanchez-Charles, Marc Solé, Josep Carmona 0001, Victor Muntés-Mulero	Improving Process Model Precision by Loop Unrolling.	SIMPDA	2016	DBLP BibTeX RDF
26	Lukasz Domagala, Duco van Amstel, Fabrice Rastello, P. Sadayappan	Register allocation and promotion through combined instruction scheduling and loop unrolling.	CC	2016	DBLP DOI BibTeX RDF
26	Sumanta Pyne, Ajit Pal	Runtime Leakage Power Reduction Using Loop Unrolling and Fine Grained Power Gating.	J. Low Power Electron.	2015	DBLP DOI BibTeX RDF
26	Sumanta Pyne, Ajit Pal	Energy Efficient Array Computations Using Loop Unrolling with Partial Gray Code Sequence.	J. Low Power Electron.	2015	DBLP DOI BibTeX RDF
26	Alessandro Cilardo, Luca Gallo	Interplay of loop unrolling and multidimensional memory partitioning in HLS.	DATE	2015	DBLP BibTeX RDF
26	Pallabi Sarkar, Anirban Sengupta, Mrinal Kanti Naskar	GA driven integrated exploration of loop unrolling factor and datapath for optimal scheduling of CDFGs during high level synthesis.	CCECE	2015	DBLP DOI BibTeX RDF
26	Rajitha Navarathna, Swarnalatha Radhakrishnan, Roshan G. Ragel	Loop Unrolling in Multi-pipeline ASIP Design.	CoRR	2014	DBLP BibTeX RDF
26	Anirban Sengupta, Vipul Kumar Mishra	Swarm Intelligence Driven Simultaneous Adaptive Exploration of Datapath and Loop Unrolling Factor during Area-Performance Tradeoff.	ISVLSI	2014	DBLP DOI BibTeX RDF
26	Goran Velkoski, Marjan Gusev, Sasko Ristov	The performance impact analysis of loop unrolling.	MIPRO	2014	DBLP DOI BibTeX RDF
26	Jiasen Huang, Junyan Ren, Jun Xu, Yuanyuan Wang 0001	General expression based inner loop unrolling scheme for TV-GD algorithm adopted in photoacoustic imaging.	BioCAS	2014	DBLP DOI BibTeX RDF
26	Sumanta Pyne, Ajit Pal	Loop unrolling with fine grained power gating for runtime leakage power reduction.	VDAT	2014	DBLP DOI BibTeX RDF
26	Meisam Booshehri, Abbas Malekpour, Peter Luksch 0001	An Improving Method for Loop Unrolling.	CoRR	2013	DBLP BibTeX RDF
26	Sumanta Pyne, Ajit Pal	Energy Efficient Array Initialization Using Loop Unrolling with Partial Gray Code Sequence.	VDAT	2013	DBLP DOI BibTeX RDF
26	Johann Steinbrecher, Weijia Shang	On Optimizing the Longest Common Subsequence Problem by Loop Unrolling Along Wavefronts.	PDP	2012	DBLP DOI BibTeX RDF
26	Mounira Bachir, Frederic Brault, Sid Ahmed Ali Touati, Albert Cohen 0001	Loop unrolling minimisation in the presence of multiple register types: A viable alternative to modulo variable expansion.	HPCS	2011	DBLP DOI BibTeX RDF
26	Vladimír Guzma, Teemu Pitkänen, Jarmo Takala	Effects of loop unrolling and use of instruction buffer on processor energy consumption.	SoC	2011	DBLP DOI BibTeX RDF
26	Yosi Ben-Asher, Jawad Haj-Yihia	Computing the correct Increment of Induction Pointers with application to loop unrolling.	J. Syst. Archit.	2010	DBLP DOI BibTeX RDF
26	Giridhar Sreenivasa Murthy, Mahesh Ravishankar, Muthu Manikandan Baskaran, Ponnuswamy Sadayappan	Optimal loop unrolling for GPGPU programs.	IPDPS	2010	DBLP DOI BibTeX RDF
26	Ozana Silvia Dragomir, Todor P. Stefanov, Koen Bertels	Optimal Loop Unrolling and Shifting for Reconfigurable Architectures.	ACM Trans. Reconfigurable Technol. Syst.	2009	DBLP DOI BibTeX RDF
26	Mounira Bachir, David Gregg, Sid Ahmed Ali Touati	Using the Meeting Graph Framework to Minimise Kernel Loop Unrolling for Scheduled Loops.	LCPC	2009	DBLP DOI BibTeX RDF
26	Nicholas Nethercote, Doug Burger, Kathryn S. McKinley	Convergent Compilation Applied to Loop Unrolling.	Trans. High Perform. Embed. Archit. Compil.	2007	DBLP DOI BibTeX RDF
26	Karine Heydemann, François Bodin, Peter M. W. Knijnenburg, Laurent Morin	UFS: a global trade-off strategy for loop unrolling for VLIW architectures.	Concurr. Comput. Pract. Exp.	2006	DBLP DOI BibTeX RDF