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Searching for phrase low-vt (changed automatically) with no syntactic query expansion in all metadata.

Publication years (Num. hits)
1995-2005 (16) 2006-2009 (15) 2010-2015 (3)
Publication types (Num. hits)
article(6) inproceedings(28)
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Found 34 publication records. Showing 34 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
15Mihir R. Choudhury, Masoud Rostami, Kartik Mohanram Dominant critical gate identification for power and yield optimization in logic circuits. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2010 DBLP  DOI  BibTeX  RDF low-vt, process variations, yield
8Vivek De Leakage-tolerant design techniques for high performance processors. Search on Bibsonomy ISPD The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
8Meeta Srivastav, S. S. S. P. Rao, Himanshu Bhatnagar Power Reduction Technique Using Multi-vt Libraries. Search on Bibsonomy IWSOC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF High-Vt, Low-Vt, DFT, ASIC, Leakage power, DSM
7Khawar Sarfraz, Mansun Chan A 65nm 3.2GHz 44.2mW Low-Vt register file with robust low-capacitance dynamic local bitlines. Search on Bibsonomy ESSCIRC The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
7Seyfi S. Bazarjani, W. Martin Snelgrove Low Voltage SC Circuit Design with Low-Vt MOSFETs. Search on Bibsonomy ISCAS The full citation details ... 1995 DBLP  DOI  BibTeX  RDF
4Jinseob Jeong, Seungwhun Paik, Youngsoo Shin Statistical mixed Vt allocation of body-biased circuits for reduced leakage variation. Search on Bibsonomy ASP-DAC The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
4Sherif A. Tawfik, Volkan Kursun Work-function engineering for reduced power and higher integration density: An alternative to sizing for stability in FinFET memory circuits. Search on Bibsonomy ISCAS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
4Jaehyun Kim, Youngsoo Shin Minimizing leakage power in sequential circuits by using mixed Vt flip-flops. Search on Bibsonomy ICCAD The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
4Maryam Ashouei, Abhijit Chatterjee, Adit D. Singh, Vivek De A Dual-Vt Layout Approach for Statistical Leakage Variability Minimization in Nanometer CMOS. Search on Bibsonomy ICCD The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
3Satoru Akiyama, Riichiro Takemura, Tomonori Sekiguchi, Akira Kotabe, Kiyoo Itoh 0001 A Low-Vt Small-Offset Gated-Preamplifier for Sub-1-V DRAM Mid-Point Sensing. Search on Bibsonomy IEICE Trans. Electron. The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
3Hagen Marien, Michiel Steyaert, Nick A. J. M. van Aerle, Paul Heremans A mixed-signal organic 1kHz comparator with low VT sensitivity on flexible plastic substrate. Search on Bibsonomy ESSCIRC The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
3Satoru Akiyama, Tomonori Sekiguchi, Riichiro Takemura, Akira Kotabe, Kiyoo Itoh 0001 Low-Vt small-offset gated preamplifier for sub-1V gigabit DRAM arrays. Search on Bibsonomy ISSCC The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
3Thomas Baumann, Doris Schmitt-Landsiedel, Christian Pacha Architectural assessment of design techniques to improve speed and robustness in embedded microprocessors. Search on Bibsonomy DAC The full citation details ... 2009 DBLP  DOI  BibTeX  RDF variability-aware design, robustness, micro-architecture
3Amit Agarwal 0001, Kunhyuk Kang, Swarup Bhunia, James D. Gallagher, Kaushik Roy 0001 Device-Aware Yield-Centric Dual-Vt Design Under Parameter Variations in Nanoscale Technologies. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
3Lin Yuan, Gang Qu 0001 Simultaneous input vector selection and dual threshold voltage assignment for static leakage minimization. Search on Bibsonomy ICCAD The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
3Amit Agarwal 0001, Kunhyuk Kang, Swarup Bhunia, James D. Gallagher, Kaushik Roy 0001 Effectiveness of low power dual-Vt designs in nano-scale technologies under process parameter variations. Search on Bibsonomy ISLPED The full citation details ... 2005 DBLP  DOI  BibTeX  RDF process variation, yield, leakage, dual-Vt, metal gate
3Arkadiy Morgenshtein, Israel Cidon, Ran Ginosar, Avinoam Kolodny Low-leakage repeaters for NoC interconnects. Search on Bibsonomy ISCAS (1) The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
3Qi Wang, Sarma B. K. Vrudhula Algorithms for minimizing standby power in deep submicrometer, dual-Vt CMOS circuits. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
3Muhammad E. S. Elrabaa, Mohamed I. Elmasry Split-Gate Logic circuits for multi-threshold technologies. Search on Bibsonomy ISCAS (4) The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
3S. Karthikeyan, A. Tammineedi, C. Boecker, Edward K. F. Lee A 1 V front-end interface for switched-op amp circuits. Search on Bibsonomy ISCAS (2) The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
3Hendrawan Soeleman, Dinesh Somasekhar, Kaushik Roy 0001 IDD Waveforms Analysis for Testing of Domino and Low Voltage Static CMOS Circuits. Search on Bibsonomy Great Lakes Symposium on VLSI The full citation details ... 1998 DBLP  DOI  BibTeX  RDF IDD Waveforms Analysis, Testing
3Hiok-Tiaq Ng, David J. Allstot CMOS current steering logic for low-voltage mixed-signal integrated circuits. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
1David Bol, Dina Kamel, Denis Flandre, Jean-Didier Legat Nanometer MOSFET effects on the minimum-energy point of 45nm subthreshold logic. Search on Bibsonomy ISLPED The full citation details ... 2009 DBLP  DOI  BibTeX  RDF short-channel effects, subthreshold logic, variability, cmos digital integrated circuits, ultra-low power, gate leakage
1Rouwaida Kanj, Rajiv V. Joshi, Jente B. Kuang, J. Kim, Mesut Meterelliyoz, William R. Reohr, Sani R. Nassif, Kevin J. Nowka Statistical yield analysis of silicon-on-insulator embedded DRAM. Search on Bibsonomy ISQED The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
1Sandeep Gupta, Jaya Singh, Abhijit Roy A Novel Cell-Based Heuristic Method for Leakage Reduction in Multi-Million Gate VLSI Designs. Search on Bibsonomy ISQED The full citation details ... 2008 DBLP  DOI  BibTeX  RDF Dual-Vt Technology, Cell-Based Approach, Cell-swapping, Leakage Power
1Mindaugas Drazdziulis, Per Larsson-Edefors, Lars J. Svensson Overdrive Power-Gating Techniques for Total Power Minimization. Search on Bibsonomy ISVLSI The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
1Jintae Kim, Ritesh Jhaveri, Jason Woo, Chih-Kong Ken Yang Device-circuit co-optimization for mixed-mode circuit design via geometric programming. Search on Bibsonomy ICCAD The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
1Sorin P. Voinigescu, Sean T. Nicolson, Mehdi Khanpour, Keith K. W. Tang, Kenneth H. K. Yau, N. Seyedfathi, A. Timonov, A. Nachman, George V. Eleftheriades, Peter Schvan, Ming-Ta Yang CMOS SOCs at 100 GHz: System Architectures, Device Characterization, and IC Design Examples. Search on Bibsonomy ISCAS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
1Yibin Ye, Muhammad M. Khellah, Dinesh Somasekhar, Vivek De Evaluation of differential vs. single-ended sensing and asymmetric cells in 90 nm logic technology for on-chip caches. Search on Bibsonomy ISCAS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
1Saumil Shah, Kanak Agarwal, Dennis Sylvester A New Threshold Voltage Assignment Scheme for Runtime Leakage Reduction in On-Chip Repeaters. Search on Bibsonomy ICCD The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
1Fatih Hamzaoglu, Yibin Ye, Ali Keshavarzi, Kevin Zhang 0001, Siva G. Narendra, Shekhar Borkar, Mircea R. Stan, Vivek De Analysis of dual-VT SRAM cells with full-swing single-ended bit line sensing for on-chip cache. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
1Mahesh Ketkar, Sachin S. Sapatnekar Standby power optimization via transistor sizing and dual threshold voltage assignment. Search on Bibsonomy ICCAD The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
1Debasis Samanta, Ajit Pal Optimal Dual -VT Assignment for Low-Voltage Energy-Constrained CMOS Circuits. Search on Bibsonomy ASP-DAC/VLSI Design The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
1Ali Keshavarzi, Kaushik Roy 0001, Charles F. Hawkins Intrinsic leakage in deep submicron CMOS ICs-measurement-based test solutions. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
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