Search results for "macro-models"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
44	Qing Wu 0002, Qinru Qiu, Massoud Pedram, Chih-Shun Ding	Cycle-accurate macro-models for RT-level power analysis.	IEEE Trans. Very Large Scale Integr. Syst.	1998	DBLP DOI BibTeX RDF
43	Nachiketh R. Potlapally, Michael S. Hsiao, Anand Raghunathan, Ganesh Lakshminarayana, Srimat T. Chakradhar	Accurate Power Macro-modeling Techniques for Complex RTL Circuits.	VLSI Design	2001	DBLP DOI BibTeX RDF
38	Tat Kee Tan, Anand Raghunathan, Niraj K. Jha	Embedded Operating System Energy Analysis and Macro-Modeling.	ICCD	2002	DBLP DOI BibTeX RDF
35	Basab Datta, Wayne P. Burleson	Circuit-level NBTI macro-models for collaborative reliability monitoring.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	macro-models, on-chip sensors, calibration, NBTI
34	Yulei Weng, Alex Doboli	Digital cell macro-model with regular substrate template and EKV based MOSFET model.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF
31	Tianyi Jiang, Xiaoyong Tang, Prithviraj Banerjee	Macro-models for high level area and power estimation on FPGAs.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	model, FPGA, high-level synthesis, power estimation, RTL, area estimation
29	Srinivas Bodapati, Farid N. Najm	High-level current macro model for logic blocks.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
29	Yuanzhong (Paul) Zhou, Duane Connerney, Ronald Carroll, Timwah Luk	Modeling MOS Snapback for Circuit-Level ESD Simulation Using BSIM3 and VBIC Models.	ISQED	2005	DBLP DOI BibTeX RDF
25	Sudeep Pasricha, Young-Hwan Park, Fadi J. Kurdahi, Nikil D. Dutt	System-level power-performance trade-offs in bus matrix communication architecture synthesis.	CODES+ISSS	2006	DBLP DOI BibTeX RDF	bus matrix synthesis, system-on-chip, power estimation, communication architectures, power-performance trade-offs
23	Ruiming Chen, Hai Zhou 0001	Timing macro-modeling of IP blocks with crosstalk.	ICCAD	2004	DBLP DOI BibTeX RDF
23	Yi-Min Jiang, Han Young Koh, Kwang-Ting Cheng	HRM - A Hierarchical Simulator for Full-Chip Power Network Reliability Analysis.	ISQED	2001	DBLP DOI BibTeX RDF
18	Yoni Aizik, Gila Kamhi, Yael Zbar, Hadas Ronen, Muhammad Abozaed	Power-Aware Design via Micro-architectural Link to Implementation.	PATMOS	2008	DBLP DOI BibTeX RDF
18	Anuradha Agarwal, Glenn Wolfe, Ranga Vemuri	Accuracy driven performance macromodeling of feasible regions during synthesis of analog circuits.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	performance modeling, circuit sizing, analog synthesis
17	Frank Dignum, Virginia Dignum, Catholijn M. Jonker	Towards Agents for Policy Making.	MABS	2008	DBLP DOI BibTeX RDF
16	Shrirang M. Yardi, Michael S. Hsiao, Thomas L. Martin, Dong S. Ha 0001	Quality-Driven Proactive Computation Elimination for Power-Aware Multimedia Processing.	DATE	2005	DBLP DOI BibTeX RDF
16	Yunsi Fei, Lin Zhong 0001, Niraj K. Jha	An Energy-Aware Framework for Coordinated Dynamic Software Management in Mobile Computers.	MASCOTS	2004	DBLP DOI BibTeX RDF
16	Malcolm Slaney, Jayashree Subrahmonia, Paul P. Maglio	Modeling Multitasking Users.	User Modeling	2003	DBLP DOI BibTeX RDF
16	Brian W. Amick, Claude R. Gauthier, Dean Liu	Macro-modeling concepts for the chip electrical interface.	DAC	2002	DBLP DOI BibTeX RDF	VLSI power distribution, analog and I/O power delivery, high speed microprocessor design, inductance
14	Stephan Gärttner, Peter Frolkovic, Peter Knabner, Nadja Ray	Efficiency of Micro-Macro Models for Reactive Two-Mineral Systems.	Multiscale Model. Simul.	2022	DBLP DOI BibTeX RDF
14	Jonathan Krook, Mladen Cicic, Karl Henrik Johansson	Learning Micro-Macro Models for Traffic Control Using Microscopic Data.	ECC	2022	DBLP DOI BibTeX RDF
14	Xuelian Bao, Chun Liu 0009, Yiwei Wang	On a deterministic particle-FEM discretization to micro-macro models of dilute polymeric fluids.	CoRR	2021	DBLP BibTeX RDF
14	Cinzia Bisi, Giampiero Chiaselotti, Davide Ciucci, Tommaso Gentile, Federico G. Infusino	Micro and macro models of granular computing induced by the indiscernibility relation.	Inf. Sci.	2017	DBLP DOI BibTeX RDF
14	Debjit Sinha, Vladimir Zolotov, Jin Hu, Sheshashayee K. Raghunathan, Adil Bhanji, Christine M. Casey	Generation and use of statistical timing macro-models considering slew and load variability.	ICCAD	2016	DBLP DOI BibTeX RDF
14	Debjit Sinha, Vladimir Zolotov, Eric Fluhr, Michael H. Wood, Jeffrey Ritzinger, Natesan Venkateswaran, Stephen Shuma	Sharing and Re-use of Statistical Timing Macro-Models across Multiple Voltage Domains.	VLSID	2016	DBLP DOI BibTeX RDF
14	Maria Letizia Bertotti, Giovanni Modanese	Micro to macro models for income distribution in the absence and in the presence of tax evasion.	Appl. Math. Comput.	2014	DBLP DOI BibTeX RDF
14	Ata Zadehgol	Probabilistic finite-difference time-domain simulations using stochastic electromagnetic macro-models		2011	RDF
14	Charles Thangaraj, Tom Chen 0001	Early Design Phase Power Performance Trade-Offs Using In-Situ Macro Models.	DELTA	2008	DBLP DOI BibTeX RDF	pareto-front, What-if analysis, Power-performance trade-off
14	Tianyi Jiang, Xiaoyong Tang, Prith Banerjee	Macro-models for high-level area and power estimation on FPGAs.	Int. J. Simul. Process. Model.	2006	DBLP DOI BibTeX RDF
14	Jinwen Xi, Peixin Zhong	Fast Energy Estimation of Multi-processor System-on-Chip with Energy Macro-Models for Embedded Microprocessors.	MSV	2005	DBLP BibTeX RDF
14	Srinivas Bodapati	Bottom-Up High -Level Current Macro-Models for Logic Blocks		2003	RDF
14	Subodh Gupta, Farid N. Najm	Power macro-models for DSP blocks with application to high-level synthesis.	ISLPED	1999	DBLP DOI BibTeX RDF
14	Qing Wu 0002, Chih-Shun Ding, Cheng-Ta Hsieh, Massoud Pedram	Statistical design of macro-models for RT-level power evaluation.	ASP-DAC	1997	DBLP DOI BibTeX RDF
14	Qinru Qiu, Qing Wu 0002, Massoud Pedram, Chih-Shun Ding	Cycle-accurate macro-models for RT-level power analysis.	ISLPED	1997	DBLP DOI BibTeX RDF
10	Michael Eiermann, Walter Stechele	Novel modeling techniques for RTL power estimation.	ISLPED	2002	DBLP DOI BibTeX RDF	RTL macromodels, low power, power estimation, power modeling
9	Charles Thangaraj, Tom Chen 0001	Design target exploration for meeting time-to-market using pareto analysis.	ISCAS	2008	DBLP DOI BibTeX RDF
9	Andrea Bona, Vittorio Zaccaria, Roberto Zafalon	Low Effort, High Accuracy Network-on-Chip Power Macro Modeling.	PATMOS	2004	DBLP DOI BibTeX RDF	Network-on-Chip power analysis, communication based low power design, system-level energy optimization
9	Ying Liu, Lawrence T. Pileggi, Andrzej J. Strojwas	ftd: An Exact Frequency to Time Domain Conversion for Reduced Order RLC Interconnect Models.	DAC	1998	DBLP DOI BibTeX RDF	transceiver, spread spectrum communication, RF CMOS, digital radio, ISM frequency band
8	Markus Bühler, Jürgen Koehl, Jeanne Bickford, Jason Hibbeler, Ulf Schlichtmann, Ralf Sommer, Michael Pronath, Andreas Ripp	DFM/DFY design for manufacturability and yield - influence of process variations in digital, analog and mixed-signal circuit design.	DATE	2006	DBLP DOI BibTeX RDF
8	Mohamed El-Nozahi, Yehia Massoud	An integrated circuit/behavioral simulation framework for continuous-time sigma-delta ADCs.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	macro-modeling, simulation, sigma-delta
8	B. Haddadin, Min Ma, T. S. Roseanu, Roni Khazaka	Efficient Macromodel for Interconnects Excited by Incident Fields.	CCECE	2006	DBLP DOI BibTeX RDF
8	Lin Zhong 0001, Srivaths Ravi 0001, Anand Raghunathan, Niraj K. Jha	Power estimation for cycle-accurate functional descriptions of hardware.	ICCAD	2004	DBLP DOI BibTeX RDF
8	Tat Kee Tan, Anand Raghunathan, Niraj K. Jha	Software Architectural Transformations: A New Approach to Low Energy Embedded Software.	DATE	2003	DBLP DOI BibTeX RDF
8	Christoph Wasshuber	Single-Electronics - How It Works. How It's Used. How It's Simulated (invited).	ISQED	2002	DBLP DOI BibTeX RDF
8	Tamal Mukherjee, Gary K. Fedder	Structured Design of Microelectromechanical Systems.	DAC	1997	DBLP DOI BibTeX RDF
8	Bernhard Steffen, Andreas Claßen, Marion Klein, Jens Knoop, Tiziana Margaria	The Fixpoint-Analysis Machine.	CONCUR	1995	DBLP DOI BibTeX RDF