Search results for "misprediction"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
120	Amit Golander, Shlomo Weiss	Hiding the misprediction penalty of a resource-efficient high-performance processor.	ACM Trans. Archit. Code Optim.	2008	DBLP DOI BibTeX RDF	misprediction, Checkpoints, out-of-order execution, scalable architecture, rollback
120	Peng Zhou, Soner Önder, Steve Carr 0001	Fast branch misprediction recovery in out-of-order superscalar processors.	ICS	2005	DBLP DOI BibTeX RDF	processor state, checkpoint, recovery, branch misprediction
105	James O. Bondi, Ashwini K. Nanda, Simonjit Dutta	Integrating a Misprediction Recovery Cache (MRC) into a Superscalar Pipeline.	MICRO	1996	DBLP DOI BibTeX RDF	branch target buffer technology, deep pipelines, misprediction recovery cache integration, performance loss, residual misprediction penalty, superscalar pipeline, microprocessor chips, microprocessor designs, CISC, multiple instructions
95	Enrique F. Torres, Pablo Ibáñez, Víctor Viñals, José María Llabería	Counteracting Bank Misprediction in Sliced First-Level Caches.	Euro-Par	2003	DBLP DOI BibTeX RDF
92	Ahmed S. Al-Zawawi, Vimal K. Reddy, Eric Rotenberg, Haitham Akkary	Transparent control independence (TCI).	ISCA	2007	DBLP DOI BibTeX RDF	control independence, selective re-execution, selective recovery, checkpoints, branch prediction, speculation
81	Amit Gandhi, Haitham Akkary, Srikanth T. Srinivasan	Reducing Branch Misprediction Penalty via Selective Branch Recovery.	HPCA	2004	DBLP DOI BibTeX RDF
78	Kenneth A. Ross	Selection conditions in main memory.	ACM Trans. Database Syst.	2004	DBLP DOI BibTeX RDF	Branch misprediction
68	Chang-Ching Yeh, Kuei-Chung Chang, Tien-Fu Chen, Chingwei Yeh	Reducing Branch Misprediction Penalties Via Adaptive Pipeline Scaling.	HiPEAC	2007	DBLP DOI BibTeX RDF
68	Ching-Long Su, Alvin M. Despain	Minimizing branch misprediction penalties for superpipelined processors.	MICRO	1994	DBLP DOI BibTeX RDF
65	Juan L. Aragón, José González 0002, Antonio González 0001, James E. Smith 0001	Dual path instruction processing.	ICS	2002	DBLP DOI BibTeX RDF	branch misprediction penalty, dual path processing, pre-scheduling, confidence estimation
55	Resit Sendag, Joshua J. Yi, Peng-fei Chuang	Branch Misprediction Prediction: Complementary Branch Predictors.	IEEE Comput. Archit. Lett.	2007	DBLP DOI BibTeX RDF
55	David N. Armstrong, Hyesoon Kim, Onur Mutlu, Yale N. Patt	Wrong Path Events: Exploiting Unusual and Illegal Program Behavior for Early Misprediction Detection and Recovery.	MICRO	2004	DBLP DOI BibTeX RDF
55	Enric Morancho, José María Llabería, Àngel Olivé	Recovery Mechanism for Latency Misprediction.	IEEE PACT	2001	DBLP DOI BibTeX RDF
53	Mohamed M. Zahran, Manoj Franklin	Dynamic Thread Resizing for Speculative Multithreaded Processors.	ICCD	2003	DBLP DOI BibTeX RDF
53	Jared Stark, Marius Evers, Yale N. Patt	Variable Length Path Branch Prediction.	ASPLOS	1998	DBLP DOI BibTeX RDF
42	Srinivas Mantripragada, Alexandru Nicolau	Using profiling to reduce branch misprediction costs on a dynamically scheduled processor.	ICS	2000	DBLP DOI BibTeX RDF
40	Nitya Ranganathan, Doug Burger, Stephen W. Keckler	Analysis of the TRIPS prototype block predictor.	ISPASS	2009	DBLP DOI BibTeX RDF
40	Kenneth A. Ross	Conjunctive Selection Conditions in Main Memory. (PDF / PS)	PODS	2002	DBLP DOI BibTeX RDF
40	Daniel A. Jiménez, Heather L. Hanson, Calvin Lin	Boolean Formula-Based Branch Prediction for Future Technologies.	IEEE PACT	2001	DBLP DOI BibTeX RDF
40	Juan L. Aragón, José González 0002, José M. García 0001, Antonio González 0001	Confidence Estimation for Branch Prediction Reversal.	HiPC	2001	DBLP DOI BibTeX RDF
38	Nicholas Nethercote, Alan Mycroft	The cache behaviour of large lazy functional programs on stock hardware.	MSP/ISMM	2002	DBLP DOI BibTeX RDF	Glasgow Haskell Compiler, cache measurement, Haskell, Haskell, cache simulation, hardware counters, branch misprediction
29	Adrus Mohamad Tazuddin, Azizi Abdullah, Zainal Rasyid Mahayuddin	Hierarchical CNN Automated Hierarchy Creation Using Output Prediction Analysis With Misprediction Matrix.	ICEEI	2023	DBLP DOI BibTeX RDF
29	Jiri Gesi, Xinyun Shen, Yunfan Geng, Qihong Chen, Iftekhar Ahmed 0001	Leveraging Feature Bias for Scalable Misprediction Explanation of Machine Learning Models.	ICSE	2023	DBLP DOI BibTeX RDF
29	Tanvir Ahmed Khan, Muhammed Ugur, Krishnendra Nathella, Dam Sunwoo, Heiner Litz, Daniel A. Jiménez, Baris Kasikci	Whisper: Profile-Guided Branch Misprediction Elimination for Data Center Applications.	MICRO	2022	DBLP DOI BibTeX RDF
29	Michael Mitzenmacher	Scheduling with Predictions and the Price of Misprediction.	ITCS	2020	DBLP DOI BibTeX RDF
29	Lu Yang, Yunhui Huang, Yi-Chun (Chad) Ho, Zhijie Lin	Is online multiple-stores cooperative promotion better than single-store promotion? Misprediction from evaluation mode.	Inf. Manag.	2019	DBLP DOI BibTeX RDF
29	Michael Mitzenmacher	Scheduling with Predictions and the Price of Misprediction.	CoRR	2019	DBLP BibTeX RDF
29	Wolfgang Puffitsch	Persistence-based branch misprediction bounds for WCET analysis.	SAC	2015	DBLP DOI BibTeX RDF
29	Zhaoxiang Jin, Görkem Asilioglu, Soner Önder	Mower: A New Design for Non-blocking Misprediction Recovery.	ICS	2015	DBLP DOI BibTeX RDF
29	Divino Cesar S. Lucas, Rafael Auler, Rafael Dalibera, Sandro Rigo, Edson Borin, Guido Araujo	Modeling virtual machines misprediction overhead.	IISWC	2013	DBLP DOI BibTeX RDF
29	Huatao Zhao, Jiongyao Ye, Yuxin Sun, Takahiro Watanabe	Pseudo Dual Path Processing to reduce the branch misprediction penalty in embedded processors.	ASICON	2013	DBLP DOI BibTeX RDF
29	Jiongyao Ye, Yu Wan 0002, Takahiro Watanabe	A New Recovery Mechanism in Superscalar Microprocessors by Recovering Critical Misprediction.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2011	DBLP DOI BibTeX RDF
29	Jaime Ruiz, Edward Lank	Speeding pointing in tiled widgets: understanding the effects of target expansion and misprediction.	IUI	2010	DBLP DOI BibTeX RDF	target expansion, tiled targets, Fitts' law, pointing, human performance
29	Guan-Ying Chiu, Hui-Chin Yang, Walter Yuan-Hwa Li, Chung-Ping Chung	Mechanism for return stack and branch history corrections under misprediction in deep pipeline design.	ACSAC	2008	DBLP DOI BibTeX RDF
29	Stijn Eyerman, James E. Smith 0001, Lieven Eeckhout	Characterizing the branch misprediction penalty.	ISPASS	2006	DBLP DOI BibTeX RDF
29	Yuan C. Chou, Jason Fung, John Paul Shen	Reducing branch misprediction penalties via dynamic control independence detection.	International Conference on Supercomputing	1999	DBLP DOI BibTeX RDF
29	Ashwini K. Nanda, James O. Bondi, Simonjit Dutta	The Misprediction Recovery Cache.	Int. J. Parallel Program.	1998	DBLP DOI BibTeX RDF
29	Milena Petrovic, Igor Tartalja, Veljko M. Milutinovic	Two Branch Predictor Schemes for Reduction of Misprediction Rate in Conditions of Frequent Context Switches.	SRDS	1998	DBLP DOI BibTeX RDF
29	James E. Pierce	Cache behavior in the presence of speculative execution: The benefits of misprediction.		1995	RDF
26	Gabriel H. Loh, Daniel A. Jiménez	Modulo Path History for the Reduction of Pipeline Overheads in Path-based Neural Branch Predictors.	Int. J. Parallel Program.	2008	DBLP DOI BibTeX RDF	Computer architecture, Branch prediction
26	Sung Woo Chung, Kevin Skadron	On-Demand Solution to Minimize I-Cache Leakage Energy with Maintaining Performance.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF	Low-power design, Microprocessors, Cache memories, Energy-aware systems
26	Hans Vandierendonck, André Seznec	Speculative return address stack management revisited.	ACM Trans. Archit. Code Optim.	2008	DBLP DOI BibTeX RDF	Return address prediction, back-up predictor, corruption detection
26	Tao Li 0006, Lizy Kurian John, Anand Sivasubramaniam, Narayanan Vijaykrishnan, Juan Rubio 0001	OS-Aware Branch Prediction: Improving Microprocessor Control Flow Prediction for Operating Systems.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	branch prediction, processor architectures, Pipeline processors, performance of systems, hardware/software interfaces, computer system implementation
26	C. Y. Ho, Anthony Shi-Sheung Fong	Combining Local and Global History Hashing in Perceptron Branch Prediction.	ACIS-ICIS	2007	DBLP DOI BibTeX RDF
26	Jiajin Tu, Jian Chen 0030, Lizy K. John	Hardware Efficient Piecewise Linear Branch Predictor.	VLSI Design	2007	DBLP DOI BibTeX RDF
26	Sung Woo Chung, Kevin Skadron	Using Branch Prediction Information for Near-Optimal I-Cache Leakage.	Asia-Pacific Computer Systems Architecture Conference	2006	DBLP DOI BibTeX RDF	Low Power, Branch Prediction, Leakage, Instruction Cache, Drowsy Cache
26	Daniel A. Jiménez, Gabriel H. Loh	Controlling the Power and Area of Neural Branch Predictors for Practical Implementation in High-Performance Processors.	SBAC-PAD	2006	DBLP DOI BibTeX RDF
26	Smruti R. Sarangi, Wei Liu, Yuanyuan Zhou	ReSlice: Selective Re-Execution of Long-Retired Misspeculated Instructions Using Forward Slicing.	MICRO	2005	DBLP DOI BibTeX RDF
26	Matteo Monchiero, Gianluca Palermo	The Combined Perceptron Branch Predictor.	Euro-Par	2005	DBLP DOI BibTeX RDF
26	Alex Pajuelo, Antonio González 0001, Mateo Valero	Control-Flow Independence Reuse via Dynamic Vectorization.	IPDPS	2005	DBLP DOI BibTeX RDF
26	Yuanyuan Zhang, Yasushi Inoguchi	Influence of Performance Prediction Inaccuracy on Task Scheduling in Grid Environment.	APWeb	2005	DBLP DOI BibTeX RDF	task selection, processor selection, grid computing, performance prediction, task scheduling
26	Zhigang Hu, Alper Buyuktosunoglu, Viji Srinivasan, Victor V. Zyuban, Hans M. Jacobson, Pradip Bose	Microarchitectural techniques for power gating of execution units.	ISLPED	2004	DBLP DOI BibTeX RDF	execution units, low power, microarchitecture, power-gating
26	Chao-ying Fu, Jill T. Bodine, Thomas M. Conte	Modeling Value Speculation: An Optimal Edge Selection Problem.	IEEE Trans. Computers	2003	DBLP DOI BibTeX RDF	optimal edge selection, critical path reduction, Value prediction, data dependence graph, value speculation
26	Haitham Akkary, Srikanth T. Srinivasan, Konrad Lai	Recycling waste: exploiting wrong-path execution to improve branch prediction.	ICS	2003	DBLP DOI BibTeX RDF	deep pipelines, branch prediction, instruction reuse
26	Weihaw Chuang, Brad Calder	Predicate prediction for efficient out-of-order execution.	ICS	2003	DBLP DOI BibTeX RDF	predicate prediction, predicated execution
26	Timothy Sherwood, Erez Perelman, Brad Calder	Basic Block Distribution Analysis to Find Periodic Behavior and Simulation Points in Applications.	IEEE PACT	2001	DBLP DOI BibTeX RDF
26	Aneesh Aggarwal, Manoj Franklin	Putting Data Value Predictors to Work in Fine-Grain Parallel Processors.	HiPC	2001	DBLP DOI BibTeX RDF
26	Yul Chu, Mabo Robert Ito	An Efficient Indirect Branch Predictor.	Euro-Par	2001	DBLP DOI BibTeX RDF
26	Jayanth Gummaraju, Manoj Franklin	Branch Prediction in Multi-Threaded Processors.	IEEE PACT	2000	DBLP DOI BibTeX RDF
26	Jan Hoogerbrugge	Dynamic Branch Prediction for a VLIW Processor.	IEEE PACT	2000	DBLP DOI BibTeX RDF
26	Steven Wallace, Brad Calder, Dean M. Tullsen	Threaded Multiple Path Execution.	ISCA	1998	DBLP DOI BibTeX RDF
26	Po-Yung Chang, Eric Hao, Yale N. Patt	Target Prediction for Indirect Jumps.	ISCA	1997	DBLP DOI BibTeX RDF
25	Amit Golander, Shlomo Weiss	Checkpoint allocation and release.	ACM Trans. Archit. Code Optim.	2009	DBLP DOI BibTeX RDF	early register release, misprediction, Checkpoint, leakage, out-of-order execution, rollback
25	Andrew D. Hilton, Amir Roth	Ginger: control independence using tag rewriting.	ISCA	2007	DBLP DOI BibTeX RDF	control independence, out-of-order renaming, selective re-dispatch, branch misprediction
25	Patrick Akl, Andreas Moshovos	BranchTap: improving performance with very few checkpoints through adaptive speculation control.	ICS	2006	DBLP DOI BibTeX RDF	speculation control, state checkpointing, state recovery, branch misprediction
13	Muawya Al-Otoom, Elliott Forbes, Eric Rotenberg	EXACT: explicit dynamic-branch prediction with active updates.	Conf. Computing Frontiers	2010	DBLP DOI BibTeX RDF	branch prediction, microarchitecture, superscalar processors
13	Amit Golander, Shlomo Weiss	Reexecution and Selective Reuse in Checkpoint Processors.	Trans. High Perform. Embed. Archit. Compil.	2009	DBLP DOI BibTeX RDF
13	Daniel A. Jiménez	Generalizing neural branch prediction.	ACM Trans. Archit. Code Optim.	2009	DBLP DOI BibTeX RDF	machine learning, Branch prediction
13	Uwe Brinkschulte, Daniel Lohn, Mathias Pacher	Towards a Statistical Model of a Microprocessor's Throughput by Analyzing Pipeline Stalls.	SEUS	2009	DBLP DOI BibTeX RDF
13	Pranav Vaidya, Jaehwan John Lee	Characterization of TPC-H queries for a column-oriented database on a dual-core amd athlon processor.	CIKM	2008	DBLP DOI BibTeX RDF	column-oriented databases, monetdb, tpc-h, performance profiling
13	Michael Ferdman, Thomas F. Wenisch, Anastasia Ailamaki, Babak Falsafi, Andreas Moshovos	Temporal instruction fetch streaming.	MICRO	2008	DBLP DOI BibTeX RDF
13	Kshitiz Malik, Mayank Agarwal, Sam S. Stone, Kevin M. Woley, Matthew I. Frank	Branch-mispredict level parallelism (BLP) for control independence.	HPCA	2008	DBLP DOI BibTeX RDF
13	Hongliang Gao, Yi Ma, Martin Dimitrov, Huiyang Zhou	Address-branch correlation: A novel locality for long-latency hard-to-predict branches.	HPCA	2008	DBLP DOI BibTeX RDF
13	Anthony S. Fong, C. Y. Ho	Global/Local Hashed Perceptron Branch Prediction.	ITNG	2008	DBLP DOI BibTeX RDF	neural networks, hashing, branch prediction, perceptrons
13	Resit Sendag, Joshua J. Yi, Peng-fei Chuang, David J. Lilja	Low power/area branch prediction using complementary branch predictors.	IPDPS	2008	DBLP DOI BibTeX RDF
13	Sounil Biswas, R. D. (Shawn) Blanton	Test Compaction for Mixed-Signal Circuits Using Pass-Fail Test Data.	VTS	2008	DBLP DOI BibTeX RDF	pass-fail test data, boolean minimization, minimum constrained subset cover, Mixed-signal test, test compaction
13	Eui-Young Chung, Cheol Hong Kim, Sung Woo Chung	An Accurate and Energy-Efficient Way Determination Technique for Instruction Caches by Early Tab Matching.	DELTA	2008	DBLP DOI BibTeX RDF	way predictioin, low power, Instruction cache
13	Shijian Zhang, Weiwu Hu	Fetching Primary and Redundant Instructions in Turn for a Fault-Tolerant Embedded Microprocessor.	PRDC	2008	DBLP DOI BibTeX RDF
13	Hyesoon Kim, José A. Joao, Onur Mutlu, Yale N. Patt	Diverge-Merge Processor: Generalized and Energy-Efficient Dynamic Predication.	IEEE Micro	2007	DBLP DOI BibTeX RDF	dynamic predication, adaptivity, energy efficiency, pipelining, instruction level parallelism, branch prediction, predication
13	Hyesoon Kim, José A. Joao, Onur Mutlu, Yale N. Patt	Profile-assisted Compiler Support for Dynamic Predication in Diverge-Merge Processors.	CGO	2007	DBLP DOI BibTeX RDF
13	Eduardo Quiñones, Joan-Manuel Parcerisa, Antonio González 0001	Improving Branch Prediction and Predicated Execution in Out-of-Order Processors.	HPCA	2007	DBLP DOI BibTeX RDF
13	Yefim Shuf, Ian M. Steiner	Characterizing a Complex J2EE Workload: A Comprehensive Analysis and Opportunities for Optimizations.	ISPASS	2007	DBLP DOI BibTeX RDF	J2EE workload, Java benchmarks, SPECjvm98, SPECjbb2000, Java 2 Enterprise Edition, SPECjAppServer2004, systems research, software research, cache-to-cache modified data transfers, intelligent thread co-scheduling, Java heap, bursty data cache, Java virtual method calls, optimizations, performance analysis, garbage collection, instruction cache, data prefetching, commercial workload
13	Mojtaba Shakeri, Abolfazl Toroghi Haghighat, Mohammad K. Akbari	Modeling and Evaluating the Scalability of Instruction Fetching in Superscalar Processors.	ITNG	2007	DBLP DOI BibTeX RDF
13	Haralampos-G. D. Stratigopoulos, Petros Drineas, Mustapha Slamani, Yiorgos Makris	Non-RF to RF Test Correlation Using Learning Machines: A Case Study.	VTS	2007	DBLP DOI BibTeX RDF
13	Troy A. Johnson, Rudolf Eigenmann, T. N. Vijaykumar	Speculative thread decomposition through empirical optimization.	PPoPP	2007	DBLP DOI BibTeX RDF	empirical search, chip multiprocessor, decomposition, multi-core, thread-level speculation
13	Dawei Liu, Shan Wang 0001, Biao Qin, Weiwei Gong	Characterizing DSS Workloads from the Processor Perspective.	APWeb/WAIM Workshops	2007	DBLP DOI BibTeX RDF
13	Huiyang Zhou	A case for fault tolerance and performance enhancement using chip multi-processors.	IEEE Comput. Archit. Lett.	2006	DBLP DOI BibTeX RDF
13	Ram Srinivasan, Jeanine E. Cook, Olaf M. Lubeck	Performance modeling using Monte Carlo simulation.	IEEE Comput. Archit. Lett.	2006	DBLP DOI BibTeX RDF
13	Hyesoon Kim, Onur Mutlu, Yale N. Patt, Jared Stark	Wish Branches: Enabling Adaptive and Aggressive Predicated Execution.	IEEE Micro	2006	DBLP DOI BibTeX RDF	Wish branches, wish loops, branch prediction, predicated execution
13	Babak Salamat, Amirali Baniasadi, Kaveh Jokar Deris	Area-Aware Optimizations for Resource Contrained Branch Predictors Exploited in Embedded Processors.	ICSAMOS	2006	DBLP DOI BibTeX RDF
13	Xin Fu, James Poe, Tao Li, José A. B. Fortes	Characterizing Microarchitecture Soft Error Vulnerability Phase Behavior.	MASCOTS	2006	DBLP DOI BibTeX RDF
13	Oswaldo Cadenas, Graham M. Megson	Verification and FPGA Circuits of a Block-2 Fast Path-Based Predictor.	FPL	2006	DBLP DOI BibTeX RDF
13	Ian M. Steiner, Yefim Shuf	A characterization of a java-based commercial workload on a high-end enterprise server.	SIGMETRICS/Performance	2006	DBLP DOI BibTeX RDF	object co-allocation, Java, locality, garbage collection, memory management, JVM, memory allocation, run-time systems, object placement
13	Berkin Özisikyilmaz, Ramanathan Narayanan, Joseph Zambreno, Gokhan Memik, Alok N. Choudhary	An Architectural Characterization Study of Data Mining and Bioinformatics Workloads.	IISWC	2006	DBLP DOI BibTeX RDF
13	Yong Xiao, Xing-Ming Zhou	Performance Evaluation of Data Value Prediction Schemes.	J. Comput. Sci. Technol.	2005	DBLP DOI BibTeX RDF	data value predictors, simulation, performance impact
13	Huiyang Zhou, Thomas M. Conte	Enhancing Memory-Level Parallelism via Recovery-Free Value Prediction.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	Single data stream architectures
13	Emre Özer 0001, Thomas M. Conte	High-Performance and Low-Cost Dual-Thread VLIW Processor Using Weld Architecture Paradigm.	IEEE Trans. Parallel Distributed Syst.	2005	DBLP DOI BibTeX RDF	Multithreaded processors, VLIW architectures, modeling of computer architecture
13	Babak Salamat, Amirali Baniasadi	Area-Aware Pipeline Gating for Embedded Processors.	PATMOS	2005	DBLP DOI BibTeX RDF
13	François Bodin, Isabelle Puaut	A WCET-Oriented Static Branch Prediction Scheme for Real Time Systems.	ECRTS	2005	DBLP DOI BibTeX RDF
13	Hyesoon Kim, Onur Mutlu, Jared Stark, Yale N. Patt	Wish Branches: Combining Conditional Branching and Predication for Adaptive Predicated Execution.	MICRO	2005	DBLP DOI BibTeX RDF